Show patches with: Submitter = Lehua Ding       |    State = Action Required       |    Archived = No       |   119 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[4/4] lra: Apply DF_LIVE_SUBREG data Add DF_LIVE_SUBREG data and apply to IRA and LRA - - - -1- 2024-02-03 Lehua Ding Unresolved
[3/4] ira: Apply DF_LIVE_SUBREG data Add DF_LIVE_SUBREG data and apply to IRA and LRA - - - -1- 2024-02-03 Lehua Ding Unresolved
x86: Make testcase apx-spill_to_egprs-1.c more robust x86: Make testcase apx-spill_to_egprs-1.c more robust - - - -1- 2023-11-14 Lehua Ding Unresolved
[V3,7/7] lra: Support subreg live range track and conflict detect ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[V3,6/7] lra: Switch to live_subreg data flow ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[V3,5/7] ira: Add all nregs >= 2 pseudos to tracke subreg list ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[V3,4/7] ira: Support subreg copy ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[V3,3/7] ira: Support subreg live range track ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[V3,2/7] ira: Switch to live_subreg data ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[V2,5/7] ira: Add all nregs >= 2 pseudos to tracke subreg list ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[V2,3/7] ira: Support subreg live range track ira/lra: Support subreg coalesce - - - -1- 2023-11-12 Lehua Ding Unresolved
[5/7] ira: Add all nregs >= 2 pseudos to tracke subreg list ira/lra: Support subreg coalesce - - - -1- 2023-11-08 Lehua Ding Unresolved
[4/7] ira: Support subreg copy ira/lra: Support subreg coalesce - - - -1- 2023-11-08 Lehua Ding Unresolved
[3/7] ira: Support subreg live range track ira/lra: Support subreg coalesce - - - -1- 2023-11-08 Lehua Ding Unresolved
[1/7] ira: Refactor the handling of register conflicts to make it more general ira/lra: Support subreg coalesce - - - -1- 2023-11-08 Lehua Ding Unresolved
RISC-V: Fixed failed rvv combine testcases RISC-V: Fixed failed rvv combine testcases - - - -1- 2023-11-07 Lehua Ding Unresolved
RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond - - - -1- 2023-10-31 Lehua Ding Unresolved
[V3,11/11] RISC-V: P11: Adjust and add testcases Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,10/11] RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,09/11] RISC-V: P9: Cleanup and reorganize helper functions Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,08/11] RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,07/11] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,06/11] RISC-V: P6: Add computing reaching definition data flow Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,05/11] RISC-V: P5: Combine phase 1 and 2 Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,04/11] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,03/11] RISC-V: P3: Refactor vector_infos_manager Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,02/11] RISC-V: P2: Refactor and cleanup demand system Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V3,01/11] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info/vector_block_info Refactor and cleanup vsetvl pass - - - -1- 2023-10-19 Lehua Ding Unresolved
[V2,14/14] RISC-V: P14: Adjust and add testcases Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,13/14] RISC-V: P13: Reorganize functions used to modify RTL Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,12/14] RISC-V: P12: Delete riscv-vsetvl.h Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,11/14] RISC-V: P11: Adjust vector_block_info to vsetvl_block_info class Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,10/14] RISC-V: P10: Cleanup helper functions Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,09/14] RISC-V: P9: Cleanup post optimize phase Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,08/14] RISC-V: P8: Unified insert and delete of vsetvl insn into Phase 4 Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,07/14] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,06/14] RISC-V: P6: Add computing reaching definition data flow Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,05/14] RISC-V: P5: combine phase 1 and 2 Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,04/14] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,03/14] RISC-V: P3: Refactor vector_infos_manager Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,02/14] RISC-V: P2: Refactor and cleanup demand system Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
[V2,01/14] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info Refactor and cleanup vsetvl pass - - - -1- 2023-10-17 Lehua Ding Unresolved
RISC-V: Fix failed testcase when use -cmodel=medany RISC-V: Fix failed testcase when use -cmodel=medany - - - -1- 2023-10-17 Lehua Ding Unresolved
[COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-22 Lehua Ding Unresolved
[COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type [COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type - - - -1- 2023-09-22 Lehua Ding Unresolved
[V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f… [V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f… - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… - - - -1- 2023-09-21 Lehua Ding Unresolved
[V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names - - - -1- 2023-09-21 Lehua Ding Unresolved
[2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases [1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op - - - -1- 2023-09-20 Lehua Ding Unresolved
[V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-20 Lehua Ding Unresolved
RISC-V: Reorganize and rename combine patterns in autovec-opt.md RISC-V: Reorganize and rename combine patterns in autovec-opt.md - - - -1- 2023-09-20 Lehua Ding Unresolved
RISC-V: Fixed ICE caused by missing operand RISC-V: Fixed ICE caused by missing operand - - - -1- 2023-09-20 Lehua Ding Unresolved
RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum - - - -1- 2023-09-18 Lehua Ding Unresolved
RISC-V: Removed misleading comments in testcases RISC-V: Removed misleading comments in testcases - - - -1- 2023-09-18 Lehua Ding Unresolved
RISC-V: Refactor and cleanup fma patterns RISC-V: Refactor and cleanup fma patterns - - - -1- 2023-09-18 Lehua Ding Unresolved
RISC-V: Fix using wrong mode to get reduction insn vlmax RISC-V: Fix using wrong mode to get reduction insn vlmax - - - -1- 2023-09-15 Lehua Ding Unresolved
RISC-V: Refactor expand_reduction and cleanup enum reduction_type RISC-V: Refactor expand_reduction and cleanup enum reduction_type - - - -1- 2023-09-15 Lehua Ding Unresolved
RISC-V: Support combine extend and reduce sum to widen reduce sum RISC-V: Support combine extend and reduce sum to widen reduce sum - - - -1- 2023-09-14 Lehua Ding Unresolved
[2/2] RISC-V: Refactor vector reduction patterns [1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode - - - -1- 2023-09-13 Lehua Ding Unresolved
[1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode [1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode - - - -1- 2023-09-13 Lehua Ding Unresolved
RISC-V: Support cond vmulh.vv and vmulu.vv RISC-V: Support cond vmulh.vv and vmulu.vv - - - -1- 2023-09-12 Lehua Ding Unresolved
RISC-V: Support cond vnsrl/vnsra RISC-V: Support cond vnsrl/vnsra - - - -1- 2023-09-12 Lehua Ding Unresolved
RISC-V: Support cond vfsgnj.vv autovec pattern RISC-V: Support cond vfsgnj.vv autovec pattern - - - -1- 2023-09-12 Lehua Ding Unresolved
RISC-V: Add missed cond autovec testcases RISC-V: Add missed cond autovec testcases - - - -1- 2023-09-12 Lehua Ding Unresolved
[V3] Support folding min(poly,poly) to const [V3] Support folding min(poly,poly) to const - - - -1- 2023-09-08 Lehua Ding Unresolved
[V2] Support folding min(poly,poly) to const [V2] Support folding min(poly,poly) to const - - - -1- 2023-09-08 Lehua Ding Unresolved
Support folding min(poly,poly) to const Support folding min(poly,poly) to const - - - -1- 2023-09-08 Lehua Ding Unresolved
[V5,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - -1- 2023-09-05 Lehua Ding Unresolved
[V5,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - -1- 2023-09-05 Lehua Ding Unresolved
[V5,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - -1- 2023-09-05 Lehua Ding Unresolved
RISC-V: Keep vlmax vector operators in simple form until split1 pass RISC-V: Keep vlmax vector operators in simple form until split1 pass - - - -1- 2023-09-04 Lehua Ding Unresolved
RISC-V: Add conditional sqrt autovec pattern RISC-V: Add conditional sqrt autovec pattern - - - -1- 2023-09-04 Lehua Ding Unresolved
[4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[V4,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
[V4,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
[V4,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
RISC-V: Change vsetvl tail and mask policy to default policy RISC-V: Change vsetvl tail and mask policy to default policy - - - -1- 2023-08-31 Lehua Ding Unresolved
RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions - - - -1- 2023-08-30 Lehua Ding Unresolved
RISC-V: Fix vsetvl pass ICE RISC-V: Fix vsetvl pass ICE - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} [V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - -1- 2023-08-29 Lehua Ding Unresolved
[V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} [V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - -1- 2023-08-29 Lehua Ding Unresolved
[COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern [COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern - - - -1- 2023-08-29 Lehua Ding Unresolved
RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - -1- 2023-08-25 Lehua Ding Unresolved
[V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns [V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns - - - -1- 2023-08-25 Lehua Ding Unresolved
RISC-V: Add conditional autovec convert(INT<->FP) patterns RISC-V: Add conditional autovec convert(INT<->FP) patterns - - - -1- 2023-08-24 Lehua Ding Unresolved
RISC-V: Add conditional convert autovec patterns between FPs RISC-V: Add conditional convert autovec patterns between FPs - - - -1- 2023-08-23 Lehua Ding Unresolved
RISC-V: Add conditional sign/zero extension and truncation autovec patterns RISC-V: Add conditional sign/zero extension and truncation autovec patterns - - - -1- 2023-08-23 Lehua Ding Unresolved
[V2] RISC-V: Add conditional unary neg/abs/not autovec patterns [V2] RISC-V: Add conditional unary neg/abs/not autovec patterns - - - -1- 2023-08-23 Lehua Ding Unresolved
RISC-V: Add conditional unary neg/abs/not autovec patterns RISC-V: Add conditional unary neg/abs/not autovec patterns - - - -1- 2023-08-22 Lehua Ding Unresolved
RISC-V: Change fnms testcases assertion to xfail RISC-V: Change fnms testcases assertion to xfail - - - -1- 2023-08-22 Lehua Ding Unresolved
RISC-V: Fix -march error of zhinxmin testcases RISC-V: Fix -march error of zhinxmin testcases - - - -1- 2023-08-18 Lehua Ding Unresolved
[V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl [V2] RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl - - - -1- 2023-08-17 Lehua Ding Unresolved
RISC-V: Fix XPASS slp testcases RISC-V: Fix XPASS slp testcases - - - -1- 2023-08-17 Lehua Ding Unresolved
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