Show patches with: Archived = No       |   15942 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[05/13,APX,EGPR] Add register and memory constraints that disallow EGPR Support Intel APX EGPR - - - -1- 2023-09-22 Hongyu Wang Unresolved
[04/13,APX,EGPR] Add 16 new integer general purpose registers Support Intel APX EGPR - - - -1- 2023-09-22 Hongyu Wang Unresolved
[03/13,APX_EGPR] Initial support for APX_F Support Intel APX EGPR - - - -1- 2023-09-22 Hongyu Wang Unresolved
[02/13,APX,EGPR] middle-end: Add index_reg_class with insn argument. Support Intel APX EGPR - - - 1-- 2023-09-22 Hongyu Wang Accepted
[01/13,APX,EGPR] middle-end: Add insn argument to base_reg_class Support Intel APX EGPR - - - 1-- 2023-09-22 Hongyu Wang Accepted
light expander sra light expander sra - - - 1-- 2023-09-22 Jiufu Guo Accepted
[v1] RISC-V: Move ceil test cases to unop folder [v1] RISC-V: Move ceil test cases to unop folder - - - --1 2023-09-22 Li, Pan2 Not Applicable
[Committed] RISC-V: Remove @ of vec_duplicate pattern [Committed] RISC-V: Remove @ of vec_duplicate pattern - - - -1- 2023-09-22 juzhe.zhong@rivai.ai Unresolved
[2/3] recog: Support space in "[ cons" [1/3] recog: Improve parser for pattern new compact syntax - - - -1- 2023-09-22 Andrea Corallo Unresolved
[1/3] recog: Improve parser for pattern new compact syntax [1/3] recog: Improve parser for pattern new compact syntax - - - -1- 2023-09-22 Andrea Corallo Unresolved
RISC-V: Add VLS conditional patterns support RISC-V: Add VLS conditional patterns support - - - -1- 2023-09-22 juzhe.zhong@rivai.ai Unresolved
[2/2] RISC-V: Fix ICE by expansion and register coercion RISC-V: Define not broken prefetch builtins - - - -1- 2023-09-22 Tsukasa OI Unresolved
[1/2] RISC-V: Define not broken prefetch builtins RISC-V: Define not broken prefetch builtins - - - -1- 2023-09-22 Tsukasa OI Unresolved
[v1] RISCV-V: Suport FP floor auto-vectorization [v1] RISCV-V: Suport FP floor auto-vectorization - - - -1- 2023-09-22 Li, Pan2 Unresolved
[v1] RISC-V: Rename the test macro for math autovec test [v1] RISC-V: Rename the test macro for math autovec test - - - -1- 2023-09-22 Li, Pan2 Unresolved
[v1] RISC-V: Remove arch and abi option for run test case. [v1] RISC-V: Remove arch and abi option for run test case. - - - -1- 2023-09-22 Li, Pan2 Unresolved
[COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [COMMITTED,V4] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-22 Lehua Ding Unresolved
[COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type [COMMITTED] RISC-V: Split VLS avl_type from NONVLMAX avl_type - - - -1- 2023-09-22 Lehua Ding Unresolved
[V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] [V2] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] - - - -1- 2023-09-22 Li Xu Unresolved
RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] RISC-V: Optimization of vrgather.vv into vrgatherei16.vv[PR111451] - - - -1- 2023-09-22 Li Xu Unresolved
[v1] RISC-V: Leverage __builtin_xx instead of math.h for test [v1] RISC-V: Leverage __builtin_xx instead of math.h for test - - - -1- 2023-09-22 Li, Pan2 Unresolved
[v4] RISC-V: Support ceil and ceilf auto-vectorization [v4] RISC-V: Support ceil and ceilf auto-vectorization - - - -1- 2023-09-22 Li, Pan2 Unresolved
[Committed] RISC-V: Add VLS integer ABS support [Committed] RISC-V: Add VLS integer ABS support - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
AArch64: Add inline memmove expansion AArch64: Add inline memmove expansion - - - --1 2023-09-21 Wilco Dijkstra Not Applicable
[v3] RISC-V: Support ceil and ceilf auto-vectorization [v3] RISC-V: Support ceil and ceilf auto-vectorization - - - -1- 2023-09-21 Li, Pan2 Unresolved
[v2] AArch64: Fix strict-align cpymem/setmem [PR103100] [v2] AArch64: Fix strict-align cpymem/setmem [PR103100] - - - 1-- 2023-09-21 Wilco Dijkstra Accepted
[v3] c++: Catch indirect change of active union member in constexpr [PR101631] [v3] c++: Catch indirect change of active union member in constexpr [PR101631] - - - 1-- 2023-09-21 Nathaniel Shead Accepted
[Committed] RISC-V: Add more VLS unary tests [Committed] RISC-V: Add more VLS unary tests - - - 1-- 2023-09-21 juzhe.zhong@rivai.ai Accepted
[Committed] RISC-V: Support VLS mult high [Committed] RISC-V: Support VLS mult high - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[v2] RISC-V: Support ceil and ceilf auto-vectorization [v2] RISC-V: Support ceil and ceilf auto-vectorization - - - -1- 2023-09-21 Li, Pan2 Unresolved
[V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f… [V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn f… - - - -1- 2023-09-21 Lehua Ding Unresolved
[3/3,v2] build: Regenerate build files Untitled series #59083 - - - 1-- 2023-09-21 Arthur Cohen Accepted
[wwwdocs] OpenMP: gcc-14/changes.html and projects/gomp/ update [wwwdocs] OpenMP: gcc-14/changes.html and projects/gomp/ update - - - -1- 2023-09-21 Tobias Burnus Unresolved
[3/3] build: Regenerate build files Untitled series #59081 - - - 1-- 2023-09-21 Arthur Cohen Accepted
RISC-V: Enable undefined support for RVV auto-vectorization[PR110751] RISC-V: Enable undefined support for RVV auto-vectorization[PR110751] - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
PHIOPT: Fix minmax_replacement for three way PHIOPT: Fix minmax_replacement for three way - - - 1-- 2023-09-21 Andrew Pinski Accepted
[18/18] Allow -mno-evex512 usage Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[17/18] Support -mevex512 for AVX512FP16 intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[16/18] Support -mevex512 for AVX512{IFMA, VBMI, VNNI, BF16, VPOPCNTDQ, VBMI2, BITALG, VP2INTERSECT… Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[15/18] Support -mevex512 for AVX512BW intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[14/18] Support -mevex512 for AVX512DQ intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[13/18] Support -mevex512 for AVX512F intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[12/18] Disable zmm register and 512 bit libmvec call when !TARGET_EVEX512 Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[11/18,5/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[10/18,4/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[09/18,3/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[08/18,2/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[07/18,1/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[06/18,5/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[05/18,4/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[04/18,3/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[03/18,2/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[01/18] Initial support for -mevex512 Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Fix SUBREG move of VLS mode[PR111486] RISC-V: Fix SUBREG move of VLS mode[PR111486] - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[v2] Re: Introduce -finline-stringops [v2] Re: Introduce -finline-stringops - - - 1-- 2023-09-21 Alexandre Oliva Accepted
[V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Optimized for strided load/store with stride == element width[PR111450] RISC-V: Optimized for strided load/store with stride == element width[PR111450] - - - -1- 2023-09-21 Li Xu Unresolved
MATCH: Simplify `(A ==/!= B) &/| (((cast)A) CMP C)` MATCH: Simplify `(A ==/!= B) &/| (((cast)A) CMP C)` - - - -1- 2023-09-21 Andrew Pinski Unresolved
check undefine_p for one more vr check undefine_p for one more vr - - - -1- 2023-09-21 Jiufu Guo Unresolved
[Committed] RISC-V: Support VLS INT <-> FP conversions [Committed] RISC-V: Support VLS INT <-> FP conversions - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
LoongArch: Optimizations of vector construction. LoongArch: Optimizations of vector construction. - - - -1- 2023-09-21 Guo Jie Unresolved
LoongArch: Optimizations of vector construction. LoongArch: Optimizations of vector construction. - - - -1- 2023-09-21 Guo Jie Unresolved
[COMMITTED] Tweak ssa_cache::merge_range API. [COMMITTED] Tweak ssa_cache::merge_range API. - - - -1- 2023-09-20 Andrew MacLeod Unresolved
c++: constraint rewriting during ttp coercion [PR111485] c++: constraint rewriting during ttp coercion [PR111485] - - - 1-- 2023-09-20 Patrick Palka Accepted
RISC-V: Remove math.h import to resolve missing stubs failures RISC-V: Remove math.h import to resolve missing stubs failures - - 2 -1- 2023-09-20 Patrick O'Neill Unresolved
[v2] AArch64: Fix memmove operand corruption [PR111121] [v2] AArch64: Fix memmove operand corruption [PR111121] - - - 1-- 2023-09-20 Wilco Dijkstra Accepted
[frange] Remove special casing from unordered operators. [frange] Remove special casing from unordered operators. - - - 1-- 2023-09-20 Aldy Hernandez Accepted
[Committed,V4] internal-fn: Support undefined rtx for uninitialized SSA_NAME[PR110751] [Committed,V4] internal-fn: Support undefined rtx for uninitialized SSA_NAME[PR110751] - - - 1-- 2023-09-20 juzhe.zhong@rivai.ai Accepted
c++: missing SFINAE in grok_array_decl [PR111493] c++: missing SFINAE in grok_array_decl [PR111493] - - - 1-- 2023-09-20 Patrick Palka Accepted
ifcvt/vect: Emit COND_ADD for conditional scalar reduction. ifcvt/vect: Emit COND_ADD for conditional scalar reduction. - - - -1- 2023-09-20 Robin Dapp Unresolved
AArch64: Fix strict-align cpymem/setmem [PR103100] AArch64: Fix strict-align cpymem/setmem [PR103100] - - - 1-- 2023-09-20 Wilco Dijkstra Accepted
[2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases [1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op - - - -1- 2023-09-20 Lehua Ding Unresolved
[1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op [1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op - - - 1-- 2023-09-20 Lehua Ding Accepted
[Committed] RISC-V: Support VLS floating-point extend/truncate [Committed] RISC-V: Support VLS floating-point extend/truncate - - - -1- 2023-09-20 juzhe.zhong@rivai.ai Unresolved
[2/3] build: Add libgrust as compilation modules [1/3] librust: Add libproc_macro and build system - - - 1-- 2023-09-20 Arthur Cohen Accepted
[1/3] librust: Add libproc_macro and build system [1/3] librust: Add libproc_macro and build system - - - 1-- 2023-09-20 Arthur Cohen Accepted
Add a GCC Security policy Add a GCC Security policy - - - 1-- 2023-09-20 Siddhesh Poyarekar Accepted
OpenMP: Support accelerated 2D/3D memory copies for AMD GCN OpenMP: Support accelerated 2D/3D memory copies for AMD GCN - - - -1- 2023-09-20 Julian Brown Unresolved
[3/3,og13] OpenMP: Support accelerated 2D/3D memory copies for AMD GCN OpenMP: Accelerated 2D/3D host<->target memory copies - - - -1- 2023-09-20 Julian Brown Unresolved
[2/3,og13] OpenMP, NVPTX: memcpy[23]D bias correction OpenMP: Accelerated 2D/3D host<->target memory copies - - - -1- 2023-09-20 Julian Brown Unresolved
[1/3,og13] OpenMP: Call cuMemcpy2D/cuMemcpy3D for nvptx for omp_target_memcpy_rect OpenMP: Accelerated 2D/3D host<->target memory copies - - - -1- 2023-09-20 Julian Brown Unresolved
[Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS] [Committed] RISC-V: Fix Demand comparison bug[VSETVL PASS] - - - 1-- 2023-09-20 juzhe.zhong@rivai.ai Accepted
[pushed] Darwin: Move checking of the 'shared' driver spec. [pushed] Darwin: Move checking of the 'shared' driver spec. - - - -1- 2023-09-20 Iain Sandoe Unresolved
[2/2] tree-optimization/111489 - raise --param uninit-max-chain-len to 8 [1/2] tree-optimization/111489 - turn uninit limits to params - - - 1-- 2023-09-20 Richard Biener Accepted
[1/2] tree-optimization/111489 - turn uninit limits to params [1/2] tree-optimization/111489 - turn uninit limits to params - - - 1-- 2023-09-20 Richard Biener Accepted
[rs6000] Enable vector compare for 16-byte memory equality compare [PR111449] [rs6000] Enable vector compare for 16-byte memory equality compare [PR111449] - - - 1-- 2023-09-20 HAO CHEN GUI Accepted
[V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-20 Lehua Ding Unresolved
middle-end: use MAX_FIXED_MODE_SIZE instead of precidion of TImode/DImode middle-end: use MAX_FIXED_MODE_SIZE instead of precidion of TImode/DImode - - - -1- 2023-09-20 Jakub Jelinek Unresolved
c, c++, v3: Accept __builtin_classify_type (typename) c, c++, v3: Accept __builtin_classify_type (typename) - - - -1- 2023-09-20 Jakub Jelinek Unresolved
[fortran] PR68155 - ICE on initializing character array in type (len_lhs <> len_rhs) [fortran] PR68155 - ICE on initializing character array in type (len_lhs <> len_rhs) - - - 1-- 2023-09-20 Paul Richard Thomas Accepted
RISC-V: Reorganize and rename combine patterns in autovec-opt.md RISC-V: Reorganize and rename combine patterns in autovec-opt.md - - - -1- 2023-09-20 Lehua Ding Unresolved
[committed] openmp: Add omp::decl attribute support [PR111392] [committed] openmp: Add omp::decl attribute support [PR111392] - - - -1- 2023-09-20 Jakub Jelinek Unresolved
[v5] Introduce attribute sym_alias (was: Last call for bikeshedding on attribute sym/exalias/revers… [v5] Introduce attribute sym_alias (was: Last call for bikeshedding on attribute sym/exalias/revers… - - - -1- 2023-09-20 Alexandre Oliva Unresolved
RISC-V: Fixed ICE caused by missing operand RISC-V: Fixed ICE caused by missing operand - - - -1- 2023-09-20 Lehua Ding Unresolved
[_GLIBCXX_INLINE_VERSION] Fix <contracts> [_GLIBCXX_INLINE_VERSION] Fix <contracts> - - - 1-- 2023-09-20 François Dumont Accepted
libcpp: Improve the diagnostic for poisoned identifiers [PR36887] libcpp: Improve the diagnostic for poisoned identifiers [PR36887] - - - -1- 2023-09-20 Lewis Hyatt Unresolved
RISC-V: Support simplifying x/(-1) to neg for vector. RISC-V: Support simplifying x/(-1) to neg for vector. - - - 1-- 2023-09-20 Wang, Yanzhang Accepted
[v1] RISC-V: Support ceil and ceilf auto-vectorization [v1] RISC-V: Support ceil and ceilf auto-vectorization - - - -1- 2023-09-20 Li, Pan2 Unresolved
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