Show patches with: State = Action Required       |    Archived = No       |   8194 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Add vec_extract for BI -> QI. RISC-V: Add vec_extract for BI -> QI. - - - -1- 2023-09-01 Robin Dapp Unresolved
[4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Add conditional autovec convert patterns - - - -1- 2023-09-01 Lehua Ding Unresolved
[v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode [v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode - - - -1- 2023-09-01 Li, Pan2 via Gcc-patches Unresolved
RISC-V: Enable VECT_COMPARE_COSTS by default RISC-V: Enable VECT_COMPARE_COSTS by default - - - -1- 2023-08-31 juzhe.zhong@rivai.ai Unresolved
Add Types to Un-Typed Pic Instructions: Add Types to Un-Typed Pic Instructions: - - - -1- 2023-08-31 Edwin Lu Unresolved
c++, v3: Fix up mangling of function/block scope static structured bindings and emit abi tags [PR11… c++, v3: Fix up mangling of function/block scope static structured bindings and emit abi tags [PR11… - - - -1- 2023-08-31 Jakub Jelinek Unresolved
RISC-V: Add Types to Un-Typed Risc-v Instructions: RISC-V: Add Types to Un-Typed Risc-v Instructions: - - - -1- 2023-08-31 Edwin Lu Unresolved
lra: Avoid unfolded plus-0 lra: Avoid unfolded plus-0 - - - -1- 2023-08-31 Richard Sandiford Unresolved
[v3,4/4] LoongArch: support loongarch*-elf target LoongArch: target configuration interface update - - - -1- 2023-08-31 Yang Yujie Unresolved
[v3,3/4] LoongArch: add new configure option --with-strict-align-lib LoongArch: target configuration interface update - - - -1- 2023-08-31 Yang Yujie Unresolved
[v3,2/4] LoongArch: define preprocessing macros "__loongarch_{arch, tune}" LoongArch: target configuration interface update - - - -1- 2023-08-31 Yang Yujie Unresolved
[v3,1/4] LoongArch: improved target configuration interface LoongArch: target configuration interface update - - - -1- 2023-08-31 Yang Yujie Unresolved
[V4,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
[V4,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
[V4,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-31 Lehua Ding Unresolved
RISC-V: Add Vector cost model framework for RVV RISC-V: Add Vector cost model framework for RVV - - - -1- 2023-08-31 juzhe.zhong@rivai.ai Unresolved
Fix gcc.dg/tree-ssa/forwprop-42.c Fix gcc.dg/tree-ssa/forwprop-42.c - - - -1- 2023-08-31 Richard Biener Unresolved
RISC-V: Change vsetvl tail and mask policy to default policy RISC-V: Change vsetvl tail and mask policy to default policy - - - -1- 2023-08-31 Lehua Ding Unresolved
[13/13,APX,EGPR] Handle vex insns that only support GPR16 (5/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[12/13,APX_EGPR] Handle legacy insns that only support GPR16 (4/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[11/13,APX,EGPR] Handle legacy insns that only support GPR16 (3/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[10/13,APX,EGPR] Handle legacy insns that only support GPR16 (2/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[09/13,APX,EGPR] Handle legacy insn that only support GPR16 (1/5) Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[08/13,APX,EGPR] Handle GPR16 only vector move insns Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[07/13,APX,EGPR] Add backend hook for base_reg_class/index_reg_class. Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[06/13,APX,EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint. Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[05/13,APX,EGPR] Add register and memory constraints that disallow EGPR Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[04/13,APX,EGPR] Add 16 new integer general purpose registers Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[03/13,APX_EGPR] Initial support for APX_F Support Intel APX EGPR - - - -1- 2023-08-31 Hongyu Wang Unresolved
[RFC] c++: Diagnose [basic.scope.block]/2 violations even for block externs [PR52953] [RFC] c++: Diagnose [basic.scope.block]/2 violations even for block externs [PR52953] - - - -1- 2023-08-31 Jakub Jelinek Unresolved
c++: Diagnose [basic.scope.block]/2 violations even in compound-stmt of function-try-block [PR52953] c++: Diagnose [basic.scope.block]/2 violations even in compound-stmt of function-try-block [PR52953] - - - -1- 2023-08-31 Jakub Jelinek Unresolved
[2/2] c++: Extended diagnostics for P0847R7 (Deducing This) [PR102609] Untitled series #56768 - - - -1- 2023-08-31 waffl3x Unresolved
[2/2,RISC-V] Enalble zcmp for -Os resolve confilct between zcmp multi push/pop and shrink-wrap-separate - - - -1- 2023-08-31 Fei Gao Unresolved
[1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609] [1/2] c++: Initial support for P0847R7 (Deducing This) [PR102609] - - - -1- 2023-08-31 waffl3x Unresolved
[v2] RISC-V: Optimize the MASK opt generation [v2] RISC-V: Optimize the MASK opt generation - - - -1- 2023-08-31 Feng Wang Unresolved
[RFC,v2,1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support - - - -1- 2023-08-30 Tsukasa OI Unresolved
MATCH: extend min_value/max_value match to vectors MATCH: extend min_value/max_value match to vectors - - - -1- 2023-08-30 Andrew Pinski Unresolved
RISC-V: zicond: remove bogus opt2 pattern RISC-V: zicond: remove bogus opt2 pattern - - - -1- 2023-08-30 Vineet Gupta Unresolved
[V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V6] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions RISC-V: Refactor and clean emit_{vlmax, nonvlmax}_xxx functions - - - -1- 2023-08-30 Lehua Ding Unresolved
test: Adapt slp-26.c check for RVV test: Adapt slp-26.c check for RVV - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
[v3,4/4] ifcvt: Remove obsolete code for subreg handling in noce_convert_multiple_sets ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets - - - -1- 2023-08-30 Manolis Tsamis Unresolved
[v3,3/4] ifcvt: Handle multiple rewired regs and refactor noce_convert_multiple_sets ifcvt: Allow if conversion of arithmetic in basic blocks with multiple sets - - - -1- 2023-08-30 Manolis Tsamis Unresolved
RISC-V: Fix vsetvl pass ICE RISC-V: Fix vsetvl pass ICE - - - -1- 2023-08-30 Lehua Ding Unresolved
Refactor vector HF/BF mode iterators and patterns. Refactor vector HF/BF mode iterators and patterns. - - - -1- 2023-08-30 liuhongt Unresolved
tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914] tree-ssa-strlen: Fix up handling of conditionally zero memcpy [PR110914] - - - -1- 2023-08-30 Jakub Jelinek Unresolved
[V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V5] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
store-merging: Fix up >= 64 bit insertion [PR111015] store-merging: Fix up >= 64 bit insertion [PR111015] - - - -1- 2023-08-30 Jakub Jelinek Unresolved
[RFC] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support [RFC] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support - - - -1- 2023-08-30 Tsukasa OI Unresolved
RISC-V: Make sure we get VL REG operand for VLMAX vsetvl RISC-V: Make sure we get VL REG operand for VLMAX vsetvl - - - -1- 2023-08-30 juzhe.zhong@rivai.ai Unresolved
[v2,4/4] LoongArch: support loongarch*-elf target LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[v2,3/4] LoongArch: add new configure option --with-strict-align-lib LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[v2,2/4] LoongArch: define preprocessing macros "__loongarch_{arch, tune}" LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[v2,1/4] LoongArch: improved target configuration interface LoongArch: target configuration interface update - - - -1- 2023-08-30 Yang Yujie Unresolved
[V3,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[V3,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns RISC-V: Add an experimental vector calling convention - - - -1- 2023-08-30 Lehua Ding Unresolved
[committed] RISC-V: Use splitter to generate zicond in another case [committed] RISC-V: Use splitter to generate zicond in another case - - - -1- 2023-08-29 Jeff Law Unresolved
[pushed] analyzer: new warning: -Wanalyzer-overlapping-buffers [PR99860] [pushed] analyzer: new warning: -Wanalyzer-overlapping-buffers [PR99860] - - - -1- 2023-08-29 David Malcolm Unresolved
analyzer: implement reference count checking for CPython plugin [PR107646] analyzer: implement reference count checking for CPython plugin [PR107646] - - - -1- 2023-08-29 Eric Feng Unresolved
OpenMP (C only): omp allocate - handle stack vars, improve diagnostic OpenMP (C only): omp allocate - handle stack vars, improve diagnostic - - - -1- 2023-08-29 Tobias Burnus Unresolved
[pushed] analyzer: improve strdup handling [PR105899] [pushed] analyzer: improve strdup handling [PR105899] - - - -1- 2023-08-29 David Malcolm Unresolved
RISC-V: Enable movmisalign for VLS modes RISC-V: Enable movmisalign for VLS modes - - - -1- 2023-08-29 juzhe.zhong@rivai.ai Unresolved
[3/3,V2,RISC-V] support cm.mva01s cm.mvsa01 in zcmp support zcmp extension - - - -1- 2023-08-29 Fei Gao Unresolved
[2/3,V2,RISC-V] support cm.popretz in zcmp support zcmp extension - - - -1- 2023-08-29 Fei Gao Unresolved
[1/3,V6,RISC-V] support cm.push cm.pop cm.popret in zcmp support zcmp extension - - - -1- 2023-08-29 Fei Gao Unresolved
tree-ssa-math-opts: Improve uaddc/usubc pattern matching [PR111209] tree-ssa-math-opts: Improve uaddc/usubc pattern matching [PR111209] - - - -1- 2023-08-29 Jakub Jelinek Unresolved
RISC-V: Added zvfh support for zfa extensions. RISC-V: Added zvfh support for zfa extensions. - - - -1- 2023-08-29 Jin Ma Unresolved
[V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} [V3] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - -1- 2023-08-29 Lehua Ding Unresolved
[V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} [V2] RISC-V: Refactor and clean expand_cond_len_{unop, binop, ternop} - - - -1- 2023-08-29 Lehua Ding Unresolved
[1/1] RISC-V: Imply 'Zicsr' from 'Zcmt' RISC-V: Imply 'Zicsr' from 'Zcmt' - - - -1- 2023-08-29 Tsukasa OI Unresolved
[v3,3/3] RISC-V: Add stub support for existing extensions (unprivileged) RISC-V: Add stub support for existing extensions - - - -1- 2023-08-29 Tsukasa OI Unresolved
[v3,2/3] RISC-V: Add stub support for existing extensions (vendor) RISC-V: Add stub support for existing extensions - - - -1- 2023-08-29 Tsukasa OI Unresolved
[v3,1/3] RISC-V: Add stub support for existing extensions (privileged) RISC-V: Add stub support for existing extensions - - - -1- 2023-08-29 Tsukasa OI Unresolved
RISC-V: Make arch-24.c to test "success" case RISC-V: Make arch-24.c to test "success" case - - - -1- 2023-08-29 Tsukasa OI Unresolved
RISC-V: Fix ASM check of vlmax_switch_vtype-16.c RISC-V: Fix ASM check of vlmax_switch_vtype-16.c - - - -1- 2023-08-29 juzhe.zhong@rivai.ai Unresolved
[COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern [COMMITTED,V3] RISC-V: Fix error combine of pred_mov pattern - - - -1- 2023-08-29 Lehua Ding Unresolved
RISC-V: Fix AVL/VL get ICE[VSETVL PASS] RISC-V: Fix AVL/VL get ICE[VSETVL PASS] - - - -1- 2023-08-29 juzhe.zhong@rivai.ai Unresolved
Fix cond-bool-2.c on powerpc and other targets Fix cond-bool-2.c on powerpc and other targets - - - -1- 2023-08-28 Andrew Pinski Unresolved
RISC-V: Add Types to Un-Typed Vector Instructions: RISC-V: Add Types to Un-Typed Vector Instructions: - - - -1- 2023-08-28 Edwin Lu Unresolved
[RFC] > WIDE_INT_MAX_PREC support in wide-int [RFC] > WIDE_INT_MAX_PREC support in wide-int - - - -1- 2023-08-28 Jakub Jelinek Unresolved
libcpp, v2: Small incremental patch for P1854R4 [PR110341] libcpp, v2: Small incremental patch for P1854R4 [PR110341] - - - -1- 2023-08-28 Jakub Jelinek Unresolved
c++, v2: Fix up mangling of function/block scope static structured bindings and emit abi tags [PR11… c++, v2: Fix up mangling of function/block scope static structured bindings and emit abi tags [PR11… - - - -1- 2023-08-28 Jakub Jelinek Unresolved
[V4] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V4] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix uninitialized probability for GIMPLE IR tests RISC-V: Fix uninitialized probability for GIMPLE IR tests - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V3] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Disable user vsetvl fusion into EMPTY or DIRTY (Polluted EMPTY) block [V2] RISC-V: Disable user vsetvl fusion into EMPTY or DIRTY (Polluted EMPTY) block - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disable user vsetvl fusion into EMPTY block RISC-V: Disable user vsetvl fusion into EMPTY block - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[2/2,V5,RISC-V] support cm.push cm.pop cm.popret in zcmp and resolve confilct with shrink-wrap-sepa… support cm.push cm.pop cm.popret in zcmp and resolve confilct with shrink-wrap-separate - - - -1- 2023-08-28 Fei Gao Unresolved
[V2] RISC-V: Enable vec_int testsuite for RVV VLA vectorization [V2] RISC-V: Enable vec_int testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[COMMITTED,frange] Handle relations in LTGT_EXPR. [COMMITTED,frange] Handle relations in LTGT_EXPR. - - - -1- 2023-08-28 Aldy Hernandez Unresolved
[v2] LoongArch: Enable '-free' starting at -O2. [v2] LoongArch: Enable '-free' starting at -O2. - - - -1- 2023-08-28 chenglulu Unresolved
[v1] LoongArch: Enable '-free' starting at -O2. [v1] LoongArch: Enable '-free' starting at -O2. - - - -1- 2023-08-28 chenglulu Unresolved
RISC-V: Enable vec_init testsuite for RVV VLA vectorization RISC-V: Enable vec_init testsuite for RVV VLA vectorization - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
RISC-V: Fix VSETVL test failures RISC-V: Fix VSETVL test failures - - - -1- 2023-08-28 juzhe.zhong@rivai.ai Unresolved
[committed] RISC-V: Fix xtheadcondmov-indirect.c [committed] RISC-V: Fix xtheadcondmov-indirect.c - - - -1- 2023-08-27 Jeff Law Unresolved
[C] c: flag for tag compatibility rules [C] c: flag for tag compatibility rules - - - -1- 2023-08-26 Martin Uecker Unresolved
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