Show patches with: Submitter = Edwin Lu       |    State = Action Required       |    Archived = No       |   40 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
RISC-V: Update test expectancies with recent scheduler change RISC-V: Update test expectancies with recent scheduler change - - - -1- 2024-02-23 Edwin Lu Unresolved
[V2] RISC-V: Specify mtune and march for PR113742 [V2] RISC-V: Specify mtune and march for PR113742 - - - -1- 2024-02-20 Edwin Lu Unresolved
[V4,5/5] RISC-V: Enable assert for insn_has_dfa_reservation RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-02-15 Edwin Lu Unresolved
[V4,4/5] RISC-V: Quick and simple fixes to testcases that break due to reordering RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-02-15 Edwin Lu Unresolved
[V4,3/5] RISC-V: Use default cost model for insn scheduling RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-02-15 Edwin Lu Unresolved
[V4,2/5] RISC-V: Add vector related pipelines RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-02-15 Edwin Lu Unresolved
[V4,1/5] RISC-V: Add non-vector types to dfa pipelines RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-02-15 Edwin Lu Unresolved
RISC-V: Set require-effective-target rv64 for PR113742 RISC-V: Set require-effective-target rv64 for PR113742 - - - -1- 2024-02-14 Edwin Lu Unresolved
[V4,2/4] RISC-V: Add vector related pipelines Untitled series #80411 - - - -1- 2024-01-31 Edwin Lu Unresolved
RISC-V: Fix rvv intrinsic pragma tests dejagnu selector RISC-V: Fix rvv intrinsic pragma tests dejagnu selector - 1 - -1- 2024-01-29 Edwin Lu Unresolved
[V3,4/4] RISC-V: Enable assert for insn_has_dfa_reservation RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-12 Edwin Lu Unresolved
[V3,3/4] RISC-V: Use default cost model for insn scheduling RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-12 Edwin Lu Unresolved
[V3,2/4] RISC-V: Add vector related pipelines RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-12 Edwin Lu Unresolved
[V3,1/4] RISC-V: Add non-vector types to dfa pipelines RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-12 Edwin Lu Unresolved
[V2,4/4,RFC] RISC-V: Enable assert for insn_has_dfa_reservation RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-10 Edwin Lu Unresolved
[V2,3/4,RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249 RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-10 Edwin Lu Unresolved
[V2,2/4,RFC] RISC-V: Add vector related reservations RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-10 Edwin Lu Unresolved
[V2,1/4,RFC] RISC-V: Add non-vector types to dfa pipelines RISC-V: Associate typed insns to dfa reservation - - - -1- 2024-01-10 Edwin Lu Unresolved
[3/3,RFC] RISC-V: Enable assert for insn_has_dfa_reservation RISC-V: Associate typed insns to dfa reservation - - - -1- 2023-12-15 Edwin Lu Unresolved
[2/3,RFC] RISC-V: Add vector related reservations RISC-V: Associate typed insns to dfa reservation - - - -1- 2023-12-15 Edwin Lu Unresolved
[1/3,RFC] RISC-V: Add non-vector types to pipelines RISC-V: Associate typed insns to dfa reservation - - - -1- 2023-12-15 Edwin Lu Unresolved
[V3] RISC-V: XFAIL scan dump fails for autovec PR111311 [V3] RISC-V: XFAIL scan dump fails for autovec PR111311 - - - -1- 2023-12-13 Edwin Lu Unresolved
[V2] RISC-V: XFAIL scan dump fails for autovec PR111311 [V2] RISC-V: XFAIL scan dump fails for autovec PR111311 - - - -1- 2023-12-08 Edwin Lu Unresolved
RISC-V: XFAIL scan dump fails for autovec PR111311 RISC-V: XFAIL scan dump fails for autovec PR111311 - - - -1- 2023-12-07 Edwin Lu Unresolved
RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557] - - - -1- 2023-11-15 Edwin Lu Unresolved
RISC-V: Add check for types without insn reservations RISC-V: Add check for types without insn reservations - - - -1- 2023-11-01 Edwin Lu Unresolved
RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert - - - -1- 2023-09-11 Edwin Lu Unresolved
[v2,2/5] RISC-V: Add Types for Un-Typed zc Instructions RISC-V: Add Types to Untyped Instructions - - - -1- 2023-09-08 Edwin Lu Unresolved
[v2,1/5] RISC-V: Update Types for Vector Instructions RISC-V: Add Types to Untyped Instructions - - - -1- 2023-09-08 Edwin Lu Unresolved
[5/5] RISC-V: Remove Assert Protecting Types RISC-V: Add Types to Untyped Instructions - - - -1- 2023-09-06 Edwin Lu Unresolved
[4/5] RISC-V: Update Types for RISC-V Instructions RISC-V: Add Types to Untyped Instructions - - - -1- 2023-09-06 Edwin Lu Unresolved
[3/5] RISC-V: Add Types to Un-Typed Zicond Instructions RISC-V: Add Types to Untyped Instructions - - - -1- 2023-09-06 Edwin Lu Unresolved
[2/5] RISC-V: Add Types for Un-Typed zc Instructions RISC-V: Add Types to Untyped Instructions - - - -1- 2023-09-06 Edwin Lu Unresolved
[1/5] RISC-V: Update Types for Vector Instructions RISC-V: Add Types to Untyped Instructions - - - -1- 2023-09-06 Edwin Lu Unresolved
Add Types to Un-Typed Pic Instructions: Add Types to Un-Typed Pic Instructions: - - - -1- 2023-08-31 Edwin Lu Unresolved
RISC-V: Add Types to Un-Typed Risc-v Instructions: RISC-V: Add Types to Un-Typed Risc-v Instructions: - - - -1- 2023-08-31 Edwin Lu Unresolved
RISC-V: Add Types to Un-Typed Vector Instructions: RISC-V: Add Types to Un-Typed Vector Instructions: - - - -1- 2023-08-28 Edwin Lu Unresolved
[V2] RISC-V: Add Types to Un-Typed Sync Instructions: [V2] RISC-V: Add Types to Un-Typed Sync Instructions: - - - -1- 2023-08-24 Edwin Lu Unresolved
RISC-V: Add Types to Un-Typed Sync Instructions: RISC-V: Add Types to Un-Typed Sync Instructions: - - - -1- 2023-08-21 Edwin Lu Unresolved
RISC-V: Add Types to Missing Bitmanip Instructions: RISC-V: Add Types to Missing Bitmanip Instructions: - - - -1- 2023-08-21 Edwin Lu Unresolved