Show patches with: State = Action Required       |    Archived = No       |   8194 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[17/18] Support -mevex512 for AVX512FP16 intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[16/18] Support -mevex512 for AVX512{IFMA, VBMI, VNNI, BF16, VPOPCNTDQ, VBMI2, BITALG, VP2INTERSECT… Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[15/18] Support -mevex512 for AVX512BW intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[14/18] Support -mevex512 for AVX512DQ intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[13/18] Support -mevex512 for AVX512F intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[12/18] Disable zmm register and 512 bit libmvec call when !TARGET_EVEX512 Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[11/18,5/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[10/18,4/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[09/18,3/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[08/18,2/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[07/18,1/5] Add OPTION_MASK_ISA2_EVEX512 for 512 bit builtins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[06/18,5/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[05/18,4/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[04/18,3/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[03/18,2/5] Push evex512 target for 512 bit intrins Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
[01/18] Initial support for -mevex512 Support -mevex512 for AVX512 - - - -1- 2023-09-21 Hu, Lin1 Unresolved
RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functi… - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Fix SUBREG move of VLS mode[PR111486] RISC-V: Fix SUBREG move of VLS mode[PR111486] - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
[V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V3] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names RISC-V: Rename predicate vector_gs_scale_operand_16/32 to more generic names - - - -1- 2023-09-21 Lehua Ding Unresolved
RISC-V: Optimized for strided load/store with stride == element width[PR111450] RISC-V: Optimized for strided load/store with stride == element width[PR111450] - - - -1- 2023-09-21 Li Xu Unresolved
MATCH: Simplify `(A ==/!= B) &/| (((cast)A) CMP C)` MATCH: Simplify `(A ==/!= B) &/| (((cast)A) CMP C)` - - - -1- 2023-09-21 Andrew Pinski Unresolved
check undefine_p for one more vr check undefine_p for one more vr - - - -1- 2023-09-21 Jiufu Guo Unresolved
[Committed] RISC-V: Support VLS INT <-> FP conversions [Committed] RISC-V: Support VLS INT <-> FP conversions - - - -1- 2023-09-21 juzhe.zhong@rivai.ai Unresolved
LoongArch: Optimizations of vector construction. LoongArch: Optimizations of vector construction. - - - -1- 2023-09-21 Guo Jie Unresolved
LoongArch: Optimizations of vector construction. LoongArch: Optimizations of vector construction. - - - -1- 2023-09-21 Guo Jie Unresolved
[COMMITTED] Tweak ssa_cache::merge_range API. [COMMITTED] Tweak ssa_cache::merge_range API. - - - -1- 2023-09-20 Andrew MacLeod Unresolved
RISC-V: Remove math.h import to resolve missing stubs failures RISC-V: Remove math.h import to resolve missing stubs failures - - 2 -1- 2023-09-20 Patrick O'Neill Unresolved
ifcvt/vect: Emit COND_ADD for conditional scalar reduction. ifcvt/vect: Emit COND_ADD for conditional scalar reduction. - - - -1- 2023-09-20 Robin Dapp Unresolved
[2/2] RISC-V: Add assert of the number of vmerge in autovec cond testcases [1/2] match.pd: Support combine cond_len_op + vec_cond similar to cond_op - - - -1- 2023-09-20 Lehua Ding Unresolved
[Committed] RISC-V: Support VLS floating-point extend/truncate [Committed] RISC-V: Support VLS floating-point extend/truncate - - - -1- 2023-09-20 juzhe.zhong@rivai.ai Unresolved
OpenMP: Support accelerated 2D/3D memory copies for AMD GCN OpenMP: Support accelerated 2D/3D memory copies for AMD GCN - - - -1- 2023-09-20 Julian Brown Unresolved
[3/3,og13] OpenMP: Support accelerated 2D/3D memory copies for AMD GCN OpenMP: Accelerated 2D/3D host<->target memory copies - - - -1- 2023-09-20 Julian Brown Unresolved
[2/3,og13] OpenMP, NVPTX: memcpy[23]D bias correction OpenMP: Accelerated 2D/3D host<->target memory copies - - - -1- 2023-09-20 Julian Brown Unresolved
[1/3,og13] OpenMP: Call cuMemcpy2D/cuMemcpy3D for nvptx for omp_target_memcpy_rect OpenMP: Accelerated 2D/3D host<->target memory copies - - - -1- 2023-09-20 Julian Brown Unresolved
[pushed] Darwin: Move checking of the 'shared' driver spec. [pushed] Darwin: Move checking of the 'shared' driver spec. - - - -1- 2023-09-20 Iain Sandoe Unresolved
[V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum [V2] RISC-V: Support combine cond extend and reduce sum to widen reduce sum - - - -1- 2023-09-20 Lehua Ding Unresolved
middle-end: use MAX_FIXED_MODE_SIZE instead of precidion of TImode/DImode middle-end: use MAX_FIXED_MODE_SIZE instead of precidion of TImode/DImode - - - -1- 2023-09-20 Jakub Jelinek Unresolved
c, c++, v3: Accept __builtin_classify_type (typename) c, c++, v3: Accept __builtin_classify_type (typename) - - - -1- 2023-09-20 Jakub Jelinek Unresolved
RISC-V: Reorganize and rename combine patterns in autovec-opt.md RISC-V: Reorganize and rename combine patterns in autovec-opt.md - - - -1- 2023-09-20 Lehua Ding Unresolved
[committed] openmp: Add omp::decl attribute support [PR111392] [committed] openmp: Add omp::decl attribute support [PR111392] - - - -1- 2023-09-20 Jakub Jelinek Unresolved
[v5] Introduce attribute sym_alias (was: Last call for bikeshedding on attribute sym/exalias/revers… [v5] Introduce attribute sym_alias (was: Last call for bikeshedding on attribute sym/exalias/revers… - - - -1- 2023-09-20 Alexandre Oliva Unresolved
RISC-V: Fixed ICE caused by missing operand RISC-V: Fixed ICE caused by missing operand - - - -1- 2023-09-20 Lehua Ding Unresolved
libcpp: Improve the diagnostic for poisoned identifiers [PR36887] libcpp: Improve the diagnostic for poisoned identifiers [PR36887] - - - -1- 2023-09-20 Lewis Hyatt Unresolved
[v1] RISC-V: Support ceil and ceilf auto-vectorization [v1] RISC-V: Support ceil and ceilf auto-vectorization - - - -1- 2023-09-20 Li, Pan2 Unresolved
[Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator [Committed] RISC-V: Extend VLS modes in 'VWEXTI' iterator - - - -1- 2023-09-20 juzhe.zhong@rivai.ai Unresolved
[v1] Update check_effective_target_vect_int_mod according to LoongArch SX/ASX capabilities. [v1] Update check_effective_target_vect_int_mod according to LoongArch SX/ASX capabilities. - - - -1- 2023-09-20 Chenghui Pan Unresolved
[Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap [Committed] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap - - 1 -1- 2023-09-19 Patrick O'Neill Corrupt patch
[pushed] c++: fix cxx_print_type's template-info dumping [pushed] c++: fix cxx_print_type's template-info dumping - - - -1- 2023-09-19 Patrick Palka Unresolved
Remove .PHONY targets when building .fda files during autoprofiledbootstrap Remove .PHONY targets when building .fda files during autoprofiledbootstrap - - - -1- 2023-09-19 Eugene Rozenfeld Corrupt patch
RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap - - 2 -1- 2023-09-19 Patrick O'Neill Unresolved
c++: improve class NTTP object pretty printing [PR111471] c++: improve class NTTP object pretty printing [PR111471] - - - -1- 2023-09-19 Patrick Palka Unresolved
[COMMITTED,frange] Add op2_range for operator_not_equal. [COMMITTED,frange] Add op2_range for operator_not_equal. - - - -1- 2023-09-19 Aldy Hernandez Unresolved
[2/2] RISC-V: Add support for XCValu extension in CV32E40P RISC-V: Support CORE-V XCVMAC and XCVALU extensions - - - -1- 2023-09-19 Mary Bennett Unresolved
[1/2] RISC-V: Add support for XCVmac extension in CV32E40P RISC-V: Support CORE-V XCVMAC and XCVALU extensions - - - -1- 2023-09-19 Mary Bennett Unresolved
c++: further optimize tsubst_template_decl c++: further optimize tsubst_template_decl - - - -1- 2023-09-19 Patrick Palka Unresolved
middle-end ifcvt: replace C++ sort with vec::qsort [PR109154] middle-end ifcvt: replace C++ sort with vec::qsort [PR109154] - - - -1- 2023-09-19 Tamar Christina Unresolved
c/111468 - dump unordered compare operators in their GIMPLE form with -gimple c/111468 - dump unordered compare operators in their GIMPLE form with -gimple - - - -1- 2023-09-19 Richard Biener Unresolved
middle-end: relax validate_subreg to allow paradoxical subregs that change mode middle-end: relax validate_subreg to allow paradoxical subregs that change mode - - - -1- 2023-09-19 Tamar Christina Unresolved
RISC-V: Add FNMS floating-point VLS tests RISC-V: Add FNMS floating-point VLS tests - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS unary floating-point patterns [Committed] RISC-V: Support VLS unary floating-point patterns - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization [Committed] RISC-V: Support VLS floating-point FMA/FNMA/FMS auto-vectorization - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
[v2,3/4] Improve functionality of ree pass with various constants with AND operation. Untitled series #58652 - - - -1- 2023-09-19 Ajit Agarwal Unresolved
[RFC,2/2] RISC-V: Add 'Zfbfmin' extension. [RFC,1/2] RISC-V: Add support for _Bfloat16. - - - -1- 2023-09-19 Jin Ma Unresolved
[RFC,1/2] RISC-V: Add support for _Bfloat16. [RFC,1/2] RISC-V: Add support for _Bfloat16. - - - -1- 2023-09-19 Jin Ma Unresolved
[Committed] RISC-V: Support integer FMA/FNMA VLS modes autovectorization [Committed] RISC-V: Support integer FMA/FNMA VLS modes autovectorization - - - -1- 2023-09-19 juzhe.zhong@rivai.ai Unresolved
match.pd: Some build_nonstandard_integer_type tweaks match.pd: Some build_nonstandard_integer_type tweaks - - - -1- 2023-09-19 Jakub Jelinek Unresolved
[committed] libgomp: Handle NULL environ like pointer to NULL pointer [PR111413] [committed] libgomp: Handle NULL environ like pointer to NULL pointer [PR111413] - - - -1- 2023-09-19 Jakub Jelinek Unresolved
v2: small _BitInt tweaks v2: small _BitInt tweaks - - - -1- 2023-09-19 Jakub Jelinek Unresolved
[2/2] testcase: rename pr111303.c to pr111324.c [1/2] using overflow_free_p to simplify pattern - - - -1- 2023-09-19 Jiufu Guo Unresolved
[1/2] using overflow_free_p to simplify pattern [1/2] using overflow_free_p to simplify pattern - - - -1- 2023-09-19 Jiufu Guo Unresolved
[v7] c++: Move consteval folding to cp_fold_r [v7] c++: Move consteval folding to cp_fold_r - - - -1- 2023-09-18 Marek Polacek Unresolved
[pushed] configure, Darwin: Adjust handing of stdlib option. [pushed] configure, Darwin: Adjust handing of stdlib option. - - - -1- 2023-09-18 Iain Sandoe Unresolved
c++, v2: Implement C++26 P2741R3 - user-generated static_assert messages [PR110348] c++, v2: Implement C++26 P2741R3 - user-generated static_assert messages [PR110348] - - - -1- 2023-09-18 Jakub Jelinek Unresolved
c++, v2: Implement C++26 P2169R4 - Placeholder variables with no name [PR110349] c++, v2: Implement C++26 P2169R4 - Placeholder variables with no name [PR110349] - - - -1- 2023-09-18 Jakub Jelinek Unresolved
RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum RISC-V: Support combine cond extend and reduce sum to cond widen reduce sum - - - -1- 2023-09-18 Lehua Ding Unresolved
[pushed] wwwdocs: conduct: Fix nested lists [pushed] wwwdocs: conduct: Fix nested lists - - - -1- 2023-09-18 Gerald Pfeifer Unresolved
LTO: Get rid of 'lto_mode_identity_table' (was: Machine Mode ICE in RISC-V when LTO) LTO: Get rid of 'lto_mode_identity_table' (was: Machine Mode ICE in RISC-V when LTO) - - - -1- 2023-09-18 Thomas Schwinge Unresolved
[wwwdocs] Document libstdc++ changes in GCC 14 [wwwdocs] Document libstdc++ changes in GCC 14 - - - -1- 2023-09-18 Jonathan Wakely Unresolved
RISC-V: Remove redundant vec_duplicate pattern RISC-V: Remove redundant vec_duplicate pattern - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
[Committed] RISC-V: Fix bogus FAILs of vsetvl testcases [Committed] RISC-V: Fix bogus FAILs of vsetvl testcases - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Removed misleading comments in testcases RISC-V: Removed misleading comments in testcases - - - -1- 2023-09-18 Lehua Ding Unresolved
OpenMP: Add ME support for 'omp allocate' stack variables OpenMP: Add ME support for 'omp allocate' stack variables - - - -1- 2023-09-18 Tobias Burnus Unresolved
[Committed] RISC-V: Support VLS reduction [Committed] RISC-V: Support VLS reduction - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Refactor and cleanup fma patterns RISC-V: Refactor and cleanup fma patterns - - - -1- 2023-09-18 Lehua Ding Unresolved
[v1] LoongArch: Adjust the vector cost model for better performance [v1] LoongArch: Adjust the vector cost model for better performance - - - -1- 2023-09-18 Li Wei Unresolved
RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] RISC-V: Remove autovec-vls.md file and clean up VLS move modes[NFC] - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] RISC-V: Remove phase 6 of vsetvl pass in GCC13[PR111412] - - - -1- 2023-09-18 Li Xu Unresolved
[v1] RISC-V: Support VLS mode for vec_set [v1] RISC-V: Support VLS mode for vec_set - - - -1- 2023-09-18 Li, Pan2 via Gcc-patches Unresolved
[Committed] RISC-V: Remove redundant codes of VLS patterns[NFC] [Committed] RISC-V: Remove redundant codes of VLS patterns[NFC] - - - -1- 2023-09-18 juzhe.zhong@rivai.ai Unresolved
MATCH: Make zero_one_valued_p non-recusive fully MATCH: Make zero_one_valued_p non-recusive fully - - - -1- 2023-09-17 Andrew Pinski Unresolved
c++: optimize tsubst_template_decl for function templates c++: optimize tsubst_template_decl for function templates - - - -1- 2023-09-17 Patrick Palka Unresolved
[v1] RISC-V: Bugfix for scalar move with merged operand [v1] RISC-V: Bugfix for scalar move with merged operand - - - -1- 2023-09-17 Li, Pan2 via Gcc-patches Unresolved
RISC-V: Support VLS modes reduction[PR111153] RISC-V: Support VLS modes reduction[PR111153] - - - -1- 2023-09-17 juzhe.zhong@rivai.ai Unresolved
MATCH: Avoid recusive zero_one_valued_p for conversions MATCH: Avoid recusive zero_one_valued_p for conversions - - - -1- 2023-09-17 Andrew Pinski Unresolved
[v14,40/40] libstdc++: Optimize is_scalar trait performance Optimize type traits performance - - - -1- 2023-09-15 Ken Matsui Unresolved
[v14,39/40] c++, libstdc++: Implement __is_scalar built-in trait Optimize type traits performance - - - -1- 2023-09-15 Ken Matsui Unresolved
[v14,38/40] libstdc++: Optimize is_signed trait performance Optimize type traits performance - - - -1- 2023-09-15 Ken Matsui Unresolved
[v14,37/40] c++, libstdc++: Implement __is_signed built-in trait Optimize type traits performance - - - -1- 2023-09-15 Ken Matsui Unresolved
[v14,36/40] libstdc++: Optimize is_unsigned trait performance Optimize type traits performance - - - -1- 2023-09-15 Ken Matsui Unresolved
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