Show patches with: Archived = No       |   15942 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,1/2] Implement ASM_DECLARE_FUNCTION_NAME using ASM_OUTPUT_FUNCTION_LABEL asan: Align .LASANPC on function boundary - - - -1- 2024-01-02 Ilya Leoshkevich Unresolved
libstdc++: testsuite: reduce max_size_type.cc exec time [PR113175] libstdc++: testsuite: reduce max_size_type.cc exec time [PR113175] - - - 1-- 2024-01-02 Patrick Palka Accepted
[OpenACC,2.7] Implement reductions for arrays and structs [OpenACC,2.7] Implement reductions for arrays and structs - - - 1-- 2024-01-02 Chung-Lin Tang Accepted
libsanitizer: Enable LSan and TSan for riscv64 libsanitizer: Enable LSan and TSan for riscv64 - - - 1-- 2024-01-02 Andreas Schwab Accepted
[v4] RISC-V: Handle differences between XTheadvector and Vector [v4] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2024-01-02 joshua Unresolved
[v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option [v3] RISC-V: Bugfix for doesn't honor no-signed-zeros option - - - -1- 2024-01-02 Li, Pan2 Unresolved
Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2024-01-02 joshua Corrupt patch
[v3,12/12,GCC] arm: vld1_types_x4 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,11/12,GCC] arm: vld1_types_x3 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,10/12,GCC] arm: vld1_types_x2 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,09/12,GCC] arm: vst1q_types_x4 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,08/12,GCC] arm: vst1q_types_x3 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,07/12,GCC] arm: vst1q_types_x2 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,06/12,GCC] arm: vst1_types_x4 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,05/12,GCC] arm: vst1_types_x3 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,04/12,GCC] arm: vst1_types_x2 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,03/12,GCC] arm: vld1q_types_x4 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,02/12,GCC] arm: vld1q_types_x3 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics [v3,01/12,GCC] arm: vld1q_types_x2 ACLE intrinsics - - - 1-- 2024-01-02 Ezra Sitorus Accepted
[v6,1/2] RISC-V: Add crypto vector builtin function. [v6,1/2] RISC-V: Add crypto vector builtin function. - - - -1- 2024-01-02 Feng Wang Unresolved
[v5,2/2] RISC-V: Add crypto vector api-testing cases. [v5,1/2] RISC-V: Add crypto vector builtin function. - - - -1- 2024-01-02 Feng Wang Unresolved
[v5,1/2] RISC-V: Add crypto vector builtin function. [v5,1/2] RISC-V: Add crypto vector builtin function. - - - -1- 2024-01-02 Feng Wang Unresolved
[Committed] RISC-V: Add simplification of dummy len and dummy mask COND_LEN_xxx pattern [Committed] RISC-V: Add simplification of dummy len and dummy mask COND_LEN_xxx pattern - - - -1- 2024-01-02 juzhe.zhong@rivai.ai Unresolved
Re：Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector Re：Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2024-01-02 joshua Corrupt patch
RISC-V: Make liveness be aware of rgroup number of LENS[dynamic LMUL] RISC-V: Make liveness be aware of rgroup number of LENS[dynamic LMUL] - - - -1- 2024-01-02 juzhe.zhong@rivai.ai Unresolved
testsuite: Reduce gcc.dg/torture/inline-mem-cpy-1.c by 11 for simulators testsuite: Reduce gcc.dg/torture/inline-mem-cpy-1.c by 11 for simulators - - - -1- 2024-01-02 Hans-Peter Nilsson Unresolved
Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2024-01-02 joshua Corrupt patch
[committed] RISC-V: Modify copyright year of vector-crypto.md [committed] RISC-V: Modify copyright year of vector-crypto.md - - - -1- 2024-01-02 Feng Wang Unresolved
[Committed] RISC-V: Declare STMT_VINFO_TYPE (...) as local variable [Committed] RISC-V: Declare STMT_VINFO_TYPE (...) as local variable - - - -1- 2024-01-02 juzhe.zhong@rivai.ai Unresolved
[committed] RISC-V: Add crypto machine descriptions [committed] RISC-V: Add crypto machine descriptions - - - -1- 2024-01-02 Feng Wang Unresolved
[RFA,V3] new pass for sign/zero extension elimination [RFA,V3] new pass for sign/zero extension elimination - - - 1-- 2024-01-01 Jeff Law Accepted
config-ml.in: Fix multi-os-dir search config-ml.in: Fix multi-os-dir search - - - 1-- 2024-01-01 YunQiang Su Accepted
[gcc,3/3] libgcc: Add basic support for aarch64-gnu (GNU/Hurd on AArch64) [gcc,1/3] Move GNU/Hurd startfile spec from config/i386/gnu.h to config/gnu.h - - - -1- 2024-01-01 Sergey Bugaev Unresolved
[gcc,2/3] aarch64: Add support for aarch64-gnu (GNU/Hurd on AArch64) [gcc,1/3] Move GNU/Hurd startfile spec from config/i386/gnu.h to config/gnu.h - - - -1- 2024-01-01 Sergey Bugaev Unresolved
[gcc,1/3] Move GNU/Hurd startfile spec from config/i386/gnu.h to config/gnu.h [gcc,1/3] Move GNU/Hurd startfile spec from config/i386/gnu.h to config/gnu.h - - - -1- 2024-01-01 Sergey Bugaev Unresolved
Match: Improve inverted_equal_p for bool and `^` and `==` [PR113186] Match: Improve inverted_equal_p for bool and `^` and `==` [PR113186] - - - -1- 2024-01-01 Andrew Pinski (QUIC) Unresolved
LoongArch: Provide fmin/fmax RTL pattern for vectors LoongArch: Provide fmin/fmax RTL pattern for vectors - - - -1- 2023-12-31 Xi Ruoyao Unresolved
[middle-end,take,#2] Only call targetm.truly_noop_truncation for truncations. [middle-end,take,#2] Only call targetm.truly_noop_truncation for truncations. - - - 1-- 2023-12-31 Roger Sayle Accepted
[v9,2/2] Add gcov MC/DC tests for GDC [v9,1/2] Add condition coverage (MC/DC) - - - -1- 2023-12-31 Jørgen Kvalsvik Unresolved
[v9,1/2] Add condition coverage (MC/DC) [v9,1/2] Add condition coverage (MC/DC) - - - -1- 2023-12-31 Jørgen Kvalsvik Unresolved
install: Correct check-g++ to check-gcc-c++ install: Correct check-g++ to check-gcc-c++ - - - 1-- 2023-12-31 YunQiang Su Accepted
Pass GUILE down to subdirectories Pass GUILE down to subdirectories - - - -1- 2023-12-30 Tom Tromey Unresolved
MIPS: Add pattern insqisi_extended and inshisi_extended MIPS: Add pattern insqisi_extended and inshisi_extended - - - 1-- 2023-12-30 YunQiang Su Accepted
Ping^3: [PATCH] Add a late-combine pass [PR106594] Ping^3: [PATCH] Add a late-combine pass [PR106594] - - - 1-- 2023-12-30 Richard Sandiford Accepted
libstdc++ testsuite/std/ranges/iota/max_size_type.cc: Reduce /10 for simulators libstdc++ testsuite/std/ranges/iota/max_size_type.cc: Reduce /10 for simulators - - - -1- 2023-12-30 Hans-Peter Nilsson Unresolved
libstdc++ testsuite/20_util/hash/quality.cc: Increase timeout 3x libstdc++ testsuite/20_util/hash/quality.cc: Increase timeout 3x - - - 1-- 2023-12-30 Hans-Peter Nilsson Accepted
[committed] MAINTAINERS: Update my email address [committed] MAINTAINERS: Update my email address - - - 1-- 2023-12-30 Joseph Myers Accepted
[2/2] MIPS: Implement TARGET_INSN_COSTS [1/2] RTX_COST: Count instructions - - - -1- 2023-12-29 YunQiang Su Unresolved
[1/2] RTX_COST: Count instructions [1/2] RTX_COST: Count instructions - - - -1- 2023-12-29 YunQiang Su Unresolved
[v2,2/2] MIPS: define_attr perf_ratio in mips.md [v2,1/2] MIPS: add pattern insqisi_extended and inshisi_extended - - - 1-- 2023-12-29 YunQiang Su Accepted
[v2,1/2] MIPS: add pattern insqisi_extended and inshisi_extended [v2,1/2] MIPS: add pattern insqisi_extended and inshisi_extended - - - 1-- 2023-12-29 YunQiang Su Accepted
[20/21] Arm: Add Advanced SIMD cbranch implementation Untitled series #75645 - - - -1- 2023-12-29 Tamar Christina Unresolved
AArch64 Update costing for vector conversions [PR110625] AArch64 Update costing for vector conversions [PR110625] - - - -1- 2023-12-29 Tamar Christina Unresolved
[pushed] LoongArch: Fix the format of bstrins_<mode>_for_ior_mask condition (NFC) [pushed] LoongArch: Fix the format of bstrins_<mode>_for_ior_mask condition (NFC) - - - -1- 2023-12-29 Xi Ruoyao Unresolved
Pushed: [PATCH v4] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with com… Pushed: [PATCH v4] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with com… - - - -1- 2023-12-29 Xi Ruoyao Unresolved
[2/2] MIPS: define_attr perf_ratio in mips.md [1/2] MIPS: add pattern insqisi_extended - - - 1-- 2023-12-29 YunQiang Su Accepted
[1/2] MIPS: add pattern insqisi_extended [1/2] MIPS: add pattern insqisi_extended - - - 1-- 2023-12-29 YunQiang Su Accepted
Do not count unused scalar use when marking STMT_VINFO_LIVE_P [PR113091] Do not count unused scalar use when marking STMT_VINFO_LIVE_P [PR113091] - - - -1- 2023-12-29 Feng Xue OS Unresolved
[committed] i386: Fix TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter [PR113133] [committed] i386: Fix TARGET_USE_VECTOR_FP_CONVERTS SF->DF float_extend splitter [PR113133] - - - 1-- 2023-12-29 Uros Bizjak Accepted
[v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-26.c. [v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-26.c. - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-21.c. [v1] LoongArch: testsuite:Add loongarch to gcc.dg/vect/slp-21.c. - - - 1-- 2023-12-29 chenxiaolong Accepted
Fix gen-vect-26.c testcase after loops with multiple exits [PR113167] Fix gen-vect-26.c testcase after loops with multiple exits [PR113167] - - - 1-- 2023-12-29 Andrew Pinski (QUIC) Accepted
[v4,6/6] RISC-V: Add support for xtheadvector-specific intrinsics. [v4] RISC-V: Refactor riscv-vector-builtins-bases.cc - - - -1- 2023-12-29 joshua Unresolved
[v4] RISC-V: Handle differences between XTheadvector and Vector [v4] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2023-12-29 joshua Unresolved
[v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 [v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0 - - - -1- 2023-12-29 joshua Unresolved
[v4] RISC-V: Refactor riscv-vector-builtins-bases.cc [v4] RISC-V: Refactor riscv-vector-builtins-bases.cc - - - -1- 2023-12-29 joshua Unresolved
[v1] LoongArch: testsuite:Add the "-ffast-math" compilation option for the file vect-fmin-3.c. [v1] LoongArch: testsuite:Add the "-ffast-math" compilation option for the file vect-fmin-3.c. - - - 1-- 2023-12-29 chenxiaolong Accepted
Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2023-12-29 joshua Corrupt patch
Re：Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector Re：Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2023-12-29 joshua Corrupt patch
Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2023-12-29 joshua Corrupt patch
[v1,8/8] LoongArch: testsuite:Modify the result check in the FMA file. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1,7/8] LoongArch: testsuite:Added additional vectorization "-mlsx" compilation option. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1,6/8] LoongArch: testsuite:Added additional vectorization "-mlasx" compilation option. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1,5/8] LoongArch: testsuite:Modify the test behavior in file pr60510.f. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1,4/8] LoongArch: testsuite:Fix FAIL in file bind_c_array_params_2.f90. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1,3/8] LoongArch: testsuite:Added test support for vect-{82, 83}.c. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1,2/8] LoongArch: testsuite:Modify the test behavior of the vect-bic-bitmask-{12, 23}.c file. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
[v1,1/8] LoongArch: testsuite:Add detection procedures supported by the target. LoongArch:Enable testing for common - - - -1- 2023-12-29 chenxiaolong Unresolved
Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2023-12-29 joshua Corrupt patch
回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector 回复：[PATCH v4 5/6] RISC-V: Handle differences between XTheadvector and Vector - - - -1- 2023-12-29 joshua Corrupt patch
[v4,6/6] RISC-V: Add support for xtheadvector-specific intrinsics. Untitled series #75588 - - - -1- 2023-12-29 joshua Unresolved
[v4,5/6] RISC-V: Handle differences between XTheadvector and Vector Untitled series #75588 - - - -1- 2023-12-29 joshua Unresolved
[v1] LoongArch: testsuite:Fix FAIL in lasx-xvstelm.c file. [v1] LoongArch: testsuite:Fix FAIL in lasx-xvstelm.c file. - - - -1- 2023-12-29 chenxiaolong Unresolved
[Committed] RISC-V: Robostify testcase pr113112-1.c [Committed] RISC-V: Robostify testcase pr113112-1.c - - - -1- 2023-12-29 juzhe.zhong@rivai.ai Unresolved
RISC-V: Count pointer type SSA into RVV regs liveness for dynamic LMUL cost model RISC-V: Count pointer type SSA into RVV regs liveness for dynamic LMUL cost model - - - -1- 2023-12-29 juzhe.zhong@rivai.ai Unresolved
[v3] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine [v3] LoongArch: Replace -mexplicit-relocs=auto simple-used address peephole2 with combine - - - -1- 2023-12-28 Xi Ruoyao Unresolved
Improved RTL expansion of field assignments into promoted registers. Improved RTL expansion of field assignments into promoted registers. - - - 1-- 2023-12-28 Roger Sayle Accepted
MIPS: Implement TARGET_INSN_COSTS MIPS: Implement TARGET_INSN_COSTS - - - 1-- 2023-12-28 YunQiang Su Accepted
[v2] LoongArch: Merge constant vector permuatation implementations. [v2] LoongArch: Merge constant vector permuatation implementations. - - - -1- 2023-12-28 Li Wei Unresolved
[committed] i386: Cleanup ix86_expand_{unary|binary}_operator issues [committed] i386: Cleanup ix86_expand_{unary|binary}_operator issues - - - -1- 2023-12-28 Uros Bizjak Unresolved
[v1] LoongArch: Merge constant vector permuatation implementations. [v1] LoongArch: Merge constant vector permuatation implementations. - - - -1- 2023-12-28 Li Wei Unresolved
[Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes [Committed] RISC-V: Make dynamic LMUL cost model more accurate for conversion codes - - - -1- 2023-12-28 juzhe.zhong@rivai.ai Unresolved
[C] C: Fix type compatibility for structs with variable sized fields. [C] C: Fix type compatibility for structs with variable sized fields. - - - -1- 2023-12-27 Martin Uecker Unresolved
aarch64: add 'AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA' aarch64: add 'AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA' - - - -1- 2023-12-27 Di Zhao OS Unresolved
[2/2] LoongArch: When the code model is extreme, the symbol address is obtained through macro instr… When cmodel=extreme, add macro support and only - - - -1- 2023-12-27 chenglulu Unresolved
[1/2] LoongArch: Add the macro implementation of mcmodel=extreme. When cmodel=extreme, add macro support and only - - - -1- 2023-12-27 chenglulu Unresolved
[Committed] RISC-V: Make known NITERS loop be aware of dynamic lmul cost model liveness information [Committed] RISC-V: Make known NITERS loop be aware of dynamic lmul cost model liveness information - - - -1- 2023-12-27 juzhe.zhong@rivai.ai Unresolved
[V2] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] [V2] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] - - - -1- 2023-12-27 juzhe.zhong@rivai.ai Unresolved
RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] RISC-V: Disallow transformation into VLMAX AVL for cond_len_xxx when length is in range [0, 31] - - - -1- 2023-12-27 juzhe.zhong@rivai.ai Unresolved
LoongArch: Fix infinite secondary reloading of FCCmode [PR113148] LoongArch: Fix infinite secondary reloading of FCCmode [PR113148] - - - -1- 2023-12-26 Xi Ruoyao Unresolved
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