diff mbox series

RISC-V: Remove duplicate `order_operator' predicate

Message ID alpine.DEB.2.20.2311190609100.5892@tpp.orcam.me.uk
State Accepted
Headers
Series RISC-V: Remove duplicate `order_operator' predicate |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Maciej W. Rozycki Nov. 19, 2023, 11:24 a.m. UTC 
  Remove our RISC-V-specific `order_operator' predicate, which is exactly 
the same as generic `ordered_comparison_operator' one.

	gcc/
	* config/riscv/predicates.md (order_operator): Remove predicate.
	* config/riscv/riscv.cc (riscv_rtx_costs): Update accordingly.
	* config/riscv/riscv.md (*branch<mode>, *mov<GPR:mode><X:mode>cc)
	(cstore<mode>4): Likewise.
---
Hi,

 Verified with the `riscv64-linux-gnu' target and the C language 
testsuite.  OK to apply?

  Maciej
---
 gcc/config/riscv/predicates.md |    3 ---
 gcc/config/riscv/riscv.cc      |    2 +-
 gcc/config/riscv/riscv.md      |    6 +++---
 3 files changed, 4 insertions(+), 7 deletions(-)

gcc-riscv-ordered-comparison-operator.diff

Comments

Maciej W. Rozycki Nov. 22, 2023, 1:31 a.m. UTC | #1 
On Sun, 19 Nov 2023, Jeff Law wrote:

> >   Verified with the `riscv64-linux-gnu' target and the C language
> > testsuite.  OK to apply?
> OK

 Applied now, thank you for your review.

  Maciej
diff mbox series

Patch

Index: gcc/gcc/config/riscv/predicates.md
===================================================================
--- gcc.orig/gcc/config/riscv/predicates.md
+++ gcc/gcc/config/riscv/predicates.md
@@ -339,9 +339,6 @@ 
 (define_predicate "equality_operator"
   (match_code "eq,ne"))
 
-(define_predicate "order_operator"
-  (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
-
 (define_predicate "signed_order_operator"
   (match_code "eq,ne,lt,le,ge,gt"))
 
Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -2914,7 +2914,7 @@  riscv_rtx_costs (rtx x, machine_mode mod
 	      *total = COSTS_N_INSNS (SINGLE_SHIFT_COST + 1);
 	      return true;
 	    }
-	  if (order_operator (XEXP (x, 0), mode))
+	  if (ordered_comparison_operator (XEXP (x, 0), mode))
 	    {
 	      *total = COSTS_N_INSNS (1);
 	      return true;
Index: gcc/gcc/config/riscv/riscv.md
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.md
+++ gcc/gcc/config/riscv/riscv.md
@@ -2640,7 +2640,7 @@ 
 (define_insn "*branch<mode>"
   [(set (pc)
 	(if_then_else
-	 (match_operator 1 "order_operator"
+	 (match_operator 1 "ordered_comparison_operator"
 			 [(match_operand:X 2 "register_operand" "r")
 			  (match_operand:X 3 "reg_or_0_operand" "rJ")])
 	 (label_ref (match_operand 0 "" ""))
@@ -2716,7 +2716,7 @@ 
 (define_insn "*mov<GPR:mode><X:mode>cc"
   [(set (match_operand:GPR 0 "register_operand" "=r,r")
 	(if_then_else:GPR
-	 (match_operator 5 "order_operator"
+	 (match_operator 5 "ordered_comparison_operator"
 		[(match_operand:X 1 "register_operand" "r,r")
 		 (match_operand:X 2 "reg_or_0_operand" "rJ,rJ")])
 	 (match_operand:GPR 3 "register_operand" "0,0")
@@ -2902,7 +2902,7 @@ 
 
 (define_expand "cstore<mode>4"
   [(set (match_operand:SI 0 "register_operand")
-	(match_operator:SI 1 "order_operator"
+	(match_operator:SI 1 "ordered_comparison_operator"
 	    [(match_operand:GPR 2 "register_operand")
 	     (match_operand:GPR 3 "nonmemory_operand")]))]
   ""