diff mbox series

[43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation

Message ID alpine.DEB.2.20.2311190216320.5892@tpp.orcam.me.uk
State Unresolved
Headers
Series RISC-V: Various if-conversion fixes and improvements |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Maciej W. Rozycki Nov. 19, 2023, 5:44 a.m. UTC 
  Verify, for the generic floating-point NE conditional-add operation, 
that if-conversion does *not* trigger at `-mbranch-cost=2' setting, 
which makes original branched code sequences cheaper than their 
branchless equivalents if-conversion would emit.

	gcc/testsuite/
	* gcc.target/riscv/adddibfne.c: New test.
	* gcc.target/riscv/addsibfne.c: New test.
---
 gcc/testsuite/gcc.target/riscv/adddibfne.c |   26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibfne.c |   26 ++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

gcc-riscv-test-addccne-branch-generic.diff
diff mbox series

Patch

Index: gcc/gcc/testsuite/gcc.target/riscv/adddibfne.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/adddibfne.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a5,fa0,fa1
+	bne	a5,zero,.L2
+	add	a0,a0,a1
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/addsibfne.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/addsibfne.c
@@ -0,0 +1,26 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a5,fa0,fa1
+	bne	a5,zero,.L2
+	add[w]	a0,a0,a1
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */