diff mbox series

[28/44] RISC-V/testsuite: Add branchless cases for generic integer cond moves

Message ID alpine.DEB.2.20.2311182049270.5892@tpp.orcam.me.uk
State Unresolved
Headers
Series RISC-V: Various if-conversion fixes and improvements |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Maciej W. Rozycki Nov. 19, 2023, 5:41 a.m. UTC 
  Verify, for generic integer conditional-move operations, if-conversion 
to trigger via `noce_try_cmove' at the respective sufficiently high 
`-mbranch-cost=' settings that make branchless code sequences produced 
by if-conversion cheaper than their original branched equivalents, and, 
where applicable, that extraneous instructions such as SNEZ, etc. are 
not present in output.  Cover all integer relational operations to make 
sure no corner case escapes.

	gcc/testsuite/
	* gcc.target/riscv/movdieq.c: New test.
	* gcc.target/riscv/movdige.c: New test.
	* gcc.target/riscv/movdigeu.c: New test.
	* gcc.target/riscv/movdigt.c: New test.
	* gcc.target/riscv/movdigtu.c: New test.
	* gcc.target/riscv/movdile.c: New test.
	* gcc.target/riscv/movdileu.c: New test.
	* gcc.target/riscv/movdilt.c: New test.
	* gcc.target/riscv/movdiltu.c: New test.
	* gcc.target/riscv/movdine.c: New test.
	* gcc.target/riscv/movsieq.c: New test.
	* gcc.target/riscv/movsige.c: New test.
	* gcc.target/riscv/movsigeu.c: New test.
	* gcc.target/riscv/movsigt.c: New test.
	* gcc.target/riscv/movsigtu.c: New test.
	* gcc.target/riscv/movsile.c: New test.
	* gcc.target/riscv/movsileu.c: New test.
	* gcc.target/riscv/movsilt.c: New test.
	* gcc.target/riscv/movsiltu.c: New test.
	* gcc.target/riscv/movsine.c: New test.
---
 gcc/testsuite/gcc.target/riscv/movdieq.c  |   29 +++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdige.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdigeu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdigt.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdigtu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdile.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdileu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdilt.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdiltu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdine.c  |   29 +++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsieq.c  |   29 +++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsige.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsigeu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsigt.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsigtu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsile.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsileu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsilt.c  |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsiltu.c |   28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsine.c  |   29 +++++++++++++++++++++++++++++
 20 files changed, 564 insertions(+)

gcc-riscv-test-movcc-generic.diff
diff mbox series

Patch

Index: gcc/gcc/testsuite/gcc.target/riscv/movdieq.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdieq.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=7 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdieq (int_t w, int_t x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sub	a5,a0,a1
+	snez	a5,a5
+	neg	a5,a5
+	and	a3,a5,a3
+	not	a5,a5
+	and	a5,a5,a2
+	or	a0,a3,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdige.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdige.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdige (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	slt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdigeu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdigeu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigeu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sltu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdigt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdigt.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdigtu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdigtu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgtu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdile.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdile.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdile (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdileu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdileu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdileu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgtu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdilt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdilt.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdilt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	slt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdiltu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdiltu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sltu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movdine.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movdine.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdine (int_t w, int_t x, int_t y, int_t z)
+{
+  return w != x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sub	a5,a0,a1
+	seqz	a5,a5
+	neg	a5,a5
+	and	a3,a5,a3
+	not	a5,a5
+	and	a5,a5,a2
+	or	a0,a3,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsieq.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsieq.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=7 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=7 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsieq (int_t w, int_t x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sub	a5,a0,a1
+	snez	a5,a5
+	neg	a5,a5
+	and	a3,a5,a3
+	not	a5,a5
+	and	a5,a5,a2
+	or	a0,a3,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsige.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsige.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsige (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	slt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsigeu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsigeu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigeu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sltu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsigt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsigt.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsigtu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsigtu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgtu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsile.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsile.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsile (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsileu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsileu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsileu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sgtu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsilt.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsilt.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsilt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	slt	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsiltu.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsiltu.c
@@ -0,0 +1,28 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sltu	a1,a0,a1
+	neg	a1,a1
+	and	a3,a1,a3
+	not	a1,a1
+	and	a1,a1,a2
+	or	a0,a3,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
Index: gcc/gcc/testsuite/gcc.target/riscv/movsine.c
===================================================================
--- /dev/null
+++ gcc/gcc/testsuite/gcc.target/riscv/movsine.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=6 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsine (int_t w, int_t x, int_t y, int_t z)
+{
+  return w != x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	sub	a5,a0,a1
+	seqz	a5,a5
+	neg	a5,a5
+	and	a3,a5,a3
+	not	a5,a5
+	and	a5,a5,a2
+	or	a0,a3,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */