diff mbox series

[v2] RISC-V: Bugfix for the RVV const vector

Message ID 20231218073557.2020740-1-pan2.li@intel.com
State Unresolved
Headers
Series [v2] RISC-V: Bugfix for the RVV const vector |

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Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Li, Pan2 Dec. 18, 2023, 7:35 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to fix one bug of const vector for interleave.
Assume we need to generate interleave const vector like below.

 V = {{4, -4, 3, -3, 2, -2, 1, -1,}

Before this patch:
vsetvl a3, zero, e64, m8, ta, ma
vid.v       v8            v8 =  {0, 1, 2, 3, 4}
li          a6, -1
vmul.vx     v8, v8, a6    v8 =  {-0, -1, -2, -3, -4}
vadd.vi     v24, v8, 4    v24 = { 4,  3,  2,  1,  0}
vadd.vi     v8, v8, -4    v8 =  {-4, -5, -6, -7, -8}
li          a6, 32
vsll.vx     v8, v8, a6    v8 =  {0, -4, 0, -5, 0, -6, 0, -7,} for e32
vor         v24, v24, v8  v24 = {4, -4, 3, -5, 2, -6, 1, -7,} for e32

After this patch:
vsetvli a6,zero,e64,m8,ta,ma
vid.v  v8                  v8 =  {0, 1, 2, 3, 4}
li a7,-1
vmul.vx v16,v8,a7         v16 = {-0, -1, -2, -3, -4}
vaddvi v16,v16,4          v16 = { 4,  3,  2,  1, 0}
vaddvi v8,v8,-4           v8 =  {-4, -3, -2, -1, 0}
li a7,32
vsll.vx v8,v8,a7          v8 =  {0, -4, 0, -3, 0, -2,} for e32
vor.vv v16,v16,v8         v8 =  {4, -4, 3, -3, 2, -2,} for e32

It is not easy to add asm check stable enough for this case, as we need
to check the vadd -4 target comes from the vid output, which crosses 4
instructions up to point. Thus there is no test here and will be covered
by gcc.dg/vect/pr92420.c in the underlying patches.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Take step2
	instead of step1 for second series.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

juzhe.zhong@rivai.ai Dec. 18, 2023, 7:36 a.m. UTC | #1 
OK. LGTM. It's an obvious fix and not easy to add the test (No need to add such test).



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-12-18 15:35
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for the RVV const vector
From: Pan Li <pan2.li@intel.com>
 
This patch would like to fix one bug of const vector for interleave.
Assume we need to generate interleave const vector like below.
 
V = {{4, -4, 3, -3, 2, -2, 1, -1,}
 
Before this patch:
vsetvl a3, zero, e64, m8, ta, ma
vid.v       v8            v8 =  {0, 1, 2, 3, 4}
li          a6, -1
vmul.vx     v8, v8, a6    v8 =  {-0, -1, -2, -3, -4}
vadd.vi     v24, v8, 4    v24 = { 4,  3,  2,  1,  0}
vadd.vi     v8, v8, -4    v8 =  {-4, -5, -6, -7, -8}
li          a6, 32
vsll.vx     v8, v8, a6    v8 =  {0, -4, 0, -5, 0, -6, 0, -7,} for e32
vor         v24, v24, v8  v24 = {4, -4, 3, -5, 2, -6, 1, -7,} for e32
 
After this patch:
vsetvli a6,zero,e64,m8,ta,ma
vid.v  v8                  v8 =  {0, 1, 2, 3, 4}
li a7,-1
vmul.vx v16,v8,a7         v16 = {-0, -1, -2, -3, -4}
vaddvi v16,v16,4          v16 = { 4,  3,  2,  1, 0}
vaddvi v8,v8,-4           v8 =  {-4, -3, -2, -1, 0}
li a7,32
vsll.vx v8,v8,a7          v8 =  {0, -4, 0, -3, 0, -2,} for e32
vor.vv v16,v16,v8         v8 =  {4, -4, 3, -3, 2, -2,} for e32
 
It is not easy to add asm check stable enough for this case, as we need
to check the vadd -4 target comes from the vid output, which crosses 4
instructions up to point. Thus there is no test here and will be covered
by gcc.dg/vect/pr92420.c in the underlying patches.
 
gcc/ChangeLog:
 
* config/riscv/riscv-v.cc (expand_const_vector): Take step2
instead of step1 for second series.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/riscv-v.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
 
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index eade8db4cf1..d1eb7a0a9a5 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1331,7 +1331,7 @@ expand_const_vector (rtx target, rtx src)
  rtx tmp2 = gen_reg_rtx (new_mode);
  base2 = gen_int_mode (rtx_to_poly_int64 (base2), new_smode);
  expand_vec_series (tmp2, base2,
-      gen_int_mode (step1, new_smode));
+      gen_int_mode (step2, new_smode));
  rtx shifted_tmp2 = expand_simple_binop (
    new_mode, ASHIFT, tmp2,
    gen_int_mode (builder.inner_bits_size (), Pmode), NULL_RTX,
-- 
2.34.1
Li, Pan2 Dec. 18, 2023, 7:53 a.m. UTC | #2 
Committed, thanks Juzhe.

Pan

From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Monday, December 18, 2023 3:37 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v2] RISC-V: Bugfix for the RVV const vector

OK. LGTM. It's an obvious fix and not easy to add the test (No need to add such test).
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index eade8db4cf1..d1eb7a0a9a5 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1331,7 +1331,7 @@  expand_const_vector (rtx target, rtx src)
 		  rtx tmp2 = gen_reg_rtx (new_mode);
 		  base2 = gen_int_mode (rtx_to_poly_int64 (base2), new_smode);
 		  expand_vec_series (tmp2, base2,
-				     gen_int_mode (step1, new_smode));
+				     gen_int_mode (step2, new_smode));
 		  rtx shifted_tmp2 = expand_simple_binop (
 		    new_mode, ASHIFT, tmp2,
 		    gen_int_mode (builder.inner_bits_size (), Pmode), NULL_RTX,