diff mbox series

RISC-V: Robustify vec_init pattern[NFC]

Message ID 20231110033316.1126689-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Robustify vec_init pattern[NFC] |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai Nov. 10, 2023, 3:33 a.m. UTC 
  Although current GCC didn't cause ICE when I create FP16 vec_init case
with -march=rv64gcv (no ZVFH), current vec_init pattern looks wrong.

Since V_VLS FP16 predicate is TARGET_VECTOR_ELEN_FP_16, wheras vec_init
needs vfslide1down/vfslide1up.

It makes more sense to robustify the vec_init patterns which split them
into 2 patterns (one is integer, the other is float) like other autovectorization patterns.

gcc/ChangeLog:

	* config/riscv/autovec.md (vec_init<mode><vel>): Split patterns.

---
 gcc/config/riscv/autovec.md | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

Comments

Li, Pan2 Nov. 10, 2023, 8:17 a.m. UTC | #1 
Committed, thanks Robin.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Friday, November 10, 2023 4:12 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; kito.cheng@gmail.com; kito.cheng@sifive.com; jeffreyalaw@gmail.com
Subject: Re: [PATCH] RISC-V: Robustify vec_init pattern[NFC]

Hi Juzhe,

yes, that's reasonable. OK.

Regards
 Robin
diff mbox series

Patch

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 33722ea1139..868b47c8af7 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -373,7 +373,19 @@ 
 ;; -------------------------------------------------------------------------
 
 (define_expand "vec_init<mode><vel>"
-  [(match_operand:V_VLS 0 "register_operand")
+  [(match_operand:V_VLSI 0 "register_operand")
+   (match_operand 1 "")]
+  "TARGET_VECTOR"
+  {
+    riscv_vector::expand_vec_init (operands[0], operands[1]);
+    DONE;
+  }
+)
+
+;; We split RVV floating-point because we are going to
+;; use vfslide1down/vfslide1up for FP16 which need TARGET_ZVFH.
+(define_expand "vec_init<mode><vel>"
+  [(match_operand:V_VLSF 0 "register_operand")
    (match_operand 1 "")]
   "TARGET_VECTOR"
   {