diff mbox series

[v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init

Message ID 20230924034528.1827780-1-pan2.li@intel.com
State Unresolved
Headers
Series [v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Li, Pan2 Sept. 24, 2023, 3:45 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

When broadcast the reperated element, we take the mask machine mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.

The below test case in RV32 will be fixed.

* gcc/testsuite/gfortran.dg/overload_5.f90

	PR target/111546

gcc/ChangeLog:

	* config/riscv/riscv-v.cc
	(expand_vector_init_merge_repeating_sequence): Bugfix

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-v.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

juzhe.zhong@rivai.ai Sept. 24, 2023, 4:14 a.m. UTC | #1 
The codes here are quite confusing.
Plz rename it:

  /* We can't use BIT mode (BI) directly to generate mask = 0b01010...
     since we don't have such instruction in RVV.
     Instead, we should use INT mode (QI/HI/SI/DI) with integer move instruction
     to generate the mask data we want.  */
  machine_mode mask_int_mode = get_repeating_sequence_dup_machine_mode (builder);
  machine_mode mask_bit_mode = get_mask_mode (builder.mode ());



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-09-24 11:45
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng; patrick
Subject: [PATCH v1] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init
From: Pan Li <pan2.li@intel.com>
 
When broadcast the reperated element, we take the mask machine mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.
 
The below test case in RV32 will be fixed.
 
* gcc/testsuite/gfortran.dg/overload_5.f90
 
PR target/111546
 
gcc/ChangeLog:
 
* config/riscv/riscv-v.cc
(expand_vector_init_merge_repeating_sequence): Bugfix
 
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/riscv-v.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
 
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2466b1354f..6fcbd1622af 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2059,7 +2059,7 @@ expand_vector_init_merge_repeating_sequence (rtx target,
   uint64_t full_nelts = builder.full_nelts ().to_constant ();
   /* Step 1: Broadcast the first pattern.  */
-  rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
+  rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))};
   emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()),
    UNARY_OP, ops);
   /* Step 2: Merge the rest iteration of pattern.  */
-- 
2.34.1
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2466b1354f..6fcbd1622af 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2059,7 +2059,7 @@  expand_vector_init_merge_repeating_sequence (rtx target,
   uint64_t full_nelts = builder.full_nelts ().to_constant ();
 
   /* Step 1: Broadcast the first pattern.  */
-  rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))};
+  rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))};
   emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()),
 		    UNARY_OP, ops);
   /* Step 2: Merge the rest iteration of pattern.  */