diff mbox series

RISC-V: Fixed ICE caused by missing operand

Message ID 20230920053954.3454414-1-lehua.ding@rivai.ai
State Unresolved
Headers
Series RISC-V: Fixed ICE caused by missing operand |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Lehua Ding Sept. 20, 2023, 5:39 a.m. UTC 
  This ICE appears in GCC compiled with -O2 flags.

	PR target/111488

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Add missed operand.

---
 gcc/config/riscv/autovec-opt.md | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

--
2.36.3

Comments

Lehua Ding Sept. 20, 2023, 6:16 a.m. UTC | #1 
Committed, thanks Juzhe.

On 2023/9/20 14:03, juzhe.zhong wrote:
> LGTM
> ---- Replied Message ----
> From	Lehua Ding<lehua.ding@rivai.ai> <mailto:lehua.ding@rivai.ai>
> Date	09/20/2023 13:39
> To	gcc-patches@gcc.gnu.org<gcc-patches@gcc.gnu.org> 
> <mailto:gcc-patches@gcc.gnu.org>
> Cc	juzhe.zhong@rivai.ai<juzhe.zhong@rivai.ai> <mailto:juzhe.zhong@rivai.ai>,
> kito.cheng@gmail.com<kito.cheng@gmail.com> <mailto:kito.cheng@gmail.com>,
> rdapp.gcc@gmail.com<rdapp.gcc@gmail.com> <mailto:rdapp.gcc@gmail.com>,
> palmer@rivosinc.com<palmer@rivosinc.com> <mailto:palmer@rivosinc.com>,
> jeffreyalaw@gmail.com<jeffreyalaw@gmail.com> <mailto:jeffreyalaw@gmail.com>,
> lehua.ding@rivai.ai<lehua.ding@rivai.ai> <mailto:lehua.ding@rivai.ai>
> Subject	[PATCH] RISC-V: Fixed ICE caused by missing operand
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index cef9f157e99..66c77ad6ebb 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -957,7 +957,8 @@ 
     riscv_vector::emit_vlmax_insn (extend_icode, riscv_vector::UNARY_OP,
                                    extend_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_plus (<MODE>mode),
 				   riscv_vector::TERNARY_OP, ops);
     DONE;
@@ -1008,7 +1009,8 @@ 
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul (PLUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1059,7 +1061,8 @@ 
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (PLUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1110,7 +1113,8 @@ 
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul (MINUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;
@@ -1163,7 +1167,8 @@ 
     rtx ext_ops[] = {tmp, operands[2]};
     riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops);

-    rtx ops[] = {operands[0], tmp, operands[3], operands[1]};
+    rtx ops[] = {operands[0], tmp, operands[3], operands[1],
+                 RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (MINUS, <MODE>mode),
 				   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;