diff mbox series

RISC-V: Add fixed PR111255 testcase by other patch

Message ID 20230918121324.3696866-1-lehua.ding@rivai.ai
State Accepted
Headers
Series RISC-V: Add fixed PR111255 testcase by other patch |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Lehua Ding Sept. 18, 2023, 12:13 p.m. UTC 
  This patch add the missed PR111255 testcase which is fixed by this
committed patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628922.html).

	PR target/111255

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/pr111255.c: New test.

---
 .../gcc.target/riscv/rvv/vsetvl/pr111255.c    | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c

--
2.36.3

Comments

juzhe.zhong@rivai.ai Sept. 18, 2023, 12:13 p.m. UTC | #1 
LGTM。



juzhe.zhong@rivai.ai
 
From: Lehua Ding
Date: 2023-09-18 20:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH] RISC-V: Add fixed PR111255 testcase by other patch
This patch add the missed PR111255 testcase which is fixed by this
committed patch (https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628922.html).
 
PR target/111255
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/vsetvl/pr111255.c: New test.
 
---
.../gcc.target/riscv/rvv/vsetvl/pr111255.c    | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
new file mode 100644
index 00000000000..736f6838a50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)                                           \
+  void __attribute__ ((noipa))                                                 \
+  test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,                      \
+   OLD_TYPE *__restrict a, NEW_TYPE b,          \
+   OLD_TYPE *__restrict pred, int n)            \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      {                                                                        \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b;                                  \
+      }                                                                        \
+  }
+
+/* INT -> narrower-INT */
+#define TEST_ALL_X2X_NARROWER(T)                                               \
+  T (int16_t, int8_t)
+
+TEST_ALL_X2X_NARROWER (DEF_LOOP)
+
+/* { dg-final { scan-assembler-not {\tvsetvli\t[a-x0-9]+,[a-x0-9]+,e[0-9]+,m[f0-9]+,t[au],m[au]\n\tvsetvli\t} } } */
--
2.36.3
Lehua Ding Sept. 18, 2023, 12:16 p.m. UTC | #2 
Committed, thanks Juzhe.

On 2023/9/18 20:13, juzhe.zhong@rivai.ai wrote:
> LGTM。
> 
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
> 
>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>     *Date:* 2023-09-18 20:13
>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>     <mailto:lehua.ding@rivai.ai>
>     *Subject:* [PATCH] RISC-V: Add fixed PR111255 testcase by other patch
>     This patch add the missed PR111255 testcase which is fixed by this
>     committed patch
>     (https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628922.html).
>     PR target/111255
>     gcc/testsuite/ChangeLog:
>     * gcc.target/riscv/rvv/vsetvl/pr111255.c: New test.
>     ---
>     .../gcc.target/riscv/rvv/vsetvl/pr111255.c    | 24 +++++++++++++++++++
>     1 file changed, 24 insertions(+)
>     create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
>     diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
>     b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
>     new file mode 100644
>     index 00000000000..736f6838a50
>     --- /dev/null
>     +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
>     @@ -0,0 +1,24 @@
>     +/* { dg-do compile } */
>     +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param
>     riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
>     +
>     +#include <stdint.h>
>     +
>     +#define DEF_LOOP(OLD_TYPE,
>     NEW_TYPE)                                           \
>     +  void __attribute__
>     ((noipa))                                                 \
>     +  test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict
>     r,                      \
>     +   OLD_TYPE *__restrict a, NEW_TYPE b,          \
>     +   OLD_TYPE *__restrict pred, int n)            \
>     + 
>     {                                                                            \
>     +    for (int i = 0; i < n;
>     ++i)                                                \
>     +     
>     {                                                                        \
>     + r[i] = pred[i] ? (NEW_TYPE) a[i] :
>     b;                                  \
>     +     
>     }                                                                        \
>     +  }
>     +
>     +/* INT -> narrower-INT */
>     +#define
>     TEST_ALL_X2X_NARROWER(T)                                               \
>     +  T (int16_t, int8_t)
>     +
>     +TEST_ALL_X2X_NARROWER (DEF_LOOP)
>     +
>     +/* { dg-final { scan-assembler-not
>     {\tvsetvli\t[a-x0-9]+,[a-x0-9]+,e[0-9]+,m[f0-9]+,t[au],m[au]\n\tvsetvli\t} } } */
>     --
>     2.36.3
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
new file mode 100644
index 00000000000..736f6838a50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111255.c
@@ -0,0 +1,24 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 --param riscv-autovec-lmul=m2 -fno-vect-cost-model" } */
+
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE)                                           \
+  void __attribute__ ((noipa))                                                 \
+  test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r,                      \
+				  OLD_TYPE *__restrict a, NEW_TYPE b,          \
+				  OLD_TYPE *__restrict pred, int n)            \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      {                                                                        \
+	r[i] = pred[i] ? (NEW_TYPE) a[i] : b;                                  \
+      }                                                                        \
+  }
+
+/* INT -> narrower-INT */
+#define TEST_ALL_X2X_NARROWER(T)                                               \
+  T (int16_t, int8_t)
+
+TEST_ALL_X2X_NARROWER (DEF_LOOP)
+
+/* { dg-final { scan-assembler-not {\tvsetvli\t[a-x0-9]+,[a-x0-9]+,e[0-9]+,m[f0-9]+,t[au],m[au]\n\tvsetvli\t} } } */