diff mbox series

riscv: thead: Fix mode attribute for extension patterns

Message ID 20230908061600.1922301-1-christoph.muellner@vrull.eu
State Unresolved
Headers
Series riscv: thead: Fix mode attribute for extension patterns |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Christoph Müllner Sept. 8, 2023, 6:16 a.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

The mode attribute of an extension pattern is usually set to the target type.
Let's follow this convention consistently for xtheadbb.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

gcc/ChangeLog:

	* config/riscv/thead.md: Use more appropriate mode attributes
	for extensions.
---
 gcc/config/riscv/thead.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Kito Cheng Sept. 8, 2023, 8:13 a.m. UTC | #1 
LGTM

Christoph Muellner <christoph.muellner@vrull.eu> 於 2023年9月8日 週五 14:16 寫道：

> From: Christoph Müllner <christoph.muellner@vrull.eu>
>
> The mode attribute of an extension pattern is usually set to the target
> type.
> Let's follow this convention consistently for xtheadbb.
>
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>
> gcc/ChangeLog:
>
>         * config/riscv/thead.md: Use more appropriate mode attributes
>         for extensions.
> ---
>  gcc/config/riscv/thead.md | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
> index 05d1b32bd94..2287b752ea1 100644
> --- a/gcc/config/riscv/thead.md
> +++ b/gcc/config/riscv/thead.md
> @@ -101,7 +101,7 @@ (define_insn "*zero_extendsidi2_th_extu"
>     th.extu\t%0,%1,31,0
>     lwu\t%0,%1"
>    [(set_attr "type" "bitmanip,load")
> -   (set_attr "mode" "SI")])
> +   (set_attr "mode" "DI")])
>
>  (define_insn "*zero_extendhi<GPR:mode>2_th_extu"
>    [(set (match_operand:GPR 0 "register_operand" "=r,r")
> @@ -111,7 +111,7 @@ (define_insn "*zero_extendhi<GPR:mode>2_th_extu"
>     th.extu\t%0,%1,15,0
>     lhu\t%0,%1"
>    [(set_attr "type" "bitmanip,load")
> -   (set_attr "mode" "HI")])
> +   (set_attr "mode" "<GPR:MODE>")])
>
>  (define_insn "*th_clz<mode>2"
>    [(set (match_operand:X 0 "register_operand" "=r")
> --
> 2.41.0
>
>
Philipp Tomsich Sept. 8, 2023, 11:29 a.m. UTC | #2 
Applied to master. Thanks!
Philipp.

On Fri, 8 Sept 2023 at 10:13, Kito Cheng <kito.cheng@gmail.com> wrote:

> LGTM
>
> Christoph Muellner <christoph.muellner@vrull.eu> 於 2023年9月8日 週五 14:16 寫道：
>
>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>>
>> The mode attribute of an extension pattern is usually set to the target
>> type.
>> Let's follow this convention consistently for xtheadbb.
>>
>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>>
>> gcc/ChangeLog:
>>
>>         * config/riscv/thead.md: Use more appropriate mode attributes
>>         for extensions.
>> ---
>>  gcc/config/riscv/thead.md | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
>> index 05d1b32bd94..2287b752ea1 100644
>> --- a/gcc/config/riscv/thead.md
>> +++ b/gcc/config/riscv/thead.md
>> @@ -101,7 +101,7 @@ (define_insn "*zero_extendsidi2_th_extu"
>>     th.extu\t%0,%1,31,0
>>     lwu\t%0,%1"
>>    [(set_attr "type" "bitmanip,load")
>> -   (set_attr "mode" "SI")])
>> +   (set_attr "mode" "DI")])
>>
>>  (define_insn "*zero_extendhi<GPR:mode>2_th_extu"
>>    [(set (match_operand:GPR 0 "register_operand" "=r,r")
>> @@ -111,7 +111,7 @@ (define_insn "*zero_extendhi<GPR:mode>2_th_extu"
>>     th.extu\t%0,%1,15,0
>>     lhu\t%0,%1"
>>    [(set_attr "type" "bitmanip,load")
>> -   (set_attr "mode" "HI")])
>> +   (set_attr "mode" "<GPR:MODE>")])
>>
>>  (define_insn "*th_clz<mode>2"
>>    [(set (match_operand:X 0 "register_operand" "=r")
>> --
>> 2.41.0
>>
>>
diff mbox series

Patch

diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 05d1b32bd94..2287b752ea1 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -101,7 +101,7 @@  (define_insn "*zero_extendsidi2_th_extu"
    th.extu\t%0,%1,31,0
    lwu\t%0,%1"
   [(set_attr "type" "bitmanip,load")
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "DI")])
 
 (define_insn "*zero_extendhi<GPR:mode>2_th_extu"
   [(set (match_operand:GPR 0 "register_operand" "=r,r")
@@ -111,7 +111,7 @@  (define_insn "*zero_extendhi<GPR:mode>2_th_extu"
    th.extu\t%0,%1,15,0
    lhu\t%0,%1"
   [(set_attr "type" "bitmanip,load")
-   (set_attr "mode" "HI")])
+   (set_attr "mode" "<GPR:MODE>")])
 
 (define_insn "*th_clz<mode>2"
   [(set (match_operand:X 0 "register_operand" "=r")