Show patches with: Submitter = Philipp Tomsich       |    State = Action Required       |    Archived = No       |   21 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU - - - -1- 2023-11-16 Philipp Tomsich Unresolved
[COMMITTED,PR,110308] cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling [COMMITTED,PR,110308] cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling - - - -1- 2023-06-28 Philipp Tomsich Unresolved
cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling - - - -1- 2023-06-22 Philipp Tomsich Unresolved
[COMMITTED] PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1 [COMMITTED] PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1 - - - -1- 2023-01-31 Philipp Tomsich Unresolved
[PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero [PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero - - - -1- 2022-11-21 Philipp Tomsich Repeat Merge
[v2] gcc-13: aarch64: Document new cores [v2] gcc-13: aarch64: Document new cores - - - -1- 2022-11-14 Philipp Tomsich Unresolved
GCC13: aarch64: Document new cores GCC13: aarch64: Document new cores - - - -1- 2022-11-14 Philipp Tomsich Unresolved
[v2] aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU [v2] aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU - - - -1- 2022-11-14 Philipp Tomsich Unresolved
[v2,8/8] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - -1- 2022-11-13 Philipp Tomsich Unresolved
[v2,7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - -1- 2022-11-13 Philipp Tomsich Unresolved
RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs - - - -1- 2022-11-13 Philipp Tomsich Unresolved
RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori - - - -1- 2022-11-13 Philipp Tomsich Unresolved
RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi - - - -1- 2022-11-13 Philipp Tomsich Unresolved
doc: Update Jeff Law's email-address in contrib.rst doc: Update Jeff Law's email-address in contrib.rst - - - -1- 2022-11-13 Philipp Tomsich Repeat Merge
RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND - - - -1- 2022-11-10 Philipp Tomsich Unresolved
RISC-V: Use bseti to cover more immediates than with ori alone RISC-V: Use bseti to cover more immediates than with ori alone - - - -1- 2022-11-10 Philipp Tomsich Unresolved
[v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - - -1- 2022-11-09 Philipp Tomsich Unresolved
[v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - - -1- 2022-11-09 Philipp Tomsich Unresolved
RISC-V: Optimise adding a (larger than simm12) constant RISC-V: Optimise adding a (larger than simm12) constant - - - -1- 2022-11-09 Philipp Tomsich Unresolved
RISC-V: Optimize branches testing a bit-range or a shifted immediate RISC-V: Optimize branches testing a bit-range or a shifted immediate - - - -1- 2022-11-08 Philipp Tomsich Unresolved
RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w - - - -1- 2022-11-08 Philipp Tomsich Unresolved