diff mbox series

riscv: xtheadbb: Enable constant synthesis with th.srri

Message ID 20230905154234.3316144-1-christoph.muellner@vrull.eu
State Accepted
Headers
Series riscv: xtheadbb: Enable constant synthesis with th.srri |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Christoph Müllner Sept. 5, 2023, 3:42 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

Some constants can be built up using rotate-right instructions.
The code that enables this can be found in riscv_build_integer_1().
However, this functionality is only available for Zbb, which
includes the rori instruction.  This patch enables this also for
XTheadBb, which includes the th.srri instruction.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_build_integer_1): Enable constant
	synthesis with rotate-right for XTheadBb.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadbb-li-rotr.c: New test.
---
 gcc/config/riscv/riscv.cc                     |  2 +-
 .../gcc.target/riscv/xtheadbb-li-rotr.c       | 34 +++++++++++++++++++
 2 files changed, 35 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c

Comments

Jeff Law Sept. 5, 2023, 4:10 p.m. UTC | #1 
On 9/5/23 09:42, Christoph Muellner wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Some constants can be built up using rotate-right instructions.
> The code that enables this can be found in riscv_build_integer_1().
> However, this functionality is only available for Zbb, which
> includes the rori instruction.  This patch enables this also for
> XTheadBb, which includes the th.srri instruction.
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_build_integer_1): Enable constant
> 	synthesis with rotate-right for XTheadBb.
OK
Jeff
Philipp Tomsich Sept. 5, 2023, 4:13 p.m. UTC | #2 
Applied to master. Thanks!
Philipp.

On Tue, 5 Sept 2023 at 18:10, Jeff Law <jeffreyalaw@gmail.com> wrote:

>
>
> On 9/5/23 09:42, Christoph Muellner wrote:
> > From: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > Some constants can be built up using rotate-right instructions.
> > The code that enables this can be found in riscv_build_integer_1().
> > However, this functionality is only available for Zbb, which
> > includes the rori instruction.  This patch enables this also for
> > XTheadBb, which includes the th.srri instruction.
> >
> > Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv.cc (riscv_build_integer_1): Enable constant
> >       synthesis with rotate-right for XTheadBb.
> OK
> Jeff
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2db9c81ac8b..ef63079de8e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -566,7 +566,7 @@  riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
 	}
     }
 
-  if (cost > 2 && TARGET_64BIT && TARGET_ZBB)
+  if (cost > 2 && TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB))
     {
       int leading_ones = clz_hwi (~value);
       int trailing_ones = ctz_hwi (~value);
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c
new file mode 100644
index 00000000000..ecd50448d77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-li-rotr.c
@@ -0,0 +1,34 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xtheadbb" } */
+
+long
+li_rori (void)
+{
+  return 0xffff77ffffffffffL;
+}
+
+long
+li_rori_2 (void)
+{
+  return 0x77ffffffffffffffL;
+}
+
+long
+li_rori_3 (void)
+{
+  return 0xfffffffeefffffffL;
+}
+
+long
+li_rori_4 (void)
+{
+  return 0x5ffffffffffffff5L;
+}
+
+long
+li_rori_5 (void)
+{
+  return 0xaffffffffffffffaL;
+}
+
+/* { dg-final { scan-assembler-times "th.srri\t" 5 } } */