RISC-V: Ensure all implied extensions are included[PR110696]

Message ID 20230717095259.326307-1-lehua.ding@rivai.ai
State Accepted
Headers
Series RISC-V: Ensure all implied extensions are included[PR110696] |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Lehua Ding July 17, 2023, 9:52 a.m. UTC
  Hi,

This patch fix target/PR110696, recursively add all implied extensions.

Best,
Lehua

	PR target/110696

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext): recur add all implied extensions.
	(riscv_subset_list::check_implied_ext): Add new method.
	(riscv_subset_list::parse): Call checker check_implied_ext.
	* config/riscv/riscv-subset.h: Add new method.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/attribute-20.c: New test.
	* gcc.target/riscv/pr110696.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc       | 33 +++++++++++++++++--
 gcc/config/riscv/riscv-subset.h               |  3 +-
 gcc/testsuite/gcc.target/riscv/attribute-20.c |  7 ++++
 gcc/testsuite/gcc.target/riscv/pr110696.c     |  7 ++++
 4 files changed, 46 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr110696.c
  

Comments

Kito Cheng July 17, 2023, 10:30 a.m. UTC | #1
LGTM, thanks for the patch :)

On Mon, Jul 17, 2023 at 5:53 PM Lehua Ding <lehua.ding@rivai.ai> wrote:
>
> Hi,
>
> This patch fix target/PR110696, recursively add all implied extensions.
>
> Best,
> Lehua
>
>         PR target/110696
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext): recur add all implied extensions.
>         (riscv_subset_list::check_implied_ext): Add new method.
>         (riscv_subset_list::parse): Call checker check_implied_ext.
>         * config/riscv/riscv-subset.h: Add new method.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/attribute-20.c: New test.
>         * gcc.target/riscv/pr110696.c: New test.
>
> ---
>  gcc/common/config/riscv/riscv-common.cc       | 33 +++++++++++++++++--
>  gcc/config/riscv/riscv-subset.h               |  3 +-
>  gcc/testsuite/gcc.target/riscv/attribute-20.c |  7 ++++
>  gcc/testsuite/gcc.target/riscv/pr110696.c     |  7 ++++
>  4 files changed, 46 insertions(+), 4 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr110696.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index 28c8f0c1489..19075c0b241 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -949,14 +949,14 @@ riscv_subset_list::parse_std_ext (const char *p)
>
>  /* Check any implied extensions for EXT.  */
>  void
> -riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
> +riscv_subset_list::handle_implied_ext (const char *ext)
>  {
>    const riscv_implied_info_t *implied_info;
>    for (implied_info = &riscv_implied_info[0];
>         implied_info->ext;
>         ++implied_info)
>      {
> -      if (strcmp (ext->name.c_str (), implied_info->ext) != 0)
> +      if (strcmp (ext, implied_info->ext) != 0)
>         continue;
>
>        /* Skip if implied extension already present.  */
> @@ -966,6 +966,9 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
>        /* Version of implied extension will get from current ISA spec
>          version.  */
>        add (implied_info->implied_ext, true);
> +
> +      /* Recursively add implied extension by implied_info->implied_ext.  */
> +      handle_implied_ext (implied_info->implied_ext);
>      }
>
>    /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is
> @@ -980,6 +983,27 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
>      }
>  }
>
> +/* Check that all implied extensions are included.  */
> +bool
> +riscv_subset_list::check_implied_ext ()
> +{
> +  riscv_subset_t *itr;
> +  for (itr = m_head; itr != NULL; itr = itr->next)
> +    {
> +      const riscv_implied_info_t *implied_info;
> +      for (implied_info = &riscv_implied_info[0]; implied_info->ext;
> +          ++implied_info)
> +       {
> +         if (strcmp (itr->name.c_str(), implied_info->ext) != 0)
> +           continue;
> +
> +         if (!lookup (implied_info->implied_ext))
> +           return false;
> +       }
> +    }
> +  return true;
> +}
> +
>  /* Check any combine extensions for EXT.  */
>  void
>  riscv_subset_list::handle_combine_ext ()
> @@ -1194,9 +1218,12 @@ riscv_subset_list::parse (const char *arch, location_t loc)
>
>    for (itr = subset_list->m_head; itr != NULL; itr = itr->next)
>      {
> -      subset_list->handle_implied_ext (itr);
> +      subset_list->handle_implied_ext (itr->name.c_str ());
>      }
>
> +  /* Make sure all implied extensions are included. */
> +  gcc_assert (subset_list->check_implied_ext ());
> +
>    subset_list->handle_combine_ext ();
>
>    if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
> diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
> index 92e4fb31692..84a7a82db63 100644
> --- a/gcc/config/riscv/riscv-subset.h
> +++ b/gcc/config/riscv/riscv-subset.h
> @@ -67,7 +67,8 @@ private:
>    const char *parse_multiletter_ext (const char *, const char *,
>                                      const char *);
>
> -  void handle_implied_ext (riscv_subset_t *);
> +  void handle_implied_ext (const char *);
> +  bool check_implied_ext ();
>    void handle_combine_ext ();
>
>  public:
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c
> new file mode 100644
> index 00000000000..f7d0b29b71c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl65536b -mabi=lp64d" } */
> +int foo()
> +{
> +}
> +
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0\"" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
> new file mode 100644
> index 00000000000..a630f04e74f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d" } */
> +int foo()
> +{
> +}
> +
> +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
> --
> 2.36.3
>
  
Lehua Ding July 17, 2023, 11:50 a.m. UTC | #2
Commited to the trunk, thank you.
&nbsp;
&nbsp;
------------------&nbsp;Original&nbsp;------------------
From: &nbsp;"Kito&nbsp;Cheng"<kito.cheng@gmail.com&gt;;
Date: &nbsp;Mon, Jul 17, 2023 06:30 PM
To: &nbsp;"Lehua Ding"<lehua.ding@rivai.ai&gt;; 
Cc: &nbsp;"gcc-patches"<gcc-patches@gcc.gnu.org&gt;; "juzhe.zhong"<juzhe.zhong@rivai.ai&gt;; "Robin Dapp"<rdapp.gcc@gmail.com&gt;; "palmer"<palmer@rivosinc.com&gt;; "Jeff Law"<jeffreyalaw@gmail.com&gt;; 
Subject: &nbsp;Re: [PATCH] RISC-V: Ensure all implied extensions are included[PR110696]

&nbsp;

LGTM, thanks for the patch :)

On Mon, Jul 17, 2023 at 5:53 PM Lehua Ding <lehua.ding@rivai.ai&gt; wrote:
&gt;
&gt; Hi,
&gt;
&gt; This patch fix target/PR110696, recursively add all implied extensions.
&gt;
&gt; Best,
&gt; Lehua
&gt;
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PR target/110696
&gt;
&gt; gcc/ChangeLog:
&gt;
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * common/config/riscv/riscv-common.cc (riscv_subset_list::handle_implied_ext): recur add all implied extensions.
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (riscv_subset_list::check_implied_ext): Add new method.
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (riscv_subset_list::parse): Call checker check_implied_ext.
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * config/riscv/riscv-subset.h: Add new method.
&gt;
&gt; gcc/testsuite/ChangeLog:
&gt;
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * gcc.target/riscv/attribute-20.c: New test.
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * gcc.target/riscv/pr110696.c: New test.
&gt;
&gt; ---
&gt;&nbsp; gcc/common/config/riscv/riscv-common.cc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; | 33 +++++++++++++++++--
&gt;&nbsp; gcc/config/riscv/riscv-subset.h&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp; 3 +-
&gt;&nbsp; gcc/testsuite/gcc.target/riscv/attribute-20.c |&nbsp; 7 ++++
&gt;&nbsp; gcc/testsuite/gcc.target/riscv/pr110696.c&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp; 7 ++++
&gt;&nbsp; 4 files changed, 46 insertions(+), 4 deletions(-)
&gt;&nbsp; create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
&gt;&nbsp; create mode 100644 gcc/testsuite/gcc.target/riscv/pr110696.c
&gt;
&gt; diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
&gt; index 28c8f0c1489..19075c0b241 100644
&gt; --- a/gcc/common/config/riscv/riscv-common.cc
&gt; +++ b/gcc/common/config/riscv/riscv-common.cc
&gt; @@ -949,14 +949,14 @@ riscv_subset_list::parse_std_ext (const char *p)
&gt;
&gt;&nbsp; /* Check any implied extensions for EXT.&nbsp; */
&gt;&nbsp; void
&gt; -riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
&gt; +riscv_subset_list::handle_implied_ext (const char *ext)
&gt;&nbsp; {
&gt;&nbsp;&nbsp;&nbsp; const riscv_implied_info_t *implied_info;
&gt;&nbsp;&nbsp;&nbsp; for (implied_info = &amp;riscv_implied_info[0];
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; implied_info-&gt;ext;
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ++implied_info)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; {
&gt; -&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; if (strcmp (ext-&gt;name.c_str (), implied_info-&gt;ext) != 0)
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; if (strcmp (ext, implied_info-&gt;ext) != 0)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; continue;
&gt;
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Skip if implied extension already present.&nbsp; */
&gt; @@ -966,6 +966,9 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Version of implied extension will get from current ISA spec
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; version.&nbsp; */
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; add (implied_info-&gt;implied_ext, true);
&gt; +
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Recursively add implied extension by implied_info-&gt;implied_ext.&nbsp; */
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; handle_implied_ext (implied_info-&gt;implied_ext);
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; }
&gt;
&gt;&nbsp;&nbsp;&nbsp; /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is
&gt; @@ -980,6 +983,27 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; }
&gt;&nbsp; }
&gt;
&gt; +/* Check that all implied extensions are included.&nbsp; */
&gt; +bool
&gt; +riscv_subset_list::check_implied_ext ()
&gt; +{
&gt; +&nbsp; riscv_subset_t *itr;
&gt; +&nbsp; for (itr = m_head; itr != NULL; itr = itr-&gt;next)
&gt; +&nbsp;&nbsp;&nbsp; {
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; const riscv_implied_info_t *implied_info;
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; for (implied_info = &amp;riscv_implied_info[0]; implied_info-&gt;ext;
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ++implied_info)
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; {
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; if (strcmp (itr-&gt;name.c_str(), implied_info-&gt;ext) != 0)
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; continue;
&gt; +
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; if (!lookup (implied_info-&gt;implied_ext))
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; return false;
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; }
&gt; +&nbsp;&nbsp;&nbsp; }
&gt; +&nbsp; return true;
&gt; +}
&gt; +
&gt;&nbsp; /* Check any combine extensions for EXT.&nbsp; */
&gt;&nbsp; void
&gt;&nbsp; riscv_subset_list::handle_combine_ext ()
&gt; @@ -1194,9 +1218,12 @@ riscv_subset_list::parse (const char *arch, location_t loc)
&gt;
&gt;&nbsp;&nbsp;&nbsp; for (itr = subset_list-&gt;m_head; itr != NULL; itr = itr-&gt;next)
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; {
&gt; -&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; subset_list-&gt;handle_implied_ext (itr);
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; subset_list-&gt;handle_implied_ext (itr-&gt;name.c_str ());
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; }
&gt;
&gt; +&nbsp; /* Make sure all implied extensions are included. */
&gt; +&nbsp; gcc_assert (subset_list-&gt;check_implied_ext ());
&gt; +
&gt;&nbsp;&nbsp;&nbsp; subset_list-&gt;handle_combine_ext ();
&gt;
&gt;&nbsp;&nbsp;&nbsp; if (subset_list-&gt;lookup ("zfinx") &amp;&amp; subset_list-&gt;lookup ("f"))
&gt; diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
&gt; index 92e4fb31692..84a7a82db63 100644
&gt; --- a/gcc/config/riscv/riscv-subset.h
&gt; +++ b/gcc/config/riscv/riscv-subset.h
&gt; @@ -67,7 +67,8 @@ private:
&gt;&nbsp;&nbsp;&nbsp; const char *parse_multiletter_ext (const char *, const char *,
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; const char *);
&gt;
&gt; -&nbsp; void handle_implied_ext (riscv_subset_t *);
&gt; +&nbsp; void handle_implied_ext (const char *);
&gt; +&nbsp; bool check_implied_ext ();
&gt;&nbsp;&nbsp;&nbsp; void handle_combine_ext ();
&gt;
&gt;&nbsp; public:
&gt; diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c
&gt; new file mode 100644
&gt; index 00000000000..f7d0b29b71c
&gt; --- /dev/null
&gt; +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c
&gt; @@ -0,0 +1,7 @@
&gt; +/* { dg-do compile } */
&gt; +/* { dg-options "-march=rv64gcv_zvl65536b -mabi=lp64d" } */
&gt; +int foo()
&gt; +{
&gt; +}
&gt; +
&gt; +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0\"" } } */
&gt; diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
&gt; new file mode 100644
&gt; index 00000000000..a630f04e74f
&gt; --- /dev/null
&gt; +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
&gt; @@ -0,0 +1,7 @@
&gt; +/* { dg-do compile } */
&gt; +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d" } */
&gt; +int foo()
&gt; +{
&gt; +}
&gt; +
&gt; +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */
&gt; --
&gt; 2.36.3
&gt;
  

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 28c8f0c1489..19075c0b241 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -949,14 +949,14 @@  riscv_subset_list::parse_std_ext (const char *p)
 
 /* Check any implied extensions for EXT.  */
 void
-riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
+riscv_subset_list::handle_implied_ext (const char *ext)
 {
   const riscv_implied_info_t *implied_info;
   for (implied_info = &riscv_implied_info[0];
        implied_info->ext;
        ++implied_info)
     {
-      if (strcmp (ext->name.c_str (), implied_info->ext) != 0)
+      if (strcmp (ext, implied_info->ext) != 0)
 	continue;
 
       /* Skip if implied extension already present.  */
@@ -966,6 +966,9 @@  riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
       /* Version of implied extension will get from current ISA spec
 	 version.  */
       add (implied_info->implied_ext, true);
+
+      /* Recursively add implied extension by implied_info->implied_ext.  */
+      handle_implied_ext (implied_info->implied_ext);
     }
 
   /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is
@@ -980,6 +983,27 @@  riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
     }
 }
 
+/* Check that all implied extensions are included.  */
+bool
+riscv_subset_list::check_implied_ext ()
+{
+  riscv_subset_t *itr;
+  for (itr = m_head; itr != NULL; itr = itr->next)
+    {
+      const riscv_implied_info_t *implied_info;
+      for (implied_info = &riscv_implied_info[0]; implied_info->ext;
+	   ++implied_info)
+	{
+	  if (strcmp (itr->name.c_str(), implied_info->ext) != 0)
+	    continue;
+
+	  if (!lookup (implied_info->implied_ext))
+	    return false;
+	}
+    }
+  return true;
+}
+
 /* Check any combine extensions for EXT.  */
 void
 riscv_subset_list::handle_combine_ext ()
@@ -1194,9 +1218,12 @@  riscv_subset_list::parse (const char *arch, location_t loc)
 
   for (itr = subset_list->m_head; itr != NULL; itr = itr->next)
     {
-      subset_list->handle_implied_ext (itr);
+      subset_list->handle_implied_ext (itr->name.c_str ());
     }
 
+  /* Make sure all implied extensions are included. */
+  gcc_assert (subset_list->check_implied_ext ());
+
   subset_list->handle_combine_ext ();
 
   if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index 92e4fb31692..84a7a82db63 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -67,7 +67,8 @@  private:
   const char *parse_multiletter_ext (const char *, const char *,
 				     const char *);
 
-  void handle_implied_ext (riscv_subset_t *);
+  void handle_implied_ext (const char *);
+  bool check_implied_ext ();
   void handle_combine_ext ();
 
 public:
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c
new file mode 100644
index 00000000000..f7d0b29b71c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c
@@ -0,0 +1,7 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl65536b -mabi=lp64d" } */
+int foo()
+{
+}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c b/gcc/testsuite/gcc.target/riscv/pr110696.c
new file mode 100644
index 00000000000..a630f04e74f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
@@ -0,0 +1,7 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d" } */
+int foo()
+{
+}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\"" } } */