Message ID | 20230210224150.2801962-2-philipp.tomsich@vrull.eu |
---|---|
State | Accepted |
Headers |
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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:54 -0800 (PST) From: Philipp Tomsich <philipp.tomsich@vrull.eu> To: gcc-patches@gcc.gnu.org Cc: Kito Cheng <kito.cheng@gmail.com>, Christoph Muellner <christoph.muellner@vrull.eu>, Palmer Dabbelt <palmer@rivosinc.com>, Andrew Waterman <andrew@sifive.com>, Vineet Gupta <vineetg@rivosinc.com>, Philipp Tomsich <philipp.tomsich@vrull.eu> Subject: [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns Date: Fri, 10 Feb 2023 23:41:41 +0100 Message-Id: <20230210224150.2801962-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757485740962212313?= X-GMAIL-MSGID: =?utf-8?q?1757485740962212313?= |
Series |
RISC-V: Support the Zicond (conditional-operations) extension
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Checks
Context | Check | Description |
---|---|---|
snail/gcc-patch-check | success | Github commit url |
Commit Message
Philipp Tomsich
Feb. 10, 2023, 10:41 p.m. UTC
On RISC-V, conditional-zero (i.e., move a register value or zero to a
destination register) instructions are part if the Zicond extension.
To support architectures that have similar constructs, we define a
canonical RTL representation that can be used in if-conversion.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
gcc/doc/md.texi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
Comments
On Fri, Feb 10, 2023 at 2:43 PM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > On RISC-V, conditional-zero (i.e., move a register value or zero to a > destination register) instructions are part if the Zicond extension. > To support architectures that have similar constructs, we define a > canonical RTL representation that can be used in if-conversion. This is seems like worse canonical form than say: (define_insn "" [(set (match_operand:m 0 ...) (if_then_else (eq_or_ne (match_operand:m 1 ...) (const_int 0)) (match_operand:m 2 ...) (const_int 0) ))] "..." "...") (define_insn "" [(set (match_operand:m 0 ...) (if_then_else (eq_or_ne (match_operand:m 1 ...) (const_int 0)) (const_int 0) (match_operand:m 2 ...) ))] "..." "...") Why can't you use the above form instead? This is the standard way of expressing condition moves of 0. This matches even what aarch64 form is already: (define_insn "*cmov<mode>_insn" [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r") (if_then_else:ALLI (match_operator 1 "aarch64_comparison_operator" [(match_operand 2 "cc_register" "") (const_int 0)]) (match_operand:ALLI 3 "aarch64_reg_zero_or_m1_or_1" "rZ,rZ,UsM,rZ,Ui1,UsM,Ui1") (match_operand:ALLI 4 "aarch64_reg_zero_or_m1_or_1" "rZ,UsM,rZ,Ui1,rZ,UsM,Ui1")))] "!((operands[3] == const1_rtx && operands[4] == constm1_rtx) || (operands[3] == constm1_rtx && operands[4] == const1_rtx))" ;; Final two alternatives should be unreachable, but included for completeness "..." [(set_attr "type" "csel, csel, csel, csel, csel, mov_imm, mov_imm")] ) (Which is more complex as it can handle even more than just the simple case you provide). Thanks, Andrew Pinski > +(define_insn "" > + [(set (match_operand:@var{m} 0 @dots{}) > + (and:@var{m} > + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{}) > + (const_int 0))) > + (match_operand:@var{m} 2 @dots{})))] > + "@dots{}" > + "@dots{}") > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > --- > > gcc/doc/md.texi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index 7235d34c4b3..579462ea67f 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -8347,6 +8347,23 @@ operand of @code{mult} is also a shift, then that is extended also. > This transformation is only applied when it can be proven that the > original operation had sufficient precision to prevent overflow. > > +@cindex @code{conditional-zero}, canonicalization of > +@item > +A machine that has an instruction that performs a conditional-zero > +operation (i.e., an instruction that moves a register value or puts 0 > +into the destination register) should specify the pattern for that > +instruction as: > +@smallexample > +(define_insn "" > + [(set (match_operand:@var{m} 0 @dots{}) > + (and:@var{m} > + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{}) > + (const_int 0))) > + (match_operand:@var{m} 2 @dots{})))] > + "@dots{}" > + "@dots{}") > +@end smallexample > + > @end itemize > > Further canonicalization rules are defined in the function > -- > 2.34.1 >
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7235d34c4b3..579462ea67f 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -8347,6 +8347,23 @@ operand of @code{mult} is also a shift, then that is extended also. This transformation is only applied when it can be proven that the original operation had sufficient precision to prevent overflow. +@cindex @code{conditional-zero}, canonicalization of +@item +A machine that has an instruction that performs a conditional-zero +operation (i.e., an instruction that moves a register value or puts 0 +into the destination register) should specify the pattern for that +instruction as: +@smallexample +(define_insn "" + [(set (match_operand:@var{m} 0 @dots{}) + (and:@var{m} + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{}) + (const_int 0))) + (match_operand:@var{m} 2 @dots{})))] + "@dots{}" + "@dots{}") +@end smallexample + @end itemize Further canonicalization rules are defined in the function