diff mbox series

[1/7] RISC-V: Recognize xventanacondops extension

Message ID 20221112212943.3068249-2-philipp.tomsich@vrull.eu
State Accepted
Headers
Series RISC-V: Backend support for XVentanaCondOps/ZiCondops |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Philipp Tomsich Nov. 12, 2022, 9:29 p.m. UTC 
  This adds the xventanacondops extension to the option parsing and as a
default for the ventana-vt1 core:

gcc/Changelog:

	* common/config/riscv/riscv-common.cc: Recognize
          "xventanacondops" as part of an architecture string.
	* config/riscv/riscv-cores.def (RISCV_CORE): Enable
	  "xventanacondops" by default for "ventana-vt1".
	* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
	(TARGET_XVENTANACONDOPS): Define.
	* config/riscv/riscv.opt: Add "riscv_xventanacondops".

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---

 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv-opts.h           | 3 +++
 gcc/config/riscv/riscv.opt              | 3 +++
 3 files changed, 8 insertions(+)

Comments

Jeff Law Nov. 17, 2022, 10:46 p.m. UTC | #1 
On 11/12/22 14:29, Philipp Tomsich wrote:
> This adds the xventanacondops extension to the option parsing and as a
> default for the ventana-vt1 core:
>
> gcc/Changelog:
>
> 	* common/config/riscv/riscv-common.cc: Recognize
>            "xventanacondops" as part of an architecture string.
> 	* config/riscv/riscv-cores.def (RISCV_CORE): Enable
> 	  "xventanacondops" by default for "ventana-vt1".
> 	* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define.
> 	(TARGET_XVENTANACONDOPS): Define.
> 	* config/riscv/riscv.opt: Add "riscv_xventanacondops".

OK once we've cleared the non-technical hurdles to committing vendor 
specific extensions.


Jeff
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..6b2bdda5feb 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1247,6 +1247,8 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
+  {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..84c987626bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -189,4 +189,7 @@  enum stack_protector_guard {
    ? 0 \
    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
 
+#define MASK_XVENTANACONDOPS (1 << 0)
+#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..9595078bdd4 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -233,6 +233,9 @@  int riscv_zm_subext
 TargetVariable
 int riscv_sv_subext
 
+TargetVariable
+int riscv_xventanacondops = 0
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):