Show patches with: Submitter = Maciej W. Rozycki       |   78 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[2/2] RISC-V/testsuite: Add RTL cset-sext.c testcase variants RISC-V/testsuite: Add RTL if-conversion testcases - - - 1-- 2024-01-24 Maciej W. Rozycki Accepted
[1/2] RISC-V/testsuite: Add RTL pr105314.c testcase variants RISC-V/testsuite: Add RTL if-conversion testcases - - - 1-- 2024-01-24 Maciej W. Rozycki Accepted
[2/2] RISC-V/testsuite: Also verify if-conversion runs for pr105314.c RISC-V/testsuite: A couple of improvements for pr105314.c - - - -1- 2024-01-11 Maciej W. Rozycki Unresolved
[1/2] RISC-V/testsuite: Widen coverage for pr105314.c RISC-V/testsuite: A couple of improvements for pr105314.c - - - -1- 2024-01-11 Maciej W. Rozycki Unresolved
[committed] RISC-V/testsuite: Fix comment termination in pr105314.c [committed] RISC-V/testsuite: Fix comment termination in pr105314.c - - - 1-- 2024-01-10 Maciej W. Rozycki Accepted
RISC-V: Also handle sign extension in branch costing RISC-V: Also handle sign extension in branch costing - - - -1- 2024-01-08 Maciej W. Rozycki Unresolved
[GCC,1/1] testsuite: Support test execution timeout factor as a keyword Support per-test execution timeout factor - - - 1-- 2023-12-12 Maciej W. Rozycki Accepted
[DejaGNU,1/1] Support per-test execution timeout factor [DejaGNU,1/1] Support per-test execution timeout factor - - - -1- 2023-12-12 Maciej W. Rozycki Unresolved
AArch64/testsuite: Use non-capturing parentheses with ccmp_1.c AArch64/testsuite: Use non-capturing parentheses with ccmp_1.c - - - 1-- 2023-11-22 Maciej W. Rozycki Accepted
ARM/testsuite: Use non-capturing parentheses with pr53447-5.c ARM/testsuite: Use non-capturing parentheses with pr53447-5.c - - - 1-- 2023-11-22 Maciej W. Rozycki Accepted
testsuite: Fix subexpressions with `scan-assembler-times' testsuite: Fix subexpressions with `scan-assembler-times' - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
RISC-V: Remove duplicate `order_operator' predicate RISC-V: Remove duplicate `order_operator' predicate - - - 1-- 2023-11-19 Maciej W. Rozycki Accepted
[44/44] RISC-V/testsuite: Add branchless cases for FP NE cond-add operation RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[42/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[41/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[39/44] RISC-V/testsuite: Add branchless cases for generic FP cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[38/44] RISC-V/testsuite: Add branched cases for generic FP cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[37/44] RISC-V/testsuite: Add branchless cases for generic FP cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[36/44] RISC-V/testsuite: Add branched cases for generic FP cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[33/44] RISC-V: Also allow FP conditions in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[31/44] RISC-V/testsuite: Add branchless cases for generic integer cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[30/44] RISC-V/testsuite: Add branched cases for generic integer cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[29/44] RISC-V: Add `addMODEcc' implementation for generic targets RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[28/44] RISC-V/testsuite: Add branchless cases for generic integer cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[27/44] RISC-V/testsuite: Add branched cases for generic integer cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[26/44] RISC-V: Add `movMODEcc' implementation for generic targets RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[25/44] RISC-V: Implement `riscv_emit_unary' helper RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[24/44] RISC-V/testsuite: Add branchless cases for T-Head non-equality cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[23/44] RISC-V/testsuite: Add branched cases for T-Head non-equality cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[22/44] RISC-V: Fold all the cond-move variants together RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[21/44] RISC-V: Also accept constants for T-Head cond-move data input operands RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[20/44] RISC-V: Also accept constants for T-Head cond-move comparison operands RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[19/44] RISC-V/testsuite: Add branchless cases for equality cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[18/44] RISC-V/testsuite: Add branched cases for equality cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[16/44] RISC-V/testsuite: Add branchless cases for GEU and LEU cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[15/44] RISC-V/testsuite: Add branched cases for GEU and LEU cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[14/44] RISC-V: Also invert the cond-move condition for GEU and LEU RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[12/44] RISC-V/testsuite: Add branched cases for FP cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[11/44] RISC-V/testsuite: Add branchless cases for integer cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[09/44] RISC-V: Rework branch costing model for if-conversion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[08/44] RISC-V: Simplify EQ vs NE selection in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[07/44] RISC-V: Use `nullptr' in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[06/44] RISC-V: Avoid repeated GET_MODE calls in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[05/44] RISC-V: Fix `mode' usage in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[04/44] RISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int_compare' RISC-V: Various if-conversion fixes and improvements - - - 1-- 2023-11-19 Maciej W. Rozycki Accepted
[03/44] RISC-V: Reorder comment on SFB patterns RISC-V: Various if-conversion fixes and improvements - - - 1-- 2023-11-19 Maciej W. Rozycki Accepted
[02/44] RISC-V/testsuite: Add cases for integer SFB cond-move operations RISC-V: Various if-conversion fixes and improvements - - - 1-- 2023-11-19 Maciej W. Rozycki Accepted
[01/44] testsuite: Add cases for conditional-move and conditional-add operations RISC-V: Various if-conversion fixes and improvements - - - 1-- 2023-11-19 Maciej W. Rozycki Accepted
[13/44] RISC-V/testsuite: Add branchless cases for FP cond-move operations RISC-V: Various if-conversion fixes and improvements - - - 1-- 2023-11-18 Maciej W. Rozycki Accepted
[committed] RISC-V: Fix indentation of "length" attribute for branches and jumps [committed] RISC-V: Fix indentation of "length" attribute for branches and jumps - - - -1- 2023-11-10 Maciej W. Rozycki Unresolved
[RFA] PR target/111815: VAX: Only accept the index scaler as the RHS operand to ASHIFT [RFA] PR target/111815: VAX: Only accept the index scaler as the RHS operand to ASHIFT - - - 1-- 2023-10-16 Maciej W. Rozycki Accepted
RISC-V/testsuite: Enable `vect_pack_trunc' RISC-V/testsuite: Enable `vect_pack_trunc' - - - 1-- 2023-10-09 Maciej W. Rozycki Accepted
RISC-V/testsuite: Fix ILP32 RVV failures from missing <gnu/stubs-ilp32d.h> RISC-V/testsuite: Fix ILP32 RVV failures from missing <gnu/stubs-ilp32d.h> - - - -1- 2023-09-22 Maciej W. Rozycki Unresolved
[committed] testsuite: Limit bb-slp-pr95839-v8.c to 64-bit vector targets [committed] testsuite: Limit bb-slp-pr95839-v8.c to 64-bit vector targets - - - -1- 2023-07-22 Maciej W. Rozycki Unresolved
[committed] testsuite: Add 64-bit vector variant for bb-slp-pr95839.c [committed] testsuite: Add 64-bit vector variant for bb-slp-pr95839.c - - - 1-- 2023-07-19 Maciej W. Rozycki Accepted
[3/3] testsuite: Require vectors of doubles for pr97428.c testsuite: Exclude vector tests for unsupported targets - - - 1-- 2023-07-06 Maciej W. Rozycki Accepted
[2/3] testsuite: Require 128-bit vectors for bb-slp-pr95839.c testsuite: Exclude vector tests for unsupported targets - - - 1-- 2023-07-06 Maciej W. Rozycki Accepted
[1/3] testsuite: Add check for vectors of 128 bits being supported testsuite: Exclude vector tests for unsupported targets - - - 1-- 2023-07-06 Maciej W. Rozycki Accepted
[v2] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU [v2] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU - - - -1- 2022-11-28 Maciej W. Rozycki Unresolved
testsuite: Fix missing EFFECTIVE_TARGETS variable errors testsuite: Fix missing EFFECTIVE_TARGETS variable errors - - - 1-- 2022-11-15 Maciej W. Rozycki Accepted
ira: Remove duplicate `memset' over `full_costs' from `assign_hard_reg' ira: Remove duplicate `memset' over `full_costs' from `assign_hard_reg' - - - 1-- 2022-11-14 Maciej W. Rozycki Accepted
[committed] ira: Fix `create_insn_allocnos' `outer' parameter documentation [committed] ira: Fix `create_insn_allocnos' `outer' parameter documentation - - - 1-- 2022-11-14 Maciej W. Rozycki Accepted
RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU - - - --- 2022-08-03 Maciej W. Rozycki New
RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float - - - --- 2022-07-28 Maciej W. Rozycki New
RISC-V: Standardize formatting of SFB ALU conditional move RISC-V: Standardize formatting of SFB ALU conditional move - - - --- 2022-07-26 Maciej W. Rozycki New
RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' RISC-V: Remove duplicate backslashes from `stack_protect_set_<mode>' - - - --- 2022-07-26 Maciej W. Rozycki New
doc: Clarify FENV_ACCESS pragma semantics WRT `-ftrapping-math' doc: Clarify FENV_ACCESS pragma semantics WRT `-ftrapping-math' - - - --- 2022-07-19 Maciej W. Rozycki New
RISC-V: Add RTX costs for `if_then_else' expressions RISC-V: Add RTX costs for `if_then_else' expressions - - - --- 2022-07-18 Maciej W. Rozycki New
[committed] RISC-V/doc: Add index references for `mrelax' and `mriscv-attribute' [committed] RISC-V/doc: Add index references for `mrelax' and `mriscv-attribute' - - - --- 2022-07-18 Maciej W. Rozycki New
[committed] RISC-V/doc: Correct the formatting of `-mstack-protector-guard-reg=' [committed] RISC-V/doc: Correct the formatting of `-mstack-protector-guard-reg=' - - - --- 2022-07-18 Maciej W. Rozycki New
[committed] RISC-V/doc: Correct the name of `-mriscv-attribute' [committed] RISC-V/doc: Correct the name of `-mriscv-attribute' - - - --- 2022-07-18 Maciej W. Rozycki New