Show patches with: Submitter = Philipp Tomsich       |   76 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU aarch64: Add support for Ampere-1B (-mcpu=ampere1b) CPU - - - -1- 2023-11-16 Philipp Tomsich Unresolved
aarch64: costs: update for TARGET_CSSC aarch64: costs: update for TARGET_CSSC - - - 1-- 2023-11-16 Philipp Tomsich Accepted
[COMMITTED,PR,110308] cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling [COMMITTED,PR,110308] cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling - - - -1- 2023-06-28 Philipp Tomsich Unresolved
cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling cprop_hardreg: fix ORIGINAL_REGNO/REG_ATTRS/REG_POINTER handling - - - -1- 2023-06-22 Philipp Tomsich Unresolved
[v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a [v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a - - - 1-- 2023-04-14 Philipp Tomsich Accepted
aarch64: disable LDP via tuning structure for -mcpu=ampere1 aarch64: disable LDP via tuning structure for -mcpu=ampere1 - - - 1-- 2023-04-13 Philipp Tomsich Accepted
aarch64: update ampere1 vectorization cost aarch64: update ampere1 vectorization cost - - - 1-- 2023-03-27 Philipp Tomsich Accepted
[RFC,v1,10/10] RISC-V: Support XVentanaCondOps extension RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,09/10] RISC-V: Recognize xventanacondops extension RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,08/10] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,07/10] RISC-V: Recognize bexti in negated if-conversion RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,04/10] RISC-V: Support immediates in Zicond RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,02/10] RISC-V: Recognize Zicond (conditional operations) extension RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[RFC,v1,01/10] docs: Document a canonical RTL for a conditional-zero insns RISC-V: Support the Zicond (conditional-operations) extension - - - 1-- 2023-02-10 Philipp Tomsich Accepted
[COMMITTED] PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1 [COMMITTED] PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1 - - - -1- 2023-01-31 Philipp Tomsich Unresolved
aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4 aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4 - - - 1-- 2023-01-28 Philipp Tomsich Accepted
[PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero [PR107786,COMMITTED] RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero - - - -1- 2022-11-21 Philipp Tomsich Repeat Merge
[v2,2/2] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs Use Zbs with xori/ori/andi and polarity-reversed twobit-tests - - - 1-- 2022-11-18 Philipp Tomsich Accepted
[v2,1/2] RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/xori Use Zbs with xori/ori/andi and polarity-reversed twobit-tests - - - 1-- 2022-11-18 Philipp Tomsich Accepted
[v2] gcc-13: aarch64: Document new cores [v2] gcc-13: aarch64: Document new cores - - - -1- 2022-11-14 Philipp Tomsich Unresolved
GCC13: aarch64: Document new cores GCC13: aarch64: Document new cores - - - -1- 2022-11-14 Philipp Tomsich Unresolved
[v2] aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU [v2] aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU - - - -1- 2022-11-14 Philipp Tomsich Unresolved
[v2,8/8] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - -1- 2022-11-13 Philipp Tomsich Unresolved
[v2,7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - -1- 2022-11-13 Philipp Tomsich Unresolved
[v2,6/8] RISC-V: Support immediates in XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - 1 - 1-- 2022-11-13 Philipp Tomsich Accepted
[v2,5/8] RISC-V: Recognize bexti in negated if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-13 Philipp Tomsich Accepted
[v2,4/8] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-13 Philipp Tomsich Accepted
[v2,3/8] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-13 Philipp Tomsich Accepted
[v2,2/8] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-13 Philipp Tomsich Accepted
[v2,1/8] RISC-V: Recognize xventanacondops extension RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-13 Philipp Tomsich Accepted
RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs - - - -1- 2022-11-13 Philipp Tomsich Unresolved
RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori - - - -1- 2022-11-13 Philipp Tomsich Unresolved
RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi - - - -1- 2022-11-13 Philipp Tomsich Unresolved
[v2,2/2] RISC-V: Add instruction fusion (for ventana-vt1) Basic support for the Ventana VT1 w/ instruction fusion - - - 1-- 2022-11-13 Philipp Tomsich Accepted
[v2,1/2] RISC-V: Add basic support for the Ventana-VT1 core Basic support for the Ventana VT1 w/ instruction fusion - - - 1-- 2022-11-13 Philipp Tomsich Accepted
RISC-V: Zihintpause: add __builtin_riscv_pause RISC-V: Zihintpause: add __builtin_riscv_pause - - - 1-- 2022-11-13 Philipp Tomsich Accepted
RISC-V: Use .p2align for code-alignment RISC-V: Use .p2align for code-alignment - - - 1-- 2022-11-13 Philipp Tomsich Accepted
aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU aarch64: Add support for Ampere-1A (-mcpu=ampere1a) CPU - - - 1-- 2022-11-13 Philipp Tomsich Accepted
doc: Update Jeff Law's email-address in contrib.rst doc: Update Jeff Law's email-address in contrib.rst - - - -1- 2022-11-13 Philipp Tomsich Repeat Merge
[7/7] ifcvt: add if-conversion to conditional-zero instructions RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-12 Philipp Tomsich Accepted
[6/7] RISC-V: Support immediates in XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - 1 - 1-- 2022-11-12 Philipp Tomsich Accepted
[5/7] RISC-V: Recognize bexti in negated if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-12 Philipp Tomsich Accepted
[4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-12 Philipp Tomsich Accepted
[3/7] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-12 Philipp Tomsich Accepted
[2/7] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-12 Philipp Tomsich Accepted
[1/7] RISC-V: Recognize xventanacondops extension RISC-V: Backend support for XVentanaCondOps/ZiCondops - - - 1-- 2022-11-12 Philipp Tomsich Accepted
RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND RISC-V: Optimize masking with two clear bits not a SMALL_OPERAND - - - -1- 2022-11-10 Philipp Tomsich Unresolved
RISC-V: Use binvi to cover more immediates than with xori alone RISC-V: Use binvi to cover more immediates than with xori alone - - - 1-- 2022-11-10 Philipp Tomsich Accepted
RISC-V: Use bseti to cover more immediates than with ori alone RISC-V: Use bseti to cover more immediates than with ori alone - - - -1- 2022-11-10 Philipp Tomsich Unresolved
[v2] RISC-V: costs: support shift-and-add in strength-reduction [v2] RISC-V: costs: support shift-and-add in strength-reduction - - - 1-- 2022-11-10 Philipp Tomsich Accepted
RISC-V: Fix selection of pipeline model for sifive-7-series RISC-V: Fix selection of pipeline model for sifive-7-series - - - 1-- 2022-11-09 Philipp Tomsich Accepted
[v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v3] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - - -1- 2022-11-09 Philipp Tomsich Unresolved
[v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split [v2,WIP] RISC-V: Replace zero_extendsidi2_shifted with generalized split - - - -1- 2022-11-09 Philipp Tomsich Unresolved
ifcombine: fold two bit tests with different polarity ifcombine: fold two bit tests with different polarity - - - 1-- 2022-11-09 Philipp Tomsich Accepted
ifcombine: recognize single bit test of sign-bit ifcombine: recognize single bit test of sign-bit - - - 1-- 2022-11-09 Philipp Tomsich Accepted
RISC-V: Implement movmisalign<mode> to enable SLP RISC-V: Implement movmisalign<mode> to enable SLP - - - 1-- 2022-11-09 Philipp Tomsich Accepted
RISC-V: Optimise adding a (larger than simm12) constant RISC-V: Optimise adding a (larger than simm12) constant - - - -1- 2022-11-09 Philipp Tomsich Unresolved
[v2] RISC-V: No extensions for SImode min/max against safe constant [v2] RISC-V: No extensions for SImode min/max against safe constant - - - 1-- 2022-11-09 Philipp Tomsich Accepted
RISC-V: No extensions for SImode min/max against safe constant RISC-V: No extensions for SImode min/max against safe constant - - - 1-- 2022-11-08 Philipp Tomsich Accepted
RISC-V: Optimize branches testing a bit-range or a shifted immediate RISC-V: Optimize branches testing a bit-range or a shifted immediate - - - -1- 2022-11-08 Philipp Tomsich Unresolved
RISC-V: allow bseti on SImode without sign-extension RISC-V: allow bseti on SImode without sign-extension - - - 1-- 2022-11-08 Philipp Tomsich Accepted
RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w - - - -1- 2022-11-08 Philipp Tomsich Unresolved
RISC-V: split to allow formation of sh[123]add before divw RISC-V: split to allow formation of sh[123]add before divw - - - 1-- 2022-11-08 Philipp Tomsich Accepted
RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" RISC-V: bitmanip: use bexti for "(a & (1 << BIT_NO)) ? 0 : -1" - - - 1-- 2022-11-08 Philipp Tomsich Accepted
RISC-V: branch-(not)equals-zero compares against $zero RISC-V: branch-(not)equals-zero compares against $zero - - - 1-- 2022-11-08 Philipp Tomsich Accepted
RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb RISC-V: optimize '(a >= 0) ? b : 0' to srai + andn, if compiling for Zbb - - - 1-- 2022-11-08 Philipp Tomsich Accepted
RISC-V: costs: support shift-and-add in strength-reduction RISC-V: costs: support shift-and-add in strength-reduction - - - 1-- 2022-11-08 Philipp Tomsich Accepted
RISC-V: costs: handle BSWAP RISC-V: costs: handle BSWAP - - - 1-- 2022-11-08 Philipp Tomsich Accepted
[v2] aarch64: update Ampere-1 core definition [v2] aarch64: update Ampere-1 core definition - - - --- 2022-10-06 Philipp Tomsich New
[v2] aarch64: fix off-by-one in reading cpuinfo [v2] aarch64: fix off-by-one in reading cpuinfo - - - --- 2022-10-06 Philipp Tomsich New
aarch64: fix off-by-one in reading cpuinfo aarch64: fix off-by-one in reading cpuinfo - - - 1-- 2022-10-03 Philipp Tomsich Accepted
aarch64: update Ampere-1 core definition aarch64: update Ampere-1 core definition - - - 1-- 2022-10-03 Philipp Tomsich Accepted
riscv: implement TARGET_MODE_REP_EXTENDED riscv: implement TARGET_MODE_REP_EXTENDED - - - --- 2022-09-05 Philipp Tomsich New