Show patches with: State = Action Required       |   9823 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[2/2] bugzilla: remove `gcc-bugs@` mailing list address [1/1] email: fix bug and patch email addresses - - - -1- 2023-11-21 Ben Boeckel Unresolved
Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infras… Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infras… - - - -1- 2023-11-21 Xi Ruoyao Unresolved
[Committed] RISC-V: Fix reduc_run-9.c test value check bug [Committed] RISC-V: Fix reduc_run-9.c test value check bug - - - -1- 2023-11-21 juzhe.zhong@rivai.ai Unresolved
[RFC] RISC-V: Support RISC-V Profiles in -march option. [RFC] RISC-V: Support RISC-V Profiles in -march option. - - - -1- 2023-11-20 Jiawei Unresolved
[1/1] gcc-14: document P1689R5 scanning output support [1/1] gcc-14: document P1689R5 scanning output support - - - -1- 2023-11-20 Ben Boeckel Unresolved
[1/1] gcc-14: document P1689R5 scanning output support [1/1] gcc-14: document P1689R5 scanning output support - - - -1- 2023-11-20 Ben Boeckel Unresolved
[v3] RISC-V: Implement TLS Descriptors. [v3] RISC-V: Implement TLS Descriptors. - - - -1- 2023-11-20 Tatsuyuki Ishi Unresolved
[wwwdocs] Add new libstdc++ features [wwwdocs] Add new libstdc++ features - - - -1- 2023-11-20 Jonathan Wakely Unresolved
[BUG,FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32 [BUG,FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32 - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
OpenMP: Add uses_allocators support OpenMP: Add uses_allocators support - - - -1- 2023-11-20 Tobias Burnus Unresolved
RISC-V Regression: Remove scalable compile option RISC-V Regression: Remove scalable compile option - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
[v3,11/11] c: Add new -Wdeclaration-missing-parameter-type permerror : More warnings as errors by default - - - -1- 2023-11-20 Florian Weimer Unresolved
[v3,10/11] c: Turn -Wincompatible-pointer-types into a permerror : More warnings as errors by default - - - -1- 2023-11-20 Florian Weimer Unresolved
[v3,09/11] c: Turn -Wreturn-mismatch into a permerror : More warnings as errors by default - - - -1- 2023-11-20 Florian Weimer Unresolved
[v3,08/11] c: Do not ignore some forms of -Wimplicit-int in system headers : More warnings as errors by default - - - -1- 2023-11-20 Florian Weimer Unresolved
[v3,05/11] c: Turn int-conversion warnings into permerrors : More warnings as errors by default - - - -1- 2023-11-20 Florian Weimer Unresolved
GCC developer room at FOSDEM 2024: Call for Participation open GCC developer room at FOSDEM 2024: Call for Participation open - - - -1- 2023-11-20 Thomas Schwinge Unresolved
[4/4] Add vector pair tests to PowerPC Add vector pair support to PowerPC attribute((vector_size(32))) - - - -1- 2023-11-20 Michael Meissner Unresolved
[3/4] Add integer vector pair mode support to PowerPC Add vector pair support to PowerPC attribute((vector_size(32))) - - - -1- 2023-11-20 Michael Meissner Unresolved
[2/4] Vector pair floating point support for PowerPC Add vector pair support to PowerPC attribute((vector_size(32))) - - - -1- 2023-11-20 Michael Meissner Unresolved
[1/4] Add vector pair modes to PowerPC (patch attached) Add vector pair support to PowerPC attribute((vector_size(32))) - - - -1- 2023-11-20 Michael Meissner Unresolved
[BUG,FIX] RISC-V: Fix VLS DI mode of slide1 instruction attribute [BUG,FIX] RISC-V: Fix VLS DI mode of slide1 instruction attribute - - - -1- 2023-11-20 juzhe.zhong@rivai.ai Unresolved
[RFC] c++: mangle function template constraints [RFC] c++: mangle function template constraints - - - -1- 2023-11-20 Jason Merrill Unresolved
[x86] Support reduc_{and, ior, xor}_scal_m for V4HI/V8QI/V4QImode [x86] Support reduc_{and, ior, xor}_scal_m for V4HI/V8QI/V4QImode - - - -1- 2023-11-20 liuhongt Unresolved
[v3,5/5] LoongArch: Use LSX for scalar FP rounding with explicit rounding mode LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-20 Xi Ruoyao Unresolved
[v3,4/5] LoongArch: Remove lrint_allow_inexact LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-20 Xi Ruoyao Unresolved
[v3,3/5] LoongArch: Use standard pattern name and RTX code for LSX/LASX rotate shift LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-20 Xi Ruoyao Unresolved
[v3,2/5] LoongArch: Use standard pattern name and RTX code for LSX/LASX muh instructions LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-20 Xi Ruoyao Unresolved
[v3,1/5] LoongArch: Fix usage of LSX and LASX frint/ftint instructions [PR112578] LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-20 Xi Ruoyao Unresolved
libstdc++: Speed up push_back libstdc++: Speed up push_back - - - -1- 2023-11-19 Jan Hubicka Unresolved
[committed] RISC-V: Infrastructure for instruction fusion [committed] RISC-V: Infrastructure for instruction fusion - - - -1- 2023-11-19 Jeff Law Unresolved
[v2,3/3] LoongArch: Use standard pattern name and RTX code for LSX/LASX rotate shift LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-19 Xi Ruoyao Unresolved
[v2,2/3] LoongArch: Use standard pattern name and RTX code for LSX/LASX muh instructions LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-19 Xi Ruoyao Unresolved
[v2,1/3] LoongArch: Fix usage of LSX and LASX frint/ftint instructions [PR112578] LoongArch: SIMD fixes and optimizations - - - -1- 2023-11-19 Xi Ruoyao Unresolved
[Committed,V2] RISC-V: Optimize constant AVL for LRA pattern [Committed,V2] RISC-V: Optimize constant AVL for LRA pattern - - - -1- 2023-11-19 juzhe.zhong@rivai.ai Unresolved
[pushed] libcpp: split decls out to rich-location.h [pushed] libcpp: split decls out to rich-location.h - - - -1- 2023-11-19 David Malcolm Unresolved
testsuite: Fix subexpressions with `scan-assembler-times' testsuite: Fix subexpressions with `scan-assembler-times' - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
LoongArch: Optimize LSX vector shuffle on floating-point vector LoongArch: Optimize LSX vector shuffle on floating-point vector - - - -1- 2023-11-19 Xi Ruoyao Unresolved
[44/44] RISC-V/testsuite: Add branchless cases for FP NE cond-add operation RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[42/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[41/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[39/44] RISC-V/testsuite: Add branchless cases for generic FP cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[38/44] RISC-V/testsuite: Add branched cases for generic FP cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[37/44] RISC-V/testsuite: Add branchless cases for generic FP cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[36/44] RISC-V/testsuite: Add branched cases for generic FP cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[33/44] RISC-V: Also allow FP conditions in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[31/44] RISC-V/testsuite: Add branchless cases for generic integer cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[30/44] RISC-V/testsuite: Add branched cases for generic integer cond adds RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[29/44] RISC-V: Add `addMODEcc' implementation for generic targets RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[28/44] RISC-V/testsuite: Add branchless cases for generic integer cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[27/44] RISC-V/testsuite: Add branched cases for generic integer cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[26/44] RISC-V: Add `movMODEcc' implementation for generic targets RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[25/44] RISC-V: Implement `riscv_emit_unary' helper RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[24/44] RISC-V/testsuite: Add branchless cases for T-Head non-equality cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[23/44] RISC-V/testsuite: Add branched cases for T-Head non-equality cond moves RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[22/44] RISC-V: Fold all the cond-move variants together RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[21/44] RISC-V: Also accept constants for T-Head cond-move data input operands RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[20/44] RISC-V: Also accept constants for T-Head cond-move comparison operands RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[19/44] RISC-V/testsuite: Add branchless cases for equality cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[18/44] RISC-V/testsuite: Add branched cases for equality cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[16/44] RISC-V/testsuite: Add branchless cases for GEU and LEU cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[15/44] RISC-V/testsuite: Add branched cases for GEU and LEU cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[14/44] RISC-V: Also invert the cond-move condition for GEU and LEU RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[12/44] RISC-V/testsuite: Add branched cases for FP cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[11/44] RISC-V/testsuite: Add branchless cases for integer cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[09/44] RISC-V: Rework branch costing model for if-conversion RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[08/44] RISC-V: Simplify EQ vs NE selection in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[07/44] RISC-V: Use `nullptr' in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[06/44] RISC-V: Avoid repeated GET_MODE calls in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[05/44] RISC-V: Fix `mode' usage in `riscv_expand_conditional_move' RISC-V: Various if-conversion fixes and improvements - - - -1- 2023-11-19 Maciej W. Rozycki Unresolved
[pushed] analyzer: new warning: -Wanalyzer-undefined-behavior-strtok [PR107573] [pushed] analyzer: new warning: -Wanalyzer-undefined-behavior-strtok [PR107573] - - - -1- 2023-11-19 David Malcolm Unresolved
Propagate value ranges of return values Propagate value ranges of return values - - - -1- 2023-11-19 Jan Hubicka Unresolved
RFA: RISC-V: Add support for XCVhwlp extension in CV32E40P RFA: RISC-V: Add support for XCVhwlp extension in CV32E40P - - - -1- 2023-11-18 Joern Rennecke Unresolved
[4/4] c: runtime checking for assigment of VM types 4/4 [1/4] c: runtime checking for assigment of VM types 1/4 - - - -1- 2023-11-18 Martin Uecker Unresolved
[3/4] c: runtime checking for assigment of VM types 3/4 [1/4] c: runtime checking for assigment of VM types 1/4 - - - -1- 2023-11-18 Martin Uecker Unresolved
[2/4] c: runtime checking for assigment of VM types 2/4 [1/4] c: runtime checking for assigment of VM types 1/4 - - - -1- 2023-11-18 Martin Uecker Unresolved
[1/4] c: runtime checking for assigment of VM types 1/4 [1/4] c: runtime checking for assigment of VM types 1/4 - - - -1- 2023-11-18 Martin Uecker Unresolved
c: Add __builtin_stdc_bit_{width,floor,ceil} builtins c: Add __builtin_stdc_bit_{width,floor,ceil} builtins - - - -1- 2023-11-18 Jakub Jelinek Unresolved
c: Add __builtin_bit_complement c: Add __builtin_bit_complement - - - -1- 2023-11-18 Jakub Jelinek Unresolved
c-family, middle-end: Add __builtin_c[lt]zg (arg, 0ULL) exception c-family, middle-end: Add __builtin_c[lt]zg (arg, 0ULL) exception - - - -1- 2023-11-18 Jakub Jelinek Unresolved
libstdc++: implement std::generator libstdc++: implement std::generator - - - -1- 2023-11-18 Arsen Arsenović Unresolved
LoongArch: Fix "-mexplict-relocs=none -mcmodel=medium" producing %call36 when the assembler does no… LoongArch: Fix "-mexplict-relocs=none -mcmodel=medium" producing %call36 when the assembler does no… - - - -1- 2023-11-18 Xi Ruoyao Unresolved
[committed] RISC-V: Fix mismatched new delete for unique_ptr [committed] RISC-V: Fix mismatched new delete for unique_ptr - - - -1- 2023-11-18 Kito Cheng Unresolved
tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) optimization for direct optab [PR9… tree-ssa-math-opts: popcount (X) == 1 to (X ^ (X - 1)) > (X - 1) optimization for direct optab [PR9… - - - -1- 2023-11-18 Jakub Jelinek Unresolved
tree-optimization: Add register pressure in LICM at tree-ssa level optimization tree-optimization: Add register pressure in LICM at tree-ssa level optimization - - - -1- 2023-11-18 Ajit Agarwal Unresolved
RISC-V: Refactor RVV iterators[NFC] RISC-V: Refactor RVV iterators[NFC] - - - -1- 2023-11-18 juzhe.zhong@rivai.ai Unresolved
[pushed] analyzer: new warning: -Wanalyzer-infinite-loop [PR106147] [pushed] analyzer: new warning: -Wanalyzer-infinite-loop [PR106147] - - - -1- 2023-11-18 David Malcolm Unresolved
libgccjit: Add vector permutation and vector access operations libgccjit: Add vector permutation and vector access operations - - - -1- 2023-11-17 Antoni Boucher Unresolved
LoongArch: Fix usage of LSX and LASX frint/ftint instructions [PR112578] LoongArch: Fix usage of LSX and LASX frint/ftint instructions [PR112578] - - - -1- 2023-11-17 Xi Ruoyao Unresolved
[v2,6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS Add LoongArch v1.1 div32 and ld-seq-sa support - - - -1- 2023-11-17 Xi Ruoyao Unresolved
[v2,5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Add LoongArch v1.1 div32 and ld-seq-sa support - - - -1- 2023-11-17 Xi Ruoyao Unresolved
[v2,4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled Add LoongArch v1.1 div32 and ld-seq-sa support - - - -1- 2023-11-17 Xi Ruoyao Unresolved
[v2,3/6] LoongArch: Add evolution features of base ISA revisions Add LoongArch v1.1 div32 and ld-seq-sa support - - - -1- 2023-11-17 Xi Ruoyao Unresolved
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