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Show patches with
: Submitter =
Lehua Ding
| State =
Action Required
| 119 patches
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Patch
Series
A/R/T
S/W/F
Date
Submitter
Delegate
State
RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl
RISC-V: Forbidden fuse vlmax vsetvl to DEMAND_NONZERO_AVL vsetvl
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1
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2023-08-17
Lehua Ding
Unresolved
RISC-V: Revert the convert from vmv.s.x to vmv.v.i
RISC-V: Revert the convert from vmv.s.x to vmv.v.i
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1
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2023-08-11
Lehua Ding
Unresolved
[V2] RISC-V: Fix error combine of pred_mov pattern
[V2] RISC-V: Fix error combine of pred_mov pattern
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1
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2023-08-10
Lehua Ding
Unresolved
[V2,3/3] RISC-V: Part-3: Output .variant_cc directive for vector function
RISC-V: Add an experimental vector calling convention
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1
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2023-08-10
Lehua Ding
Unresolved
[V2,2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
RISC-V: Add an experimental vector calling convention
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1
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2023-08-10
Lehua Ding
Unresolved
[V2,1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
RISC-V: Add an experimental vector calling convention
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1
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2023-08-10
Lehua Ding
Unresolved
RISC-V: Fix error combine of pred_mov pattern
RISC-V: Fix error combine of pred_mov pattern
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1
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2023-08-08
Lehua Ding
Unresolved
[V5] VECT: Support floating-point in-order reduction for length loop control
[V5] VECT: Support floating-point in-order reduction for length loop control
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1
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2023-07-23
Lehua Ding
Unresolved
[3/3] RISC-V: Part-3: Output .variant_cc directive for vector function
RISC-V: Add an experimental vector calling convention
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1
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2023-07-20
Lehua Ding
Unresolved
[2/3] RISC-V: Part-2: Save/Restore vector registers which need to be preversed
RISC-V: Add an experimental vector calling convention
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1
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2023-07-20
Lehua Ding
Unresolved
[1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns
RISC-V: Add an experimental vector calling convention
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1
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2023-07-20
Lehua Ding
Unresolved
mklog: fix bugs of --append option
mklog: fix bugs of --append option
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1
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2023-07-19
Lehua Ding
Unresolved
RISC-V: Remove testcase that cannot be compiled because VLEN limitation
RISC-V: Remove testcase that cannot be compiled because VLEN limitation
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1
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2023-07-18
Lehua Ding
Repeat Merge
RISC-V: Add an experimental vector calling convention
RISC-V: Add an experimental vector calling convention
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1
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2023-06-25
Lehua Ding
Unresolved
RISC-V: Fix compiler warning of riscv_arg_has_vector
RISC-V: Fix compiler warning of riscv_arg_has_vector
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1
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2023-06-20
Lehua Ding
Unresolved
RISC-V: Add tuple vector mode psABI checking and simplify code
RISC-V: Add tuple vector mode psABI checking and simplify code
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1
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2023-06-18
Lehua Ding
Unresolved
[V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119]
[V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119]
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1
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2023-06-14
Lehua Ding
Unresolved
RISC-V: Ensure vector args and return use function stack to pass [PR110119]
RISC-V: Ensure vector args and return use function stack to pass [PR110119]
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1
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2023-06-14
Lehua Ding
Unresolved
RISC-V: Fix PR 110119
RISC-V: Fix PR 110119
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1
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2023-06-14
Lehua Ding
Unresolved
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