[V3,00/11] Refactor and cleanup vsetvl pass

  This patch refactors and cleanups the vsetvl pass in order to make the code
easier to modify and understand. This patch does several things:

1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3 only maintain
   and modify this virtual CFG. Phase 4 performs insertion, modification and
   deletion of vsetvl insns based on the virtual CFG. The Basic block in the
   virtual CFG is called vsetvl_block_info and the vsetvl information inside
   is called vsetvl_info.
2. Combine Phase 1 and 2 into a single Phase 1 and unified the demand system,
   this Phase only fuse local vsetvl info in forward direction.
3. Refactor Phase 3, change the logic for determining whether to uplift vsetvl
   info to a pred basic block to a more unified method that there is a vsetvl
   info in the vsetvl defintion reaching in compatible with it.
4. Place all modification operations to the RTL in Phase 4 and Phase 5.
   Phase 4 is responsible for inserting, modifying and deleting vsetvl
   instructions based on fully optimized vsetvl infos. Phase 5 removes the avl
   operand from the RVV instruction and removes the unused dest operand
   register from the vsetvl insns.

These modifications resulted in some testcases needing to be updated. The reasons
for updating are summarized below:

1. more optimized
   vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
   vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
   avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
2. less unnecessary fusion
   avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
3. local fuse direction (backward -> forward)
   scalar_move-1.c/
4. add some bugfix testcases.
   pr111037-3.c/pr111037-4.c
   avl_single-89.c

	PR target/111037
	PR target/111234
	PR target/111725

Lehua Ding (11):
  RISC-V: P1: Refactor
    avl_info/vl_vtype_info/vector_insn_info/vector_block_info
  RISC-V: P2: Refactor and cleanup demand system
  RISC-V: P3: Refactor vector_infos_manager
  RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
  RISC-V: P5: combine phase 1 and 2
  RISC-V: P6: Add computing reaching definition data flow
  RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
  RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
  RISC-V: P9: Cleanup and reorganize helper functions
  RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
  RISC-V: P11: Adjust and add testcases

 gcc/config/riscv/riscv-vsetvl.cc              | 6502 +++++++----------
 gcc/config/riscv/riscv-vsetvl.def             |  641 +-
 gcc/config/riscv/riscv-vsetvl.h               |  488 --
 gcc/config/riscv/t-riscv                      |    2 +-
 .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
 .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
 .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
 .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
 .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
 .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
 .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
 .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
 .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
 .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
 .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
 .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
 .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
 .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
 .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
 .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
 .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
 .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
 .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
 .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
 .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
 .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
 .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
 30 files changed, 3263 insertions(+), 4692 deletions(-)
 delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
 rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-1.c (100%)
 rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-2.c (100%)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
  

Hi Lehua,

thanks for the extensive rework.  I'm going to let Juzhe handle the review
since it's his pass and he knows it best.  Delegated it to him in patchwork.

Regards
 Robin
  

Okay, thanks anyway.

On 2023/10/19 16:38, Robin Dapp wrote:
> Hi Lehua,
> 
> thanks for the extensive rework.  I'm going to let Juzhe handle the review
> since it's his pass and he knows it best.  Delegated it to him in patchwork.
> 
> Regards
>   Robin
>
  

LGTM now. But wait for Patrick CI testing.

Hi, @Patrick. Could you apply this patch and trigger CI in your github  so that we can see the full running result.

Issues ・ patrick-rivos/riscv-gnu-toolchain ・ GitHub



juzhe.zhong@rivai.ai
 
From: Lehua Ding
Date: 2023-10-19 16:33
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
This patch refactors and cleanups the vsetvl pass in order to make the code
easier to modify and understand. This patch does several things:
 
1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3 only maintain
   and modify this virtual CFG. Phase 4 performs insertion, modification and
   deletion of vsetvl insns based on the virtual CFG. The Basic block in the
   virtual CFG is called vsetvl_block_info and the vsetvl information inside
   is called vsetvl_info.
2. Combine Phase 1 and 2 into a single Phase 1 and unified the demand system,
   this Phase only fuse local vsetvl info in forward direction.
3. Refactor Phase 3, change the logic for determining whether to uplift vsetvl
   info to a pred basic block to a more unified method that there is a vsetvl
   info in the vsetvl defintion reaching in compatible with it.
4. Place all modification operations to the RTL in Phase 4 and Phase 5.
   Phase 4 is responsible for inserting, modifying and deleting vsetvl
   instructions based on fully optimized vsetvl infos. Phase 5 removes the avl
   operand from the RVV instruction and removes the unused dest operand
   register from the vsetvl insns.
 
These modifications resulted in some testcases needing to be updated. The reasons
for updating are summarized below:
 
1. more optimized
   vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
   vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
   avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
2. less unnecessary fusion
   avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
3. local fuse direction (backward -> forward)
   scalar_move-1.c/
4. add some bugfix testcases.
   pr111037-3.c/pr111037-4.c
   avl_single-89.c
 
PR target/111037
PR target/111234
PR target/111725
 
Lehua Ding (11):
  RISC-V: P1: Refactor
    avl_info/vl_vtype_info/vector_insn_info/vector_block_info
  RISC-V: P2: Refactor and cleanup demand system
  RISC-V: P3: Refactor vector_infos_manager
  RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
  RISC-V: P5: combine phase 1 and 2
  RISC-V: P6: Add computing reaching definition data flow
  RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
  RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
  RISC-V: P9: Cleanup and reorganize helper functions
  RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
  RISC-V: P11: Adjust and add testcases
 
gcc/config/riscv/riscv-vsetvl.cc              | 6502 +++++++----------
gcc/config/riscv/riscv-vsetvl.def             |  641 +-
gcc/config/riscv/riscv-vsetvl.h               |  488 --
gcc/config/riscv/t-riscv                      |    2 +-
.../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
.../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
.../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
.../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
.../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
.../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
.../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
.../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
.../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
.../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
.../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
.../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
.../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
.../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
.../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
.../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
.../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
.../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
.../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
.../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
.../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
.../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
.../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
.../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
30 files changed, 3263 insertions(+), 4692 deletions(-)
delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-1.c (100%)
rename gcc/testsuite/gcc.target/riscv/rvv/{base => vsetvl}/pr111037-2.c (100%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
 
-- 
2.36.3
  

I tested it this morning on my machine and it passed!

Tested against:
04d6c74564b7eb51660a00b35353aeab706b5a50

Using targets:
glibc rv32gcv qemu
glibc rv64gcv qemu

This patch series does not introduce any new failures.

Here's a list of *resolved* failures by this patch series:
rv64gcv:
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test

rv32gcv:
FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
-funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test

Thanks for the quick revision Lehua!

Tested-by: Patrick O'Neill <patrick@rivosinc.com>

Patrick

On 10/19/23 01:50, 钟居哲 wrote:
> LGTM now. But wait for Patrick CI testing.
>
> Hi, @Patrick. Could you apply this patch and trigger CI in your 
> github  so that we can see the full running result.
>
> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>     *Date:* 2023-10-19 16:33
>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>     <mailto:lehua.ding@rivai.ai>
>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>     This patch refactors and cleanups the vsetvl pass in order to make
>     the code
>     easier to modify and understand. This patch does several things:
>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>     only maintain
>        and modify this virtual CFG. Phase 4 performs insertion,
>     modification and
>        deletion of vsetvl insns based on the virtual CFG. The Basic
>     block in the
>        virtual CFG is called vsetvl_block_info and the vsetvl
>     information inside
>        is called vsetvl_info.
>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>     demand system,
>        this Phase only fuse local vsetvl info in forward direction.
>     3. Refactor Phase 3, change the logic for determining whether to
>     uplift vsetvl
>        info to a pred basic block to a more unified method that there
>     is a vsetvl
>        info in the vsetvl defintion reaching in compatible with it.
>     4. Place all modification operations to the RTL in Phase 4 and
>     Phase 5.
>        Phase 4 is responsible for inserting, modifying and deleting vsetvl
>        instructions based on fully optimized vsetvl infos. Phase 5
>     removes the avl
>        operand from the RVV instruction and removes the unused dest
>     operand
>        register from the vsetvl insns.
>     These modifications resulted in some testcases needing to be
>     updated. The reasons
>     for updating are summarized below:
>     1. more optimized
>     vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>     avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>     2. less unnecessary fusion
>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>     3. local fuse direction (backward -> forward)
>        scalar_move-1.c/
>     4. add some bugfix testcases.
>        pr111037-3.c/pr111037-4.c
>        avl_single-89.c
>     PR target/111037
>     PR target/111234
>     PR target/111725
>     Lehua Ding (11):
>       RISC-V: P1: Refactor
>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>       RISC-V: P2: Refactor and cleanup demand system
>       RISC-V: P3: Refactor vector_infos_manager
>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>       RISC-V: P5: combine phase 1 and 2
>       RISC-V: P6: Add computing reaching definition data flow
>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>       RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
>       RISC-V: P9: Cleanup and reorganize helper functions
>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>       RISC-V: P11: Adjust and add testcases
>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 +++++++----------
>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>     gcc/config/riscv/t-riscv                      |    2 +-
>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>     vsetvl}/pr111037-1.c (100%)
>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>     vsetvl}/pr111037-2.c (100%)
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>     create mode 100644
>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>     -- 
>     2.36.3
>
  

Hi Patrick,

Thanks a lot for helping to test these patchs!

On 2023/10/20 2:04, Patrick O'Neill wrote:
> I tested it this morning on my machine and it passed!
> 
> Tested against:
> 04d6c74564b7eb51660a00b35353aeab706b5a50
> 
> Using targets:
> glibc rv32gcv qemu
> glibc rv64gcv qemu
> 
> This patch series does not introduce any new failures.
> 
> Here's a list of *resolved* failures by this patch series:
> rv64gcv:
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
> -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
> 
> rv32gcv:
> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
> -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
> 
> Thanks for the quick revision Lehua!
> 
> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
> 
> Patrick
> 
> On 10/19/23 01:50, 钟居哲 wrote:
>> LGTM now. But wait for Patrick CI testing.
>>
>> Hi, @Patrick. Could you apply this patch and trigger CI in your 
>> github  so that we can see the full running result.
>>
>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>
>> ------------------------------------------------------------------------
>> juzhe.zhong@rivai.ai
>>
>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>     *Date:* 2023-10-19 16:33
>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>     <mailto:lehua.ding@rivai.ai>
>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>     This patch refactors and cleanups the vsetvl pass in order to make
>>     the code
>>     easier to modify and understand. This patch does several things:
>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>>     only maintain
>>        and modify this virtual CFG. Phase 4 performs insertion,
>>     modification and
>>        deletion of vsetvl insns based on the virtual CFG. The Basic
>>     block in the
>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>     information inside
>>        is called vsetvl_info.
>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>     demand system,
>>        this Phase only fuse local vsetvl info in forward direction.
>>     3. Refactor Phase 3, change the logic for determining whether to
>>     uplift vsetvl
>>        info to a pred basic block to a more unified method that there
>>     is a vsetvl
>>        info in the vsetvl defintion reaching in compatible with it.
>>     4. Place all modification operations to the RTL in Phase 4 and
>>     Phase 5.
>>        Phase 4 is responsible for inserting, modifying and deleting vsetvl
>>        instructions based on fully optimized vsetvl infos. Phase 5
>>     removes the avl
>>        operand from the RVV instruction and removes the unused dest
>>     operand
>>        register from the vsetvl insns.
>>     These modifications resulted in some testcases needing to be
>>     updated. The reasons
>>     for updating are summarized below:
>>     1. more optimized
>>     vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>     avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>     2. less unnecessary fusion
>>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>     3. local fuse direction (backward -> forward)
>>        scalar_move-1.c/
>>     4. add some bugfix testcases.
>>        pr111037-3.c/pr111037-4.c
>>        avl_single-89.c
>>     PR target/111037
>>     PR target/111234
>>     PR target/111725
>>     Lehua Ding (11):
>>       RISC-V: P1: Refactor
>>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>       RISC-V: P2: Refactor and cleanup demand system
>>       RISC-V: P3: Refactor vector_infos_manager
>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>       RISC-V: P5: combine phase 1 and 2
>>       RISC-V: P6: Add computing reaching definition data flow
>>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
>>       RISC-V: P9: Cleanup and reorganize helper functions
>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>>       RISC-V: P11: Adjust and add testcases
>>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 +++++++----------
>>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>     gcc/config/riscv/t-riscv                      |    2 +-
>>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>     vsetvl}/pr111037-1.c (100%)
>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>     vsetvl}/pr111037-2.c (100%)
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>     -- 
>>     2.36.3
>>
  

Committed, thanks Patrick and Juzhe.

On 2023/10/20 2:04, Patrick O'Neill wrote:
> I tested it this morning on my machine and it passed!
> 
> Tested against:
> 04d6c74564b7eb51660a00b35353aeab706b5a50
> 
> Using targets:
> glibc rv32gcv qemu
> glibc rv64gcv qemu
> 
> This patch series does not introduce any new failures.
> 
> Here's a list of *resolved* failures by this patch series:
> rv64gcv:
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
> -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
> 
> rv32gcv:
> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer 
> -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test
> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
> 
> Thanks for the quick revision Lehua!
> 
> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
> 
> Patrick
> 
> On 10/19/23 01:50, 钟居哲 wrote:
>> LGTM now. But wait for Patrick CI testing.
>>
>> Hi, @Patrick. Could you apply this patch and trigger CI in your 
>> github  so that we can see the full running result.
>>
>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>
>> ------------------------------------------------------------------------
>> juzhe.zhong@rivai.ai
>>
>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>     *Date:* 2023-10-19 16:33
>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>     <mailto:lehua.ding@rivai.ai>
>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>     This patch refactors and cleanups the vsetvl pass in order to make
>>     the code
>>     easier to modify and understand. This patch does several things:
>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>>     only maintain
>>        and modify this virtual CFG. Phase 4 performs insertion,
>>     modification and
>>        deletion of vsetvl insns based on the virtual CFG. The Basic
>>     block in the
>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>     information inside
>>        is called vsetvl_info.
>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>     demand system,
>>        this Phase only fuse local vsetvl info in forward direction.
>>     3. Refactor Phase 3, change the logic for determining whether to
>>     uplift vsetvl
>>        info to a pred basic block to a more unified method that there
>>     is a vsetvl
>>        info in the vsetvl defintion reaching in compatible with it.
>>     4. Place all modification operations to the RTL in Phase 4 and
>>     Phase 5.
>>        Phase 4 is responsible for inserting, modifying and deleting vsetvl
>>        instructions based on fully optimized vsetvl infos. Phase 5
>>     removes the avl
>>        operand from the RVV instruction and removes the unused dest
>>     operand
>>        register from the vsetvl insns.
>>     These modifications resulted in some testcases needing to be
>>     updated. The reasons
>>     for updating are summarized below:
>>     1. more optimized
>>     vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>     avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>     2. less unnecessary fusion
>>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>     3. local fuse direction (backward -> forward)
>>        scalar_move-1.c/
>>     4. add some bugfix testcases.
>>        pr111037-3.c/pr111037-4.c
>>        avl_single-89.c
>>     PR target/111037
>>     PR target/111234
>>     PR target/111725
>>     Lehua Ding (11):
>>       RISC-V: P1: Refactor
>>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>       RISC-V: P2: Refactor and cleanup demand system
>>       RISC-V: P3: Refactor vector_infos_manager
>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>       RISC-V: P5: combine phase 1 and 2
>>       RISC-V: P6: Add computing reaching definition data flow
>>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization
>>       RISC-V: P9: Cleanup and reorganize helper functions
>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>>       RISC-V: P11: Adjust and add testcases
>>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 +++++++----------
>>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>     gcc/config/riscv/t-riscv                      |    2 +-
>>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>     vsetvl}/pr111037-1.c (100%)
>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>     vsetvl}/pr111037-2.c (100%)
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>     create mode 100644
>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>     -- 
>>     2.36.3
>>
  

Hi Lehua,

This patch causes a build failure with newlib 4.1.0 with -march=rv64gv_zbb.

I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941

Thanks,
Patrick

On 10/19/23 20:58, Lehua Ding wrote:
> Committed, thanks Patrick and Juzhe.
>
> On 2023/10/20 2:04, Patrick O'Neill wrote:
>> I tested it this morning on my machine and it passed!
>>
>> Tested against:
>> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>
>> Using targets:
>> glibc rv32gcv qemu
>> glibc rv64gcv qemu
>>
>> This patch series does not introduce any new failures.
>>
>> Here's a list of *resolved* failures by this patch series:
>> rv64gcv:
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> rv32gcv:
>> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> Thanks for the quick revision Lehua!
>>
>> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>>
>> Patrick
>>
>> On 10/19/23 01:50, 钟居哲 wrote:
>>> LGTM now. But wait for Patrick CI testing.
>>>
>>> Hi, @Patrick. Could you apply this patch and trigger CI in your 
>>> github  so that we can see the full running result.
>>>
>>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
>>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>>
>>> ------------------------------------------------------------------------ 
>>>
>>> juzhe.zhong@rivai.ai
>>>
>>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>>     *Date:* 2023-10-19 16:33
>>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>>>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>>     <mailto:lehua.ding@rivai.ai>
>>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>>     This patch refactors and cleanups the vsetvl pass in order to make
>>>     the code
>>>     easier to modify and understand. This patch does several things:
>>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>>>     only maintain
>>>        and modify this virtual CFG. Phase 4 performs insertion,
>>>     modification and
>>>        deletion of vsetvl insns based on the virtual CFG. The Basic
>>>     block in the
>>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>>     information inside
>>>        is called vsetvl_info.
>>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>>     demand system,
>>>        this Phase only fuse local vsetvl info in forward direction.
>>>     3. Refactor Phase 3, change the logic for determining whether to
>>>     uplift vsetvl
>>>        info to a pred basic block to a more unified method that there
>>>     is a vsetvl
>>>        info in the vsetvl defintion reaching in compatible with it.
>>>     4. Place all modification operations to the RTL in Phase 4 and
>>>     Phase 5.
>>>        Phase 4 is responsible for inserting, modifying and deleting 
>>> vsetvl
>>>        instructions based on fully optimized vsetvl infos. Phase 5
>>>     removes the avl
>>>        operand from the RVV instruction and removes the unused dest
>>>     operand
>>>        register from the vsetvl insns.
>>>     These modifications resulted in some testcases needing to be
>>>     updated. The reasons
>>>     for updating are summarized below:
>>>     1. more optimized
>>> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>>     2. less unnecessary fusion
>>>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>>     3. local fuse direction (backward -> forward)
>>>        scalar_move-1.c/
>>>     4. add some bugfix testcases.
>>>        pr111037-3.c/pr111037-4.c
>>>        avl_single-89.c
>>>     PR target/111037
>>>     PR target/111234
>>>     PR target/111725
>>>     Lehua Ding (11):
>>>       RISC-V: P1: Refactor
>>>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>>       RISC-V: P2: Refactor and cleanup demand system
>>>       RISC-V: P3: Refactor vector_infos_manager
>>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>>       RISC-V: P5: combine phase 1 and 2
>>>       RISC-V: P6: Add computing reaching definition data flow
>>>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post 
>>> optimization
>>>       RISC-V: P9: Cleanup and reorganize helper functions
>>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>>>       RISC-V: P11: Adjust and add testcases
>>>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 
>>> +++++++----------
>>>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>>     gcc/config/riscv/t-riscv                      |    2 +-
>>>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-1.c (100%)
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-2.c (100%)
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>>     --     2.36.3
>>>
>
  

I have fixed it: 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660

Plz verify it and send a patch with testcase pr111941.c if you confirm it has been fixed on the trunk.

Thanks.


juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 02:30
To: Lehua Ding
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches; 钟居哲
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
Hi Lehua,
 
This patch causes a build failure with newlib 4.1.0 with -march=rv64gv_zbb.
 
I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
 
Thanks,
Patrick
 
On 10/19/23 20:58, Lehua Ding wrote:
> Committed, thanks Patrick and Juzhe.
>
> On 2023/10/20 2:04, Patrick O'Neill wrote:
>> I tested it this morning on my machine and it passed!
>>
>> Tested against:
>> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>
>> Using targets:
>> glibc rv32gcv qemu
>> glibc rv64gcv qemu
>>
>> This patch series does not introduce any new failures.
>>
>> Here's a list of *resolved* failures by this patch series:
>> rv64gcv:
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> rv32gcv:
>> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> Thanks for the quick revision Lehua!
>>
>> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>>
>> Patrick
>>
>> On 10/19/23 01:50, 钟居哲 wrote:
>>> LGTM now. But wait for Patrick CI testing.
>>>
>>> Hi, @Patrick. Could you apply this patch and trigger CI in your 
>>> github  so that we can see the full running result.
>>>
>>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
>>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>>
>>> ------------------------------------------------------------------------ 
>>>
>>> juzhe.zhong@rivai.ai
>>>
>>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>>     *Date:* 2023-10-19 16:33
>>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>>>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>>     <mailto:lehua.ding@rivai.ai>
>>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>>     This patch refactors and cleanups the vsetvl pass in order to make
>>>     the code
>>>     easier to modify and understand. This patch does several things:
>>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>>>     only maintain
>>>        and modify this virtual CFG. Phase 4 performs insertion,
>>>     modification and
>>>        deletion of vsetvl insns based on the virtual CFG. The Basic
>>>     block in the
>>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>>     information inside
>>>        is called vsetvl_info.
>>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>>     demand system,
>>>        this Phase only fuse local vsetvl info in forward direction.
>>>     3. Refactor Phase 3, change the logic for determining whether to
>>>     uplift vsetvl
>>>        info to a pred basic block to a more unified method that there
>>>     is a vsetvl
>>>        info in the vsetvl defintion reaching in compatible with it.
>>>     4. Place all modification operations to the RTL in Phase 4 and
>>>     Phase 5.
>>>        Phase 4 is responsible for inserting, modifying and deleting 
>>> vsetvl
>>>        instructions based on fully optimized vsetvl infos. Phase 5
>>>     removes the avl
>>>        operand from the RVV instruction and removes the unused dest
>>>     operand
>>>        register from the vsetvl insns.
>>>     These modifications resulted in some testcases needing to be
>>>     updated. The reasons
>>>     for updating are summarized below:
>>>     1. more optimized
>>> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>>     2. less unnecessary fusion
>>>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>>     3. local fuse direction (backward -> forward)
>>>        scalar_move-1.c/
>>>     4. add some bugfix testcases.
>>>        pr111037-3.c/pr111037-4.c
>>>        avl_single-89.c
>>>     PR target/111037
>>>     PR target/111234
>>>     PR target/111725
>>>     Lehua Ding (11):
>>>       RISC-V: P1: Refactor
>>>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>>       RISC-V: P2: Refactor and cleanup demand system
>>>       RISC-V: P3: Refactor vector_infos_manager
>>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>>       RISC-V: P5: combine phase 1 and 2
>>>       RISC-V: P6: Add computing reaching definition data flow
>>>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post 
>>> optimization
>>>       RISC-V: P9: Cleanup and reorganize helper functions
>>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>>>       RISC-V: P11: Adjust and add testcases
>>>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 
>>> +++++++----------
>>>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>>     gcc/config/riscv/t-riscv                      |    2 +-
>>>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-1.c (100%)
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-2.c (100%)
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>>     --     2.36.3
>>>
>
  

You're on top of it - thanks for fixing this! I'll send the testcase.

Unrelated to this failure, I'm seeing a build failure on glibc 
rv32/64gcv when RTL checking is enabled.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Thanks,
Patrick

On 10/23/23 14:41, 钟居哲 wrote:
> I have fixed it:
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660
>
> Plz verify it and send a patch with testcase pr111941.c if you confirm 
> it has been fixed on the trunk.
>
> Thanks.
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
>     *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
>     *Date:* 2023-10-24 02:30
>     *To:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>     *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; rdapp.gcc
>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>     Jeff Law <mailto:jeffreyalaw@gmail.com>; gcc-patches
>     <mailto:gcc-patches@gcc.gnu.org>; 钟居哲 <mailto:juzhe.zhong@rivai.ai>
>     *Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>     Hi Lehua,
>     This patch causes a build failure with newlib 4.1.0 with
>     -march=rv64gv_zbb.
>     I've creduced the failure here:
>     https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
>     Thanks,
>     Patrick
>     On 10/19/23 20:58, Lehua Ding wrote:
>     > Committed, thanks Patrick and Juzhe.
>     >
>     > On 2023/10/20 2:04, Patrick O'Neill wrote:
>     >> I tested it this morning on my machine and it passed!
>     >>
>     >> Tested against:
>     >> 04d6c74564b7eb51660a00b35353aeab706b5a50
>     >>
>     >> Using targets:
>     >> glibc rv32gcv qemu
>     >> glibc rv64gcv qemu
>     >>
>     >> This patch series does not introduce any new failures.
>     >>
>     >> Here's a list of *resolved* failures by this patch series:
>     >> rv64gcv:
>     >> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3
>     >> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
>     >> -finline-functions  execution test
>     >> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g  execution test
>     >>
>     >> rv32gcv:
>     >> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
>     execution test
>     >> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3
>     >> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
>     >> -finline-functions  execution test
>     >> FAIL: gfortran.dg/host_assoc_function_7.f90 -O3 -g  execution test
>     >>
>     >> Thanks for the quick revision Lehua!
>     >>
>     >> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>     >>
>     >> Patrick
>     >>
>     >> On 10/19/23 01:50, 钟居哲 wrote:
>     >>> LGTM now. But wait for Patrick CI testing.
>     >>>
>     >>> Hi, @Patrick. Could you apply this patch and trigger CI in your
>     >>> github  so that we can see the full running result.
>     >>>
>     >>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub
>     >>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>     >>>
>     >>>
>     ------------------------------------------------------------------------
>
>     >>>
>     >>> juzhe.zhong@rivai.ai
>     >>>
>     >>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>     >>>     *Date:* 2023-10-19 16:33
>     >>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>     >>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>     >>> <mailto:kito.cheng@gmail.com>; rdapp.gcc
>     >>> <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>     >>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>     >>> <mailto:lehua.ding@rivai.ai>
>     >>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>     >>>     This patch refactors and cleanups the vsetvl pass in order
>     to make
>     >>>     the code
>     >>>     easier to modify and understand. This patch does several
>     things:
>     >>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1,
>     2 and 3
>     >>>     only maintain
>     >>>        and modify this virtual CFG. Phase 4 performs insertion,
>     >>>     modification and
>     >>>        deletion of vsetvl insns based on the virtual CFG. The
>     Basic
>     >>>     block in the
>     >>>        virtual CFG is called vsetvl_block_info and the vsetvl
>     >>>     information inside
>     >>>        is called vsetvl_info.
>     >>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>     >>>     demand system,
>     >>>        this Phase only fuse local vsetvl info in forward
>     direction.
>     >>>     3. Refactor Phase 3, change the logic for determining
>     whether to
>     >>>     uplift vsetvl
>     >>>        info to a pred basic block to a more unified method
>     that there
>     >>>     is a vsetvl
>     >>>        info in the vsetvl defintion reaching in compatible
>     with it.
>     >>>     4. Place all modification operations to the RTL in Phase 4 and
>     >>>     Phase 5.
>     >>>        Phase 4 is responsible for inserting, modifying and
>     deleting
>     >>> vsetvl
>     >>>        instructions based on fully optimized vsetvl infos. Phase 5
>     >>>     removes the avl
>     >>>        operand from the RVV instruction and removes the unused
>     dest
>     >>>     operand
>     >>>        register from the vsetvl insns.
>     >>>     These modifications resulted in some testcases needing to be
>     >>>     updated. The reasons
>     >>>     for updating are summarized below:
>     >>>     1. more optimized
>     >>> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>     >>> vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>     >>> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>     >>>     2. less unnecessary fusion
>     >>> avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>     >>>     3. local fuse direction (backward -> forward)
>     >>>        scalar_move-1.c/
>     >>>     4. add some bugfix testcases.
>     >>>        pr111037-3.c/pr111037-4.c
>     >>>        avl_single-89.c
>     >>>     PR target/111037
>     >>>     PR target/111234
>     >>>     PR target/111725
>     >>>     Lehua Ding (11):
>     >>>       RISC-V: P1: Refactor
>     >>> avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>     >>>       RISC-V: P2: Refactor and cleanup demand system
>     >>>       RISC-V: P3: Refactor vector_infos_manager
>     >>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>     >>>       RISC-V: P5: combine phase 1 and 2
>     >>>       RISC-V: P6: Add computing reaching definition data flow
>     >>>       RISC-V: P7: Move earliest fuse and lcm code to
>     pre_vsetvl class
>     >>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post
>     >>> optimization
>     >>>       RISC-V: P9: Cleanup and reorganize helper functions
>     >>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust
>     riscv-vsetvl.def
>     >>>       RISC-V: P11: Adjust and add testcases
>     >>> gcc/config/riscv/riscv-vsetvl.cc              | 6502
>     >>> +++++++----------
>     >>> gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>     >>> gcc/config/riscv/riscv-vsetvl.h               |  488 --
>     >>> gcc/config/riscv/t-riscv                      |    2 +-
>     >>> .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>     >>> .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>     >>> .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>     >>> .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>     >>> .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>     >>> .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>     >>> .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>     >>> .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>     >>> .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>     >>> .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>     >>> .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>     >>> .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>     >>> .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>     >>> .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>     >>> .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>     >>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>     >>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>     >>> .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>     >>> .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>     >>> .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>     >>> .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>     >>> .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>     >>> .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>     >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>     >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>     >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>     >>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>     >>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>     >>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>     >>>     vsetvl}/pr111037-1.c (100%)
>     >>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>     >>>     vsetvl}/pr111037-2.c (100%)
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>     >>>     create mode 100644
>     >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>     >>>     --     2.36.3
>     >>>
>     >
>
  

I didn't reproduce it. How to enable RTL checking ?



juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 06:46
To: 钟居哲; 丁乐华
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
You're on top of it - thanks for fixing this! I'll send the testcase.

Unrelated to this failure, I'm seeing a build failure on glibc rv32/64gcv when RTL checking is enabled.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Thanks,
Patrick
On 10/23/23 14:41, 钟居哲 wrote:
I have fixed it: 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660

Plz verify it and send a patch with testcase pr111941.c if you confirm it has been fixed on the trunk.

Thanks.


juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 02:30
To: Lehua Ding
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches; 钟居哲
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
Hi Lehua,
 
This patch causes a build failure with newlib 4.1.0 with -march=rv64gv_zbb.
 
I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
 
Thanks,
Patrick
 
On 10/19/23 20:58, Lehua Ding wrote:
> Committed, thanks Patrick and Juzhe.
>
> On 2023/10/20 2:04, Patrick O'Neill wrote:
>> I tested it this morning on my machine and it passed!
>>
>> Tested against:
>> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>
>> Using targets:
>> glibc rv32gcv qemu
>> glibc rv64gcv qemu
>>
>> This patch series does not introduce any new failures.
>>
>> Here's a list of *resolved* failures by this patch series:
>> rv64gcv:
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> rv32gcv:
>> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> Thanks for the quick revision Lehua!
>>
>> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>>
>> Patrick
>>
>> On 10/19/23 01:50, 钟居哲 wrote:
>>> LGTM now. But wait for Patrick CI testing.
>>>
>>> Hi, @Patrick. Could you apply this patch and trigger CI in your 
>>> github  so that we can see the full running result.
>>>
>>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
>>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>>
>>> ------------------------------------------------------------------------ 
>>>
>>> juzhe.zhong@rivai.ai
>>>
>>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>>     *Date:* 2023-10-19 16:33
>>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>>>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>>     <mailto:lehua.ding@rivai.ai>
>>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>>     This patch refactors and cleanups the vsetvl pass in order to make
>>>     the code
>>>     easier to modify and understand. This patch does several things:
>>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>>>     only maintain
>>>        and modify this virtual CFG. Phase 4 performs insertion,
>>>     modification and
>>>        deletion of vsetvl insns based on the virtual CFG. The Basic
>>>     block in the
>>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>>     information inside
>>>        is called vsetvl_info.
>>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>>     demand system,
>>>        this Phase only fuse local vsetvl info in forward direction.
>>>     3. Refactor Phase 3, change the logic for determining whether to
>>>     uplift vsetvl
>>>        info to a pred basic block to a more unified method that there
>>>     is a vsetvl
>>>        info in the vsetvl defintion reaching in compatible with it.
>>>     4. Place all modification operations to the RTL in Phase 4 and
>>>     Phase 5.
>>>        Phase 4 is responsible for inserting, modifying and deleting 
>>> vsetvl
>>>        instructions based on fully optimized vsetvl infos. Phase 5
>>>     removes the avl
>>>        operand from the RVV instruction and removes the unused dest
>>>     operand
>>>        register from the vsetvl insns.
>>>     These modifications resulted in some testcases needing to be
>>>     updated. The reasons
>>>     for updating are summarized below:
>>>     1. more optimized
>>> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>>     2. less unnecessary fusion
>>>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>>     3. local fuse direction (backward -> forward)
>>>        scalar_move-1.c/
>>>     4. add some bugfix testcases.
>>>        pr111037-3.c/pr111037-4.c
>>>        avl_single-89.c
>>>     PR target/111037
>>>     PR target/111234
>>>     PR target/111725
>>>     Lehua Ding (11):
>>>       RISC-V: P1: Refactor
>>>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>>       RISC-V: P2: Refactor and cleanup demand system
>>>       RISC-V: P3: Refactor vector_infos_manager
>>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>>       RISC-V: P5: combine phase 1 and 2
>>>       RISC-V: P6: Add computing reaching definition data flow
>>>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post 
>>> optimization
>>>       RISC-V: P9: Cleanup and reorganize helper functions
>>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>>>       RISC-V: P11: Adjust and add testcases
>>>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 
>>> +++++++----------
>>>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>>     gcc/config/riscv/t-riscv                      |    2 +-
>>>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-1.c (100%)
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-2.c (100%)
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>>     --     2.36.3
>>>
>
  

When configuring, pass in --enable-checking=rtl
If you're using riscv-gnu-toolchain, pass in --enable-gcc-checking=rtl

The -freport-bug output attached to the bug report has the full 
configure command used:
/scratch/tc-testing/tc-trunk/build-rtl-checking/../gcc/configure 
--target=riscv64-unknown-linux-gnu 
--prefix=/scratch/tc-testing/tc-trunk/build-rtl-checking 
--with-sysroot=/scratch/tc-testing/tc-trunk/build-rtl-checking/sysroot 
--with-newlib --without-headers --disable-shared --disable-threads 
--with-system-zlib --enable-tls --enable-languages=c --disable-libatomic 
--disable-libmudflap --disable-libssp --disable-libquadmath 
--disable-libgomp --disable-nls --disable-bootstrap --src=../../gcc 
--enable-checking=rtl --disable-multilib --with-abi=lp64d 
--with-arch=rv64gcv --with-tune=rocket --with-isa-spec=20191213 
'CFLAGS_FOR_TARGET=-O2    -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-O2    
-mcmodel=medlow'

On 10/23/23 15:50, 钟居哲 wrote:
> I didn't reproduce it. How to enable RTL checking ?
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
>     *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
>     *Date:* 2023-10-24 06:46
>     *To:* 钟居哲 <mailto:juzhe.zhong@rivai.ai>; 丁乐华
>     <mailto:lehua.ding@rivai.ai>
>     *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; rdapp.gcc
>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>     Jeff Law <mailto:jeffreyalaw@gmail.com>; gcc-patches
>     <mailto:gcc-patches@gcc.gnu.org>
>     *Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>
>     You're on top of it - thanks for fixing this! I'll send the testcase.
>
>     Unrelated to this failure, I'm seeing a build failure on glibc
>     rv32/64gcv when RTL checking is enabled.
>     https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947
>
>     Thanks,
>     Patrick
>
>     On 10/23/23 14:41, 钟居哲 wrote:
>>     I have fixed it:
>>     https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660
>>
>>     Plz verify it and send a patch with testcase pr111941.c if you
>>     confirm it has been fixed on the trunk.
>>
>>     Thanks.
>>     ------------------------------------------------------------------------
>>     juzhe.zhong@rivai.ai
>>
>>         *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
>>         *Date:* 2023-10-24 02:30
>>         *To:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>         *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>         <mailto:rdapp.gcc@gmail.com>; palmer
>>         <mailto:palmer@rivosinc.com>; Jeff Law
>>         <mailto:jeffreyalaw@gmail.com>; gcc-patches
>>         <mailto:gcc-patches@gcc.gnu.org>; 钟居哲
>>         <mailto:juzhe.zhong@rivai.ai>
>>         *Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>         Hi Lehua,
>>         This patch causes a build failure with newlib 4.1.0 with
>>         -march=rv64gv_zbb.
>>         I've creduced the failure here:
>>         https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
>>         Thanks,
>>         Patrick
>>         On 10/19/23 20:58, Lehua Ding wrote:
>>         > Committed, thanks Patrick and Juzhe.
>>         >
>>         > On 2023/10/20 2:04, Patrick O'Neill wrote:
>>         >> I tested it this morning on my machine and it passed!
>>         >>
>>         >> Tested against:
>>         >> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>         >>
>>         >> Using targets:
>>         >> glibc rv32gcv qemu
>>         >> glibc rv64gcv qemu
>>         >>
>>         >> This patch series does not introduce any new failures.
>>         >>
>>         >> Here's a list of *resolved* failures by this patch series:
>>         >> rv64gcv:
>>         >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3
>>         >> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
>>         >> -finline-functions  execution test
>>         >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g
>>         execution test
>>         >>
>>         >> rv32gcv:
>>         >> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
>>         execution test
>>         >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3
>>         >> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer
>>         >> -finline-functions  execution test
>>         >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g
>>         execution test
>>         >>
>>         >> Thanks for the quick revision Lehua!
>>         >>
>>         >> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>>         >>
>>         >> Patrick
>>         >>
>>         >> On 10/19/23 01:50, 钟居哲 wrote:
>>         >>> LGTM now. But wait for Patrick CI testing.
>>         >>>
>>         >>> Hi, @Patrick. Could you apply this patch and trigger CI
>>         in your
>>         >>> github  so that we can see the full running result.
>>         >>>
>>         >>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub
>>         >>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>         >>>
>>         >>>
>>         ------------------------------------------------------------------------
>>
>>         >>>
>>         >>> juzhe.zhong@rivai.ai
>>         >>>
>>         >>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>         >>>     *Date:* 2023-10-19 16:33
>>         >>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>         >>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>;
>>         kito.cheng
>>         >>> <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>         >>> <mailto:rdapp.gcc@gmail.com>; palmer
>>         <mailto:palmer@rivosinc.com>;
>>         >>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>         >>> <mailto:lehua.ding@rivai.ai>
>>         >>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup
>>         vsetvl pass
>>         >>>     This patch refactors and cleanups the vsetvl pass in
>>         order to make
>>         >>>     the code
>>         >>>     easier to modify and understand. This patch does
>>         several things:
>>         >>>     1. Introducing a virtual CFG for vsetvl infos and
>>         Phase 1, 2 and 3
>>         >>>     only maintain
>>         >>>        and modify this virtual CFG. Phase 4 performs
>>         insertion,
>>         >>>     modification and
>>         >>>        deletion of vsetvl insns based on the virtual CFG.
>>         The Basic
>>         >>>     block in the
>>         >>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>         >>>     information inside
>>         >>>        is called vsetvl_info.
>>         >>>     2. Combine Phase 1 and 2 into a single Phase 1 and
>>         unified the
>>         >>>     demand system,
>>         >>>        this Phase only fuse local vsetvl info in forward
>>         direction.
>>         >>>     3. Refactor Phase 3, change the logic for determining
>>         whether to
>>         >>>     uplift vsetvl
>>         >>>        info to a pred basic block to a more unified
>>         method that there
>>         >>>     is a vsetvl
>>         >>>        info in the vsetvl defintion reaching in
>>         compatible with it.
>>         >>>     4. Place all modification operations to the RTL in
>>         Phase 4 and
>>         >>>     Phase 5.
>>         >>>        Phase 4 is responsible for inserting, modifying
>>         and deleting
>>         >>> vsetvl
>>         >>>        instructions based on fully optimized vsetvl
>>         infos. Phase 5
>>         >>>     removes the avl
>>         >>>        operand from the RVV instruction and removes the
>>         unused dest
>>         >>>     operand
>>         >>>        register from the vsetvl insns.
>>         >>>     These modifications resulted in some testcases
>>         needing to be
>>         >>>     updated. The reasons
>>         >>>     for updating are summarized below:
>>         >>>     1. more optimized
>>         >>> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>         >>> vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>         >>> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>         >>>     2. less unnecessary fusion
>>         >>> avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>         >>>     3. local fuse direction (backward -> forward)
>>         >>>        scalar_move-1.c/
>>         >>>     4. add some bugfix testcases.
>>         >>>        pr111037-3.c/pr111037-4.c
>>         >>>        avl_single-89.c
>>         >>>     PR target/111037
>>         >>>     PR target/111234
>>         >>>     PR target/111725
>>         >>>     Lehua Ding (11):
>>         >>>       RISC-V: P1: Refactor
>>         >>> avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>         >>>       RISC-V: P2: Refactor and cleanup demand system
>>         >>>       RISC-V: P3: Refactor vector_infos_manager
>>         >>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>         >>>       RISC-V: P5: combine phase 1 and 2
>>         >>>       RISC-V: P6: Add computing reaching definition data flow
>>         >>>       RISC-V: P7: Move earliest fuse and lcm code to
>>         pre_vsetvl class
>>         >>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post
>>         >>> optimization
>>         >>>       RISC-V: P9: Cleanup and reorganize helper functions
>>         >>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust
>>         riscv-vsetvl.def
>>         >>>       RISC-V: P11: Adjust and add testcases
>>         >>> gcc/config/riscv/riscv-vsetvl.cc              | 6502
>>         >>> +++++++----------
>>         >>> gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>         >>> gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>         >>> gcc/config/riscv/t-riscv                      |    2 +-
>>         >>> .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>         >>> .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>         >>> .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>         >>> .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>         >>> .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>         >>> .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>         >>> .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>         >>> .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>         >>> .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>         >>> .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>         >>> .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>         >>> .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>         >>> .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>         >>> .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>         >>> .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>         >>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>         >>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>         >>> .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>         >>> .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>         >>> .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>         >>> .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>         >>> .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>         >>> .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>         >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>         >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>         >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>         >>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>         >>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>         >>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>         >>>     vsetvl}/pr111037-1.c (100%)
>>         >>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>         >>>     vsetvl}/pr111037-2.c (100%)
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>         >>>     create mode 100644
>>         >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>         >>>     --     2.36.3
>>         >>>
>>         >
>>
  

I don't have such issue:

[jzzhong@rios-cad121:/work/home/jzzhong/work/insn]$~/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/libexec/gcc/riscv64-unknown-elf/14.0.0/lto-wrapper
Target: riscv64-unknown-elf
Configured with: /work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/../../gcc/configure --target=riscv64-unknown-elf --prefix=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install --disable-shared --disable-threads --enable-languages=c,c++ --with-pkgversion=g70b66ac9bcb-dirty --with-system-zlib --enable-tls --with-newlib --with-sysroot=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/riscv64-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=../../../gcc --enable-checking=yes --disable-multilib --with-abi=lp64d --with-arch=rv64gcv_zfh_zvfh --with-tune=rocket --with-isa-spec=20191213 CFLAGS='-O0 -g3' CXXFLAGS='-O0 -g3' 'CFLAGS_FOR_TARGET=-Os    -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-Os    -mcmodel=medany'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)




juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 07:42
To: 钟居哲; 丁乐华
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
When configuring, pass in --enable-checking=rtl
If you're using riscv-gnu-toolchain, pass in --enable-gcc-checking=rtl

The -freport-bug output attached to the bug report has the full configure command used:
/scratch/tc-testing/tc-trunk/build-rtl-checking/../gcc/configure --target=riscv64-unknown-linux-gnu --prefix=/scratch/tc-testing/tc-trunk/build-rtl-checking --with-sysroot=/scratch/tc-testing/tc-trunk/build-rtl-checking/sysroot --with-newlib --without-headers --disable-shared --disable-threads --with-system-zlib --enable-tls --enable-languages=c --disable-libatomic --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-bootstrap --src=../../gcc --enable-checking=rtl --disable-multilib --with-abi=lp64d --with-arch=rv64gcv --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2    -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medlow'

On 10/23/23 15:50, 钟居哲 wrote:
I didn't reproduce it. How to enable RTL checking ?



juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 06:46
To: 钟居哲; 丁乐华
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
You're on top of it - thanks for fixing this! I'll send the testcase.

Unrelated to this failure, I'm seeing a build failure on glibc rv32/64gcv when RTL checking is enabled.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Thanks,
Patrick
On 10/23/23 14:41, 钟居哲 wrote:
I have fixed it: 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660

Plz verify it and send a patch with testcase pr111941.c if you confirm it has been fixed on the trunk.

Thanks.


juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 02:30
To: Lehua Ding
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches; 钟居哲
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
Hi Lehua,
 
This patch causes a build failure with newlib 4.1.0 with -march=rv64gv_zbb.
 
I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
 
Thanks,
Patrick
 
On 10/19/23 20:58, Lehua Ding wrote:
> Committed, thanks Patrick and Juzhe.
>
> On 2023/10/20 2:04, Patrick O'Neill wrote:
>> I tested it this morning on my machine and it passed!
>>
>> Tested against:
>> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>
>> Using targets:
>> glibc rv32gcv qemu
>> glibc rv64gcv qemu
>>
>> This patch series does not introduce any new failures.
>>
>> Here's a list of *resolved* failures by this patch series:
>> rv64gcv:
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> rv32gcv:
>> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> Thanks for the quick revision Lehua!
>>
>> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>>
>> Patrick
>>
>> On 10/19/23 01:50, 钟居哲 wrote:
>>> LGTM now. But wait for Patrick CI testing.
>>>
>>> Hi, @Patrick. Could you apply this patch and trigger CI in your 
>>> github  so that we can see the full running result.
>>>
>>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
>>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>>
>>> ------------------------------------------------------------------------ 
>>>
>>> juzhe.zhong@rivai.ai
>>>
>>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>>     *Date:* 2023-10-19 16:33
>>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>>>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>>     <mailto:lehua.ding@rivai.ai>
>>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>>     This patch refactors and cleanups the vsetvl pass in order to make
>>>     the code
>>>     easier to modify and understand. This patch does several things:
>>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>>>     only maintain
>>>        and modify this virtual CFG. Phase 4 performs insertion,
>>>     modification and
>>>        deletion of vsetvl insns based on the virtual CFG. The Basic
>>>     block in the
>>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>>     information inside
>>>        is called vsetvl_info.
>>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>>     demand system,
>>>        this Phase only fuse local vsetvl info in forward direction.
>>>     3. Refactor Phase 3, change the logic for determining whether to
>>>     uplift vsetvl
>>>        info to a pred basic block to a more unified method that there
>>>     is a vsetvl
>>>        info in the vsetvl defintion reaching in compatible with it.
>>>     4. Place all modification operations to the RTL in Phase 4 and
>>>     Phase 5.
>>>        Phase 4 is responsible for inserting, modifying and deleting 
>>> vsetvl
>>>        instructions based on fully optimized vsetvl infos. Phase 5
>>>     removes the avl
>>>        operand from the RVV instruction and removes the unused dest
>>>     operand
>>>        register from the vsetvl insns.
>>>     These modifications resulted in some testcases needing to be
>>>     updated. The reasons
>>>     for updating are summarized below:
>>>     1. more optimized
>>> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>>     2. less unnecessary fusion
>>>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>>     3. local fuse direction (backward -> forward)
>>>        scalar_move-1.c/
>>>     4. add some bugfix testcases.
>>>        pr111037-3.c/pr111037-4.c
>>>        avl_single-89.c
>>>     PR target/111037
>>>     PR target/111234
>>>     PR target/111725
>>>     Lehua Ding (11):
>>>       RISC-V: P1: Refactor
>>>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>>       RISC-V: P2: Refactor and cleanup demand system
>>>       RISC-V: P3: Refactor vector_infos_manager
>>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>>       RISC-V: P5: combine phase 1 and 2
>>>       RISC-V: P6: Add computing reaching definition data flow
>>>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post 
>>> optimization
>>>       RISC-V: P9: Cleanup and reorganize helper functions
>>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>>>       RISC-V: P11: Adjust and add testcases
>>>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 
>>> +++++++----------
>>>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>>     gcc/config/riscv/t-riscv                      |    2 +-
>>>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-1.c (100%)
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-2.c (100%)
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>>     --     2.36.3
>>>
>
  

IIRC --enable-checking=yes does not turn on RTL checking.
You need to pass in rtl explicitly using --enable-checking=rtl
You can also pass in a list of checks like this: --enable-checking=yes,rtl

Patrick

On 10/23/23 17:51, juzhe.zhong@rivai.ai wrote:
> I don't have such issue:
>
> [jzzhong@rios-cad121:/work/home/jzzhong/work/insn]$~/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc 
> -v
> Using built-in specs.
> COLLECT_GCC=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc
> COLLECT_LTO_WRAPPER=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/libexec/gcc/riscv64-unknown-elf/14.0.0/lto-wrapper
> Target: riscv64-unknown-elf
> Configured with: 
> /work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/../../gcc/configure 
> --target=riscv64-unknown-elf 
> --prefix=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install 
> --disable-shared --disable-threads --enable-languages=c,c++ 
> --with-pkgversion=g70b66ac9bcb-dirty --with-system-zlib --enable-tls 
> --with-newlib 
> --with-sysroot=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/riscv64-unknown-elf 
> --with-native-system-header-dir=/include --disable-libmudflap 
> --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls 
> --disable-tm-clone-registry --src=../../../gcc --enable-checking=yes 
> --disable-multilib --with-abi=lp64d --with-arch=rv64gcv_zfh_zvfh 
> --with-tune=rocket --with-isa-spec=20191213 CFLAGS='-O0 -g3' 
> CXXFLAGS='-O0 -g3' 'CFLAGS_FOR_TARGET=-Os    -mcmodel=medany' 
> 'CXXFLAGS_FOR_TARGET=-Os    -mcmodel=medany'
> Thread model: single
> Supported LTO compression algorithms: zlib
> gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)
>
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
>     *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
>     *Date:* 2023-10-24 07:42
>     *To:* 钟居哲 <mailto:juzhe.zhong@rivai.ai>; 丁乐华
>     <mailto:lehua.ding@rivai.ai>
>     *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; rdapp.gcc
>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>     Jeff Law <mailto:jeffreyalaw@gmail.com>; gcc-patches
>     <mailto:gcc-patches@gcc.gnu.org>
>     *Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>
>     When configuring, pass in --enable-checking=rtl
>     If you're using riscv-gnu-toolchain, pass in --enable-gcc-checking=rtl
>
>     The -freport-bug output attached to the bug report has the full
>     configure command used:
>     /scratch/tc-testing/tc-trunk/build-rtl-checking/../gcc/configure
>     --target=riscv64-unknown-linux-gnu
>     --prefix=/scratch/tc-testing/tc-trunk/build-rtl-checking
>     --with-sysroot=/scratch/tc-testing/tc-trunk/build-rtl-checking/sysroot
>     --with-newlib --without-headers --disable-shared --disable-threads
>     --with-system-zlib --enable-tls --enable-languages=c
>     --disable-libatomic --disable-libmudflap --disable-libssp
>     --disable-libquadmath --disable-libgomp --disable-nls
>     --disable-bootstrap --src=../../gcc --enable-checking=rtl
>     --disable-multilib --with-abi=lp64d --with-arch=rv64gcv
>     --with-tune=rocket --with-isa-spec=20191213
>     'CFLAGS_FOR_TARGET=-O2    -mcmodel=medlow'
>     'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medlow'
>
>     On 10/23/23 15:50, 钟居哲 wrote:
>>     I didn't reproduce it. How to enable RTL checking ?
>>
>>     ------------------------------------------------------------------------
>>     juzhe.zhong@rivai.ai
>>
>>         *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
>>         *Date:* 2023-10-24 06:46
>>         *To:* 钟居哲 <mailto:juzhe.zhong@rivai.ai>; 丁乐华
>>         <mailto:lehua.ding@rivai.ai>
>>         *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>         <mailto:rdapp.gcc@gmail.com>; palmer
>>         <mailto:palmer@rivosinc.com>; Jeff Law
>>         <mailto:jeffreyalaw@gmail.com>; gcc-patches
>>         <mailto:gcc-patches@gcc.gnu.org>
>>         *Subject:* Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>
>>         You're on top of it - thanks for fixing this! I'll send the
>>         testcase.
>>
>>         Unrelated to this failure, I'm seeing a build failure on
>>         glibc rv32/64gcv when RTL checking is enabled.
>>         https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947
>>
>>         Thanks,
>>         Patrick
>>
>>         On 10/23/23 14:41, 钟居哲 wrote:
>>>         I have fixed it:
>>>         https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660
>>>
>>>         Plz verify it and send a patch with testcase pr111941.c if
>>>         you confirm it has been fixed on the trunk.
>>>
>>>         Thanks.
>>>         ------------------------------------------------------------------------
>>>         juzhe.zhong@rivai.ai
>>>
>>>             *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
>>>             *Date:* 2023-10-24 02:30
>>>             *To:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>>             *CC:* kito.cheng <mailto:kito.cheng@gmail.com>;
>>>             rdapp.gcc <mailto:rdapp.gcc@gmail.com>; palmer
>>>             <mailto:palmer@rivosinc.com>; Jeff Law
>>>             <mailto:jeffreyalaw@gmail.com>; gcc-patches
>>>             <mailto:gcc-patches@gcc.gnu.org>; 钟居哲
>>>             <mailto:juzhe.zhong@rivai.ai>
>>>             *Subject:* Re: [PATCH V3 00/11] Refactor and cleanup
>>>             vsetvl pass
>>>             Hi Lehua,
>>>             This patch causes a build failure with newlib 4.1.0 with
>>>             -march=rv64gv_zbb.
>>>             I've creduced the failure here:
>>>             https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
>>>             Thanks,
>>>             Patrick
>>>             On 10/19/23 20:58, Lehua Ding wrote:
>>>             > Committed, thanks Patrick and Juzhe.
>>>             >
>>>             > On 2023/10/20 2:04, Patrick O'Neill wrote:
>>>             >> I tested it this morning on my machine and it passed!
>>>             >>
>>>             >> Tested against:
>>>             >> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>>             >>
>>>             >> Using targets:
>>>             >> glibc rv32gcv qemu
>>>             >> glibc rv64gcv qemu
>>>             >>
>>>             >> This patch series does not introduce any new failures.
>>>             >>
>>>             >> Here's a list of *resolved* failures by this patch
>>>             series:
>>>             >> rv64gcv:
>>>             >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3
>>>             >> -fomit-frame-pointer -funroll-loops -fpeel-loops
>>>             -ftracer
>>>             >> -finline-functions  execution test
>>>             >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g 
>>>             execution test
>>>             >>
>>>             >> rv32gcv:
>>>             >> FAIL:
>>>             gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c
>>>             execution test
>>>             >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3
>>>             >> -fomit-frame-pointer -funroll-loops -fpeel-loops
>>>             -ftracer
>>>             >> -finline-functions  execution test
>>>             >> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g 
>>>             execution test
>>>             >>
>>>             >> Thanks for the quick revision Lehua!
>>>             >>
>>>             >> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>>>             >>
>>>             >> Patrick
>>>             >>
>>>             >> On 10/19/23 01:50, 钟居哲 wrote:
>>>             >>> LGTM now. But wait for Patrick CI testing.
>>>             >>>
>>>             >>> Hi, @Patrick. Could you apply this patch and trigger
>>>             CI in your
>>>             >>> github  so that we can see the full running result.
>>>             >>>
>>>             >>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub
>>>             >>>
>>>             <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>>             >>>
>>>             >>>
>>>             ------------------------------------------------------------------------
>>>
>>>             >>>
>>>             >>> juzhe.zhong@rivai.ai
>>>             >>>
>>>             >>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>>             >>>     *Date:* 2023-10-19 16:33
>>>             >>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>>             >>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>;
>>>             kito.cheng
>>>             >>> <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>>             >>> <mailto:rdapp.gcc@gmail.com>; palmer
>>>             <mailto:palmer@rivosinc.com>;
>>>             >>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>;
>>>             lehua.ding
>>>             >>> <mailto:lehua.ding@rivai.ai>
>>>             >>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup
>>>             vsetvl pass
>>>             >>>     This patch refactors and cleanups the vsetvl
>>>             pass in order to make
>>>             >>>     the code
>>>             >>>     easier to modify and understand. This patch does
>>>             several things:
>>>             >>>     1. Introducing a virtual CFG for vsetvl infos
>>>             and Phase 1, 2 and 3
>>>             >>>     only maintain
>>>             >>>        and modify this virtual CFG. Phase 4 performs
>>>             insertion,
>>>             >>>     modification and
>>>             >>>        deletion of vsetvl insns based on the virtual
>>>             CFG. The Basic
>>>             >>>     block in the
>>>             >>>        virtual CFG is called vsetvl_block_info and
>>>             the vsetvl
>>>             >>>     information inside
>>>             >>>        is called vsetvl_info.
>>>             >>>     2. Combine Phase 1 and 2 into a single Phase 1
>>>             and unified the
>>>             >>>     demand system,
>>>             >>>        this Phase only fuse local vsetvl info in
>>>             forward direction.
>>>             >>>     3. Refactor Phase 3, change the logic for
>>>             determining whether to
>>>             >>>     uplift vsetvl
>>>             >>>        info to a pred basic block to a more unified
>>>             method that there
>>>             >>>     is a vsetvl
>>>             >>>        info in the vsetvl defintion reaching in
>>>             compatible with it.
>>>             >>>     4. Place all modification operations to the RTL
>>>             in Phase 4 and
>>>             >>>     Phase 5.
>>>             >>>        Phase 4 is responsible for inserting,
>>>             modifying and deleting
>>>             >>> vsetvl
>>>             >>>        instructions based on fully optimized vsetvl
>>>             infos. Phase 5
>>>             >>>     removes the avl
>>>             >>>        operand from the RVV instruction and removes
>>>             the unused dest
>>>             >>>     operand
>>>             >>>        register from the vsetvl insns.
>>>             >>>     These modifications resulted in some testcases
>>>             needing to be
>>>             >>>     updated. The reasons
>>>             >>>     for updating are summarized below:
>>>             >>>     1. more optimized
>>>             >>>
>>>             vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>>             >>> vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>>             >>>
>>>             avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>>             >>>     2. less unnecessary fusion
>>>             >>> avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>>             >>>     3. local fuse direction (backward -> forward)
>>>             >>>        scalar_move-1.c/
>>>             >>>     4. add some bugfix testcases.
>>>             >>> pr111037-3.c/pr111037-4.c
>>>             >>>        avl_single-89.c
>>>             >>>     PR target/111037
>>>             >>>     PR target/111234
>>>             >>>     PR target/111725
>>>             >>>     Lehua Ding (11):
>>>             >>>       RISC-V: P1: Refactor
>>>             >>>
>>>             avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>>             >>>       RISC-V: P2: Refactor and cleanup demand system
>>>             >>>       RISC-V: P3: Refactor vector_infos_manager
>>>             >>>       RISC-V: P4: move method from pass_vsetvl to
>>>             pre_vsetvl
>>>             >>>       RISC-V: P5: combine phase 1 and 2
>>>             >>>       RISC-V: P6: Add computing reaching definition
>>>             data flow
>>>             >>>       RISC-V: P7: Move earliest fuse and lcm code to
>>>             pre_vsetvl class
>>>             >>>       RISC-V: P8: Refactor emit-vsetvl phase and
>>>             delete post
>>>             >>> optimization
>>>             >>>       RISC-V: P9: Cleanup and reorganize helper
>>>             functions
>>>             >>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust
>>>             riscv-vsetvl.def
>>>             >>>       RISC-V: P11: Adjust and add testcases
>>>             >>> gcc/config/riscv/riscv-vsetvl.cc | 6502
>>>             >>> +++++++----------
>>>             >>> gcc/config/riscv/riscv-vsetvl.def |  641 +-
>>>             >>> gcc/config/riscv/riscv-vsetvl.h |  488 --
>>>             >>> gcc/config/riscv/t-riscv |    2 +-
>>>             >>> .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>>             >>> .../riscv/rvv/vsetvl/avl_single-104.c |   35 +
>>>             >>> .../riscv/rvv/vsetvl/avl_single-105.c |   23 +
>>>             >>> .../riscv/rvv/vsetvl/avl_single-106.c |   34 +
>>>             >>> .../riscv/rvv/vsetvl/avl_single-107.c |   41 +
>>>             >>> .../riscv/rvv/vsetvl/avl_single-108.c |   41 +
>>>             >>> .../riscv/rvv/vsetvl/avl_single-109.c |   45 +
>>>             >>> .../riscv/rvv/vsetvl/avl_single-23.c |    7 +-
>>>             >>> .../riscv/rvv/vsetvl/avl_single-46.c |    3 +-
>>>             >>> .../riscv/rvv/vsetvl/avl_single-84.c |    5 +-
>>>             >>> .../riscv/rvv/vsetvl/avl_single-89.c |    8 +-
>>>             >>> .../riscv/rvv/vsetvl/avl_single-95.c |    2 +-
>>>             >>> .../riscv/rvv/vsetvl/imm_bb_prop-1.c |    7 +-
>>>             >>> .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c |    2 +-
>>>             >>> .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c |    2 +-
>>>             >>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>>             >>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>>             >>> .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c |   16 +
>>>             >>> .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c |   16 +
>>>             >>> .../riscv/rvv/vsetvl/vlmax_back_prop-25.c |   10 +-
>>>             >>> .../riscv/rvv/vsetvl/vlmax_back_prop-26.c |   10 +-
>>>             >>> .../riscv/rvv/vsetvl/vlmax_conflict-12.c |    1 -
>>>             >>> .../riscv/rvv/vsetvl/vlmax_conflict-3.c |    2 +-
>>>             >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c |    4 +-
>>>             >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c |    4 +-
>>>             >>> .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c |    2 +-
>>>             >>>     30 files changed, 3263 insertions(+), 4692
>>>             deletions(-)
>>>             >>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>>             >>>     create mode 100644
>>>             >>>
>>>             gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>>             >>>     create mode 100644
>>>             >>>
>>>             gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>>             >>>     create mode 100644
>>>             >>>
>>>             gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>>             >>>     create mode 100644
>>>             >>>
>>>             gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>>             >>>     create mode 100644
>>>             >>>
>>>             gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>>             >>>     create mode 100644
>>>             >>>
>>>             gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>>             >>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>             >>>     vsetvl}/pr111037-1.c (100%)
>>>             >>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>             >>>     vsetvl}/pr111037-2.c (100%)
>>>             >>>     create mode 100644
>>>             >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>>             >>>     create mode 100644
>>>             >>> gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>>             >>>     --     2.36.3
>>>             >>>
>>>             >
>>>
  

Fixed on trunk. Pl;z verify it.




juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 09:01
To: juzhe.zhong@rivai.ai; 丁乐华
CC: kito.cheng; Robin Dapp; palmer; jeffreyalaw; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
IIRC --enable-checking=yes does not turn on RTL checking.
You need to pass in rtl explicitly using --enable-checking=rtl
You can also pass in a list of checks like this: --enable-checking=yes,rtl

Patrick

On 10/23/23 17:51, juzhe.zhong@rivai.ai wrote:
I don't have such issue:

[jzzhong@rios-cad121:/work/home/jzzhong/work/insn]$~/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/bin/riscv64-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/libexec/gcc/riscv64-unknown-elf/14.0.0/lto-wrapper
Target: riscv64-unknown-elf
Configured with: /work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/../../gcc/configure --target=riscv64-unknown-elf --prefix=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install --disable-shared --disable-threads --enable-languages=c,c++ --with-pkgversion=g70b66ac9bcb-dirty --with-system-zlib --enable-tls --with-newlib --with-sysroot=/work/home/jzzhong/work/toolchain/riscv/build/dev-rv64gcv_zfh_zvfh-lp64d-medany-newlib-spike-debug/install/riscv64-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=../../../gcc --enable-checking=yes --disable-multilib --with-abi=lp64d --with-arch=rv64gcv_zfh_zvfh --with-tune=rocket --with-isa-spec=20191213 CFLAGS='-O0 -g3' CXXFLAGS='-O0 -g3' 'CFLAGS_FOR_TARGET=-Os    -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-Os    -mcmodel=medany'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231023 (experimental) (g70b66ac9bcb-dirty)




juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 07:42
To: 钟居哲; 丁乐华
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
When configuring, pass in --enable-checking=rtl
If you're using riscv-gnu-toolchain, pass in --enable-gcc-checking=rtl

The -freport-bug output attached to the bug report has the full configure command used:
/scratch/tc-testing/tc-trunk/build-rtl-checking/../gcc/configure --target=riscv64-unknown-linux-gnu --prefix=/scratch/tc-testing/tc-trunk/build-rtl-checking --with-sysroot=/scratch/tc-testing/tc-trunk/build-rtl-checking/sysroot --with-newlib --without-headers --disable-shared --disable-threads --with-system-zlib --enable-tls --enable-languages=c --disable-libatomic --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-bootstrap --src=../../gcc --enable-checking=rtl --disable-multilib --with-abi=lp64d --with-arch=rv64gcv --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2    -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-O2    -mcmodel=medlow'

On 10/23/23 15:50, 钟居哲 wrote:
I didn't reproduce it. How to enable RTL checking ?



juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 06:46
To: 钟居哲; 丁乐华
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
You're on top of it - thanks for fixing this! I'll send the testcase.

Unrelated to this failure, I'm seeing a build failure on glibc rv32/64gcv when RTL checking is enabled.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111947

Thanks,
Patrick
On 10/23/23 14:41, 钟居哲 wrote:
I have fixed it: 
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0c4bd1321a6def5eb44c530e83b01a415633b660

Plz verify it and send a patch with testcase pr111941.c if you confirm it has been fixed on the trunk.

Thanks.


juzhe.zhong@rivai.ai
 
From: Patrick O'Neill
Date: 2023-10-24 02:30
To: Lehua Ding
CC: kito.cheng; rdapp.gcc; palmer; Jeff Law; gcc-patches; 钟居哲
Subject: Re: [PATCH V3 00/11] Refactor and cleanup vsetvl pass
Hi Lehua,
 
This patch causes a build failure with newlib 4.1.0 with -march=rv64gv_zbb.
 
I've creduced the failure here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111941
 
Thanks,
Patrick
 
On 10/19/23 20:58, Lehua Ding wrote:
> Committed, thanks Patrick and Juzhe.
>
> On 2023/10/20 2:04, Patrick O'Neill wrote:
>> I tested it this morning on my machine and it passed!
>>
>> Tested against:
>> 04d6c74564b7eb51660a00b35353aeab706b5a50
>>
>> Using targets:
>> glibc rv32gcv qemu
>> glibc rv64gcv qemu
>>
>> This patch series does not introduce any new failures.
>>
>> Here's a list of *resolved* failures by this patch series:
>> rv64gcv:
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> rv32gcv:
>> FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 
>> -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer 
>> -finline-functions  execution test
>> FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test
>>
>> Thanks for the quick revision Lehua!
>>
>> Tested-by: Patrick O'Neill <patrick@rivosinc.com>
>>
>> Patrick
>>
>> On 10/19/23 01:50, 钟居哲 wrote:
>>> LGTM now. But wait for Patrick CI testing.
>>>
>>> Hi, @Patrick. Could you apply this patch and trigger CI in your 
>>> github  so that we can see the full running result.
>>>
>>> Issues · patrick-rivos/riscv-gnu-toolchain · GitHub 
>>> <https://github.com/patrick-rivos/riscv-gnu-toolchain/issues>
>>>
>>> ------------------------------------------------------------------------ 
>>>
>>> juzhe.zhong@rivai.ai
>>>
>>>     *From:* Lehua Ding <mailto:lehua.ding@rivai.ai>
>>>     *Date:* 2023-10-19 16:33
>>>     *To:* gcc-patches <mailto:gcc-patches@gcc.gnu.org>
>>>     *CC:* juzhe.zhong <mailto:juzhe.zhong@rivai.ai>; kito.cheng
>>>     <mailto:kito.cheng@gmail.com>; rdapp.gcc
>>>     <mailto:rdapp.gcc@gmail.com>; palmer <mailto:palmer@rivosinc.com>;
>>>     jeffreyalaw <mailto:jeffreyalaw@gmail.com>; lehua.ding
>>>     <mailto:lehua.ding@rivai.ai>
>>>     *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass
>>>     This patch refactors and cleanups the vsetvl pass in order to make
>>>     the code
>>>     easier to modify and understand. This patch does several things:
>>>     1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3
>>>     only maintain
>>>        and modify this virtual CFG. Phase 4 performs insertion,
>>>     modification and
>>>        deletion of vsetvl insns based on the virtual CFG. The Basic
>>>     block in the
>>>        virtual CFG is called vsetvl_block_info and the vsetvl
>>>     information inside
>>>        is called vsetvl_info.
>>>     2. Combine Phase 1 and 2 into a single Phase 1 and unified the
>>>     demand system,
>>>        this Phase only fuse local vsetvl info in forward direction.
>>>     3. Refactor Phase 3, change the logic for determining whether to
>>>     uplift vsetvl
>>>        info to a pred basic block to a more unified method that there
>>>     is a vsetvl
>>>        info in the vsetvl defintion reaching in compatible with it.
>>>     4. Place all modification operations to the RTL in Phase 4 and
>>>     Phase 5.
>>>        Phase 4 is responsible for inserting, modifying and deleting 
>>> vsetvl
>>>        instructions based on fully optimized vsetvl infos. Phase 5
>>>     removes the avl
>>>        operand from the RVV instruction and removes the unused dest
>>>     operand
>>>        register from the vsetvl insns.
>>>     These modifications resulted in some testcases needing to be
>>>     updated. The reasons
>>>     for updating are summarized below:
>>>     1. more optimized
>>> vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/
>>>        vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/
>>> avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c
>>>     2. less unnecessary fusion
>>>     avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c
>>>     3. local fuse direction (backward -> forward)
>>>        scalar_move-1.c/
>>>     4. add some bugfix testcases.
>>>        pr111037-3.c/pr111037-4.c
>>>        avl_single-89.c
>>>     PR target/111037
>>>     PR target/111234
>>>     PR target/111725
>>>     Lehua Ding (11):
>>>       RISC-V: P1: Refactor
>>>     avl_info/vl_vtype_info/vector_insn_info/vector_block_info
>>>       RISC-V: P2: Refactor and cleanup demand system
>>>       RISC-V: P3: Refactor vector_infos_manager
>>>       RISC-V: P4: move method from pass_vsetvl to pre_vsetvl
>>>       RISC-V: P5: combine phase 1 and 2
>>>       RISC-V: P6: Add computing reaching definition data flow
>>>       RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class
>>>       RISC-V: P8: Refactor emit-vsetvl phase and delete post 
>>> optimization
>>>       RISC-V: P9: Cleanup and reorganize helper functions
>>>       RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def
>>>       RISC-V: P11: Adjust and add testcases
>>>     gcc/config/riscv/riscv-vsetvl.cc              | 6502 
>>> +++++++----------
>>>     gcc/config/riscv/riscv-vsetvl.def             |  641 +-
>>>     gcc/config/riscv/riscv-vsetvl.h               |  488 --
>>>     gcc/config/riscv/t-riscv                      |    2 +-
>>>     .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +-
>>>     .../riscv/rvv/vsetvl/avl_single-104.c         |   35 +
>>>     .../riscv/rvv/vsetvl/avl_single-105.c         |   23 +
>>>     .../riscv/rvv/vsetvl/avl_single-106.c         |   34 +
>>>     .../riscv/rvv/vsetvl/avl_single-107.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-108.c         |   41 +
>>>     .../riscv/rvv/vsetvl/avl_single-109.c         |   45 +
>>>     .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +-
>>>     .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +-
>>>     .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +-
>>>     .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +-
>>>     .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +-
>>>     .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +-
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0
>>>     .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 +
>>>     .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 +
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +-
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 -
>>>     .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +-
>>>     .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +-
>>>     30 files changed, 3263 insertions(+), 4692 deletions(-)
>>>     delete mode 100644 gcc/config/riscv/riscv-vsetvl.h
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-1.c (100%)
>>>     rename gcc/testsuite/gcc.target/riscv/rvv/{base =>
>>>     vsetvl}/pr111037-2.c (100%)
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
>>>     create mode 100644
>>>     gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c
>>>     --     2.36.3
>>>
>