Message ID | 20221113212030.4078815-1-philipp.tomsich@vrull.eu |
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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:31 -0800 (PST) From: Philipp Tomsich <philipp.tomsich@vrull.eu> To: gcc-patches@gcc.gnu.org Cc: Jeff Law <jlaw@ventanamicro.com>, Vineet Gupta <vineetg@rivosinc.com>, Kito Cheng <kito.cheng@gmail.com>, Christoph Muellner <christoph.muellner@vrull.eu>, Palmer Dabbelt <palmer@rivosinc.com>, Philipp Tomsich <philipp.tomsich@vrull.eu> Subject: [PATCH v2 0/8] RISC-V: Backend support for XVentanaCondOps/ZiCondops Date: Sun, 13 Nov 2022 22:20:21 +0100 Message-Id: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749417533653154417?= X-GMAIL-MSGID: =?utf-8?q?1749417533653154417?= |
Series |
RISC-V: Backend support for XVentanaCondOps/ZiCondops
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Message
Philipp Tomsich
Nov. 13, 2022, 9:20 p.m. UTC
Both the XVentanaCondOps (a vendor-defined extension from Ventana Microsystems) and the proposed ZiCondOps extensions define a conditional-zero(-or-value) instruction, which is similar to the following C construct: rd = rc ? rs : 0 This functionality can be tied back into if-convertsion and also match some typical programming idioms. This series includes backend support for XVentanaCondops and infrastructure to handle conditional-zero constructions in if-conversion. Tested against SPEC CPU 2017. Changes in v2: - Restore a (during rebase) dropped line to xventanacondops.md - Include the change to add xventanacondops to the VT1 code definition] as a separate patch. Philipp Tomsich (8): RISC-V: Recognize xventanacondops extension RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Recognize bexti in negated if-conversion RISC-V: Support immediates in XVentanaCondOps RISC-V: Ventana-VT1 supports XVentanaCondOps ifcvt: add if-conversion to conditional-zero instructions gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/predicates.md | 12 + gcc/config/riscv/riscv-cores.def | 2 +- gcc/config/riscv/riscv-opts.h | 3 + gcc/config/riscv/riscv.cc | 14 ++ gcc/config/riscv/riscv.md | 27 +++ gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/xventanacondops.md | 151 ++++++++++++ gcc/ifcvt.cc | 214 ++++++++++++++++++ .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ .../riscv/xventanacondops-ifconv-imm.c | 19 ++ .../gcc.target/riscv/xventanacondops-le-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-lt-03.c | 16 ++ .../gcc.target/riscv/xventanacondops-ne-01.c | 10 + .../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++ .../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++ .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ 21 files changed, 600 insertions(+), 1 deletion(-) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c