diff mbox series

RISC-V: Zihintpause: add __builtin_riscv_pause

Message ID 20221113204139.4061479-1-philipp.tomsich@vrull.eu
State Accepted
Headers
Series RISC-V: Zihintpause: add __builtin_riscv_pause |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Philipp Tomsich Nov. 13, 2022, 8:41 p.m. UTC 
  The Zihintpause extension uses an opcode from the 'fence' opcode range
to add a true hint instruction (i.e. if it is not supported on any
given platform, the 'fence' that is encoded will not enforce any
specific ordering on memory accesses) for entering a low-power state
(e.g. in an idle thread).  We expose this new instruction through a
machine-dependent builtin to allow generating it without a requirement
for any inline assembly.

Given that the encoding of 'pause' is valid (as a 'fence' encoding)
even for processors that do not (yet) support Zihintpause, we make
this builtin available without any further TARGET_* constraints.

gcc/ChangeLog:

	* config/riscv/riscv-builtins.cc (struct riscv_builtin_description):
	add the pause machine-dependent builtin with no result and no
        arguments; mark it as always present (pause is a true hint
        that encodes into a fence-insn, if not supported with the new
        pause semantics).
	* config/riscv/riscv-ftypes.def: Add type for void -> void.
	* config/riscv/riscv.md (riscv_pause): Add risc_pause and UNSPECV_PAUSE
	* doc/gcc/extensions-to-the-c-language-family/target-builtins/risc-v-built-in-functions.rst:
	Document.
	* optabs.cc (maybe_gen_insn): Allow nops == 0 (void -> void).

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/builtin_pause.c: New test.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---

 gcc/config/riscv/riscv-builtins.cc                     |  6 +++---
 gcc/config/riscv/riscv-ftypes.def                      |  1 +
 gcc/config/riscv/riscv.md                              |  8 ++++++++
 .../target-builtins/risc-v-built-in-functions.rst      |  4 ++++
 gcc/optabs.cc                                          |  2 ++
 gcc/testsuite/gcc.target/riscv/builtin_pause.c         | 10 ++++++++++
 6 files changed, 28 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c

Comments

Jeff Law Nov. 15, 2022, 4:40 p.m. UTC | #1 
On 11/13/22 13:41, Philipp Tomsich wrote:
> The Zihintpause extension uses an opcode from the 'fence' opcode range
> to add a true hint instruction (i.e. if it is not supported on any
> given platform, the 'fence' that is encoded will not enforce any
> specific ordering on memory accesses) for entering a low-power state
> (e.g. in an idle thread).  We expose this new instruction through a
> machine-dependent builtin to allow generating it without a requirement
> for any inline assembly.
>
> Given that the encoding of 'pause' is valid (as a 'fence' encoding)
> even for processors that do not (yet) support Zihintpause, we make
> this builtin available without any further TARGET_* constraints.
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-builtins.cc (struct riscv_builtin_description):
> 	add the pause machine-dependent builtin with no result and no
>          arguments; mark it as always present (pause is a true hint
>          that encodes into a fence-insn, if not supported with the new
>          pause semantics).
> 	* config/riscv/riscv-ftypes.def: Add type for void -> void.
> 	* config/riscv/riscv.md (riscv_pause): Add risc_pause and UNSPECV_PAUSE
> 	* doc/gcc/extensions-to-the-c-language-family/target-builtins/risc-v-built-in-functions.rst:
> 	Document.
> 	* optabs.cc (maybe_gen_insn): Allow nops == 0 (void -> void).
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/builtin_pause.c: New test.

OK.  Though I think you'll need to adjust the doc patch now with the 
sphinx work reverted.


Jeff
Philipp Tomsich Nov. 15, 2022, 10:12 p.m. UTC | #2 
On Tue, 15 Nov 2022 at 17:40, Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 11/13/22 13:41, Philipp Tomsich wrote:
> > The Zihintpause extension uses an opcode from the 'fence' opcode range
> > to add a true hint instruction (i.e. if it is not supported on any
> > given platform, the 'fence' that is encoded will not enforce any
> > specific ordering on memory accesses) for entering a low-power state
> > (e.g. in an idle thread).  We expose this new instruction through a
> > machine-dependent builtin to allow generating it without a requirement
> > for any inline assembly.
> >
> > Given that the encoding of 'pause' is valid (as a 'fence' encoding)
> > even for processors that do not (yet) support Zihintpause, we make
> > this builtin available without any further TARGET_* constraints.
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-builtins.cc (struct riscv_builtin_description):
> >       add the pause machine-dependent builtin with no result and no
> >          arguments; mark it as always present (pause is a true hint
> >          that encodes into a fence-insn, if not supported with the new
> >          pause semantics).
> >       * config/riscv/riscv-ftypes.def: Add type for void -> void.
> >       * config/riscv/riscv.md (riscv_pause): Add risc_pause and UNSPECV_PAUSE
> >       * doc/gcc/extensions-to-the-c-language-family/target-builtins/risc-v-built-in-functions.rst:
> >       Document.
> >       * optabs.cc (maybe_gen_insn): Allow nops == 0 (void -> void).
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/builtin_pause.c: New test.
>
> OK.  Though I think you'll need to adjust the doc patch now with the
> sphinx work reverted.

Applied to master with the earlier changes to texinfo restored. Thanks!
--Philipp.
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 021f6c6b69a..24ae22c99cd 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -88,8 +88,6 @@  struct riscv_builtin_description {
 };
 
 AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
-
-
 AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
 AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT)
 AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT)
@@ -100,6 +98,7 @@  AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -148,7 +147,8 @@  static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
-  DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
+  DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
+  DIRECT_NO_TARGET_BUILTIN (pause, RISCV_VOID_FTYPE, always),
 };
 
 /* Index I is the function declaration for riscv_builtins[I], or null if the
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index c2b45c63ea1..bf2d30782d9 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -27,6 +27,7 @@  along with GCC; see the file COPYING3.  If not see
         argument type.  */
 
 DEF_RISCV_FTYPE (0, (USI))
+DEF_RISCV_FTYPE (0, (VOID))
 DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d1f3270a3c8..a933764e897 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -94,6 +94,9 @@ 
   UNSPECV_INVAL
   UNSPECV_ZERO
   UNSPECV_PREI
+
+  ;; Zihintpause unspec
+  UNSPECV_PAUSE
 ])
 
 (define_constants
@@ -1982,6 +1985,11 @@ 
   "TARGET_ZIFENCEI"
   "fence.i")
 
+(define_insn "riscv_pause"
+  [(unspec_volatile [(const_int 0)] UNSPECV_PAUSE)]
+  ""
+  "pause")
+
 ;;
 ;;  ....................
 ;;
diff --git a/gcc/doc/gcc/extensions-to-the-c-language-family/target-builtins/risc-v-built-in-functions.rst b/gcc/doc/gcc/extensions-to-the-c-language-family/target-builtins/risc-v-built-in-functions.rst
index fca4852ad74..b2f59b310fb 100644
--- a/gcc/doc/gcc/extensions-to-the-c-language-family/target-builtins/risc-v-built-in-functions.rst
+++ b/gcc/doc/gcc/extensions-to-the-c-language-family/target-builtins/risc-v-built-in-functions.rst
@@ -14,3 +14,7 @@  processors.
 .. function:: void * __builtin_thread_pointer (void)
 
   Returns the value that is currently set in the :samp:`tp` register.
+
+.. function:: void __builtin_riscv_pause (void)
+
+  Generates the :samp:`pause` (hint) machine instruction
diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index 9fc9b1fc6e9..09d3b08cb00 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -7961,6 +7961,8 @@  maybe_gen_insn (enum insn_code icode, unsigned int nops,
 
   switch (nops)
     {
+    case 0:
+      return GEN_FCN (icode) ();
     case 1:
       return GEN_FCN (icode) (ops[0].value);
     case 2:
diff --git a/gcc/testsuite/gcc.target/riscv/builtin_pause.c b/gcc/testsuite/gcc.target/riscv/builtin_pause.c
new file mode 100644
index 00000000000..9250937cabb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/builtin_pause.c
@@ -0,0 +1,10 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" }  */
+
+void test_pause()
+{
+  __builtin_riscv_pause ();
+}
+
+/* { dg-final { scan-assembler "pause" } } */
+