Message ID | 20231009232326.91336-1-juzhe.zhong@rivai.ai |
---|---|
State | Unresolved |
Headers |
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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d2-20020a1709064c4200b009ae5a0dfc42si4743410ejw.626.2023.10.09.16.24.06 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 16:24:07 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E04053858D35 for <ouuuleilei@gmail.com>; Mon, 9 Oct 2023 23:24:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id 3BA613858D28 for <gcc-patches@gcc.gnu.org>; Mon, 9 Oct 2023 23:23:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3BA613858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp86t1696893808tgp56m6f Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 10 Oct 2023 07:23:27 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: W+onFc5Tw4NnCf6R/JUK4RxSqImeV+dQ4kLffDC2ioQSMUzwsBTUrzExZTTl8 BUYso5vqvXmkhEoMvEG5oeajoSGomidIDtjR33DWV86RU2ILOEJi+B59eSY4skzUAIempcp OUI/5HGkji0VvclAlEBdMduDzF6Q7X5Sigj+h6uMO33C4+qB+LRuILtZrRgGPD61U/wB3Zo uPtcwfHtteMq5lP1JvvKwmfDAQxx0CmrW+go9MwqP2LA58VS/PkNH2ydroJn5MtRbEs+x7a X9Pie7bdrhSGH19d6rHbMyaClfVbfJzj/6AFMV5y43N4mJ6cClyCF9nz9LfbUcJjdeoJh04 qR3xYwTOhGfFGQrb95ZBksE19HcCwFp+h1cQaCzCgjgE3bcZec= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13529166640978228976 From: Juzhe-Zhong <juzhe.zhong@rivai.ai> To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong <juzhe.zhong@rivai.ai> Subject: [PATCH] RISC-V: Add available vector size for RVV Date: Tue, 10 Oct 2023 07:23:26 +0800 Message-Id: <20231009232326.91336-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779322162707942422 X-GMAIL-MSGID: 1779322162707942422 |
Series |
RISC-V: Add available vector size for RVV
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Checks
Context | Check | Description |
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snail/gcc-patch-check | warning | Git am fail log |
Commit Message
juzhe.zhong@rivai.ai
Oct. 9, 2023, 11:23 p.m. UTC
For RVV, we have VLS modes enable according to TARGET_MIN_VLEN from M1 to M8. For example, when TARGET_MIN_VLEN = 128 bits, we enable 128/256/512/1024 bits VLS modes. This patch fixes following FAIL: FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "optimized: basic block" 2 FAIL: gcc.dg/vect/bb-slp-subgroups-2.c scan-tree-dump-times slp2 "optimized: basic block" 2 gcc/testsuite/ChangeLog: * lib/target-supports.exp: Add 256/512/1024 --- gcc/testsuite/lib/target-supports.exp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Comments
LGTM On Mon, Oct 9, 2023 at 4:23 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote: > > For RVV, we have VLS modes enable according to TARGET_MIN_VLEN > from M1 to M8. > > For example, when TARGET_MIN_VLEN = 128 bits, we enable > 128/256/512/1024 bits VLS modes. > > This patch fixes following FAIL: > FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "optimized: basic block" 2 > FAIL: gcc.dg/vect/bb-slp-subgroups-2.c scan-tree-dump-times slp2 "optimized: basic block" 2 > > gcc/testsuite/ChangeLog: > > * lib/target-supports.exp: Add 256/512/1024 > > --- > gcc/testsuite/lib/target-supports.exp | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > index af52c38433d..dc366d35a0a 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -8881,7 +8881,7 @@ proc available_vector_sizes { } { > lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2 > } elseif { [istarget riscv*-*-*] } { > if { [check_effective_target_riscv_v] } { > - lappend result 0 32 64 128 > + lappend result 0 32 64 128 256 512 1024 > } > lappend result 128 > } else { > -- > 2.36.3 >
Committed, thanks Kito. Pan -----Original Message----- From: Kito Cheng <kito.cheng@sifive.com> Sent: Tuesday, October 10, 2023 11:20 AM To: Juzhe-Zhong <juzhe.zhong@rivai.ai> Cc: gcc-patches@gcc.gnu.org; kito.cheng@gmail.com; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com Subject: Re: [PATCH] RISC-V: Add available vector size for RVV LGTM On Mon, Oct 9, 2023 at 4:23 PM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote: > > For RVV, we have VLS modes enable according to TARGET_MIN_VLEN > from M1 to M8. > > For example, when TARGET_MIN_VLEN = 128 bits, we enable > 128/256/512/1024 bits VLS modes. > > This patch fixes following FAIL: > FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects scan-tree-dump-times slp2 "optimized: basic block" 2 > FAIL: gcc.dg/vect/bb-slp-subgroups-2.c scan-tree-dump-times slp2 "optimized: basic block" 2 > > gcc/testsuite/ChangeLog: > > * lib/target-supports.exp: Add 256/512/1024 > > --- > gcc/testsuite/lib/target-supports.exp | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > index af52c38433d..dc366d35a0a 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -8881,7 +8881,7 @@ proc available_vector_sizes { } { > lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2 > } elseif { [istarget riscv*-*-*] } { > if { [check_effective_target_riscv_v] } { > - lappend result 0 32 64 128 > + lappend result 0 32 64 128 256 512 1024 > } > lappend result 128 > } else { > -- > 2.36.3 >
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index af52c38433d..dc366d35a0a 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -8881,7 +8881,7 @@ proc available_vector_sizes { } { lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2 } elseif { [istarget riscv*-*-*] } { if { [check_effective_target_riscv_v] } { - lappend result 0 32 64 128 + lappend result 0 32 64 128 256 512 1024 } lappend result 128 } else {