diff mbox series

[4/5] RISC-V: Update Types for RISC-V Instructions

Message ID 20230906175025.935887-5-ewlu@rivosinc.com
State Unresolved
Headers
Series RISC-V: Add Types to Untyped Instructions |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

Edwin Lu Sept. 6, 2023, 5:50 p.m. UTC 
  This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html

gcc/ChangeLog:

	* config/riscv/riscv.md: Update types

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
 gcc/config/riscv/riscv.md | 3 +++
 1 file changed, 3 insertions(+)

Comments

Kito Cheng Sept. 6, 2023, 11:23 p.m. UTC | #1 
LGTM

Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:52 寫道：

> This patch adds types to riscv instructions that were added or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.md: Update types
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> ---
>  gcc/config/riscv/riscv.md | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index c329f55db43..c1cecd27815 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
>    "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>    "fmv.x.w\t%0,%1"
>    [(set_attr "move_type" "fmove")
> +   (set_attr "type" "fmove")
>     (set_attr "mode" "DF")])
>
>
> @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
>    "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>    "fmvh.x.d\t%0,%1"
>    [(set_attr "move_type" "fmove")
> +   (set_attr "type" "fmove")
>     (set_attr "mode" "DF")])
>
>  (define_insn "movdfsisi3_rv32"
> @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
>    "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>    "fmvp.d.x\t%0,%2,%1"
>    [(set_attr "move_type" "fmove")
> +   (set_attr "type" "fmove")
>     (set_attr "mode" "DF")])
>
>  (define_split
> --
> 2.34.1
>
>
Edwin Lu Sept. 11, 2023, 5:48 p.m. UTC | #2 
On 9/6/2023 4:23 PM, Kito Cheng via Gcc-patches wrote:
> LGTM
> 
> Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:52 寫道：
> 
>> This patch adds types to riscv instructions that were added or were
>> missed by the original patch
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>>
>> gcc/ChangeLog:
>>
>>          * config/riscv/riscv.md: Update types
>>
>> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
>> ---
>>   gcc/config/riscv/riscv.md | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index c329f55db43..c1cecd27815 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
>>     "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>>     "fmv.x.w\t%0,%1"
>>     [(set_attr "move_type" "fmove")
>> +   (set_attr "type" "fmove")
>>      (set_attr "mode" "DF")])
>>
>>
>> @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
>>     "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>>     "fmvh.x.d\t%0,%1"
>>     [(set_attr "move_type" "fmove")
>> +   (set_attr "type" "fmove")
>>      (set_attr "mode" "DF")])
>>
>>   (define_insn "movdfsisi3_rv32"
>> @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
>>     "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>>     "fmvp.d.x\t%0,%2,%1"
>>     [(set_attr "move_type" "fmove")
>> +   (set_attr "type" "fmove")
>>      (set_attr "mode" "DF")])
>>
>>   (define_split
>> --
>> 2.34.1
>>
>>
> 
Committed!

Edwin
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c329f55db43..c1cecd27815 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2223,6 +2223,7 @@  (define_insn "movsidf2_low_rv32"
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmv.x.w\t%0,%1"
   [(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
    (set_attr "mode" "DF")])
 
 
@@ -2235,6 +2236,7 @@  (define_insn "movsidf2_high_rv32"
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmvh.x.d\t%0,%1"
   [(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
    (set_attr "mode" "DF")])
 
 (define_insn "movdfsisi3_rv32"
@@ -2247,6 +2249,7 @@  (define_insn "movdfsisi3_rv32"
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmvp.d.x\t%0,%2,%1"
   [(set_attr "move_type" "fmove")
+   (set_attr "type" "fmove")
    (set_attr "mode" "DF")])
 
 (define_split