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(183.77.162.93 with ) by smtp5006.mail.kks.ynwp.yahoo.co.jp with SMTP; 10 Sep 2022 09:44:41 -0000 X-YMail-JAS: tLgBwY4VM1mEHZiaEjtR2g3wuxeQKIL0CsB8ze0r2eIXqWmPqm4vFYpWtOBIJ1Xlk9lWIpTiODbJlLghkr.2rY4SOogOU21zr.E.3_FVVTzWYSfZ5cepPBoNrI4MUljMRi52wt1YHw-- X-Apparently-From: X-YMail-OSG: WOIsP2AVM1nJto7umL0DlyBtdo8FFCUaLhRMCGm69CP6PMO 8RS_hubL0vzanmEy19NP4Hc4T5.mUP1wtjdCnee6O5vNZwmynaQkpoBcwxXJ 34nA06MyIWkxvbod97xdqiTMryRpft1eeXD9th8k6AQv_TIAexBmL.z6qBYn 4_L3COEamdRWMbRgbLPM6nu9.LV3r_vvCGQnlY0FUHRatHmSFBcCTlWVUlWn oRbXmWHWJqr1OyqoBi29A1EBMCCo1dGjO4H1NKmywr0bVwOctYDyq7qq.9.s 7PjVKxlS9XZ2sSToLrmDODb3WR1NzJ0qT2hGL3M2YgvRka7S2KNDR_2IQqLo 7n1jfN7eqmjuMdiViijsdqsnQ9qk.1RMSgLSxRMkY6KwjpUM_R1f3LmvHeRk DY5V59LgDgveYJzYCqH7nslHY8JtpEKMip6js4oxb_16RZKj_djNpWcIcFje bAkHStvOkAwUWFX7_KH_9HQuLR.eV5lTzzIagycDj9_F7.QECHep8K0EGMW7 PjrrGMcaKqPo1pP26QrvrBJeYv9a0bqNN96.c9fAXSwLZ1Zbp.bSRDxmIgso BykOQVnH6kmbQI6ONe5GDGL8WkYL_t1rctQy5g14NubC_6GxfzChyal3w_Jf NyY0MD3Vc5qxhED6dafoHWufdlTd0ogpFBMQXOCCjOj8x763IJTvoaTuMrPt nnwpLfrZ0iBuFDz5bVH8YibNInUH8s3dywsrHfpI7rR9kcWxUPBWqDyexFSc .3INFg0eO9K111RJoXTjCbYjB7SPmB0B6ojt7439gmkoplv66ocsxqpAJbln z9CQdvjgDEDMKYoxVhb7gKUMn5.tBuBqqvgLsCYUYXeQrCo.QAZXZqQRY14m qcIICGOtEnCQZ6FJtVfBh4QLQ51GLT1OAoxHTmCjel_4JftDAsOCkRR.pAHE 0qJA6frFcP8tE8vsM Message-ID: Date: Sat, 10 Sep 2022 18:29:45 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 To: GCC Patches Subject: [PATCH] xtensa: constantsynth: Add new 3-insns synthesis pattern X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Takayuki 'January June' Suwa via Gcc-patches From: Takayuki 'January June' Suwa Reply-To: Takayuki 'January June' Suwa Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1743575456446743903?= X-GMAIL-MSGID: =?utf-8?q?1743575456446743903?= This patch adds a new 3-instructions constant synthesis pattern: - A value that can fit into a signed 12-bit after a number of either bitwise left or right rotations: => "MOVI(.N) Ax, simm12" + "SSAI (1 ... 11) or (21 ... 31)" + "SRC Ax, Ax, Ax" gcc/ChangeLog: * config/xtensa/xtensa.cc (xtensa_constantsynth): Add new pattern for the abovementioned case. gcc/testsuite/ChangeLog: * gcc.target/xtensa/constsynth_3insns.c (test_4): Add new test function. --- gcc/config/xtensa/xtensa.cc | 31 +++++++++++++++++++ .../gcc.target/xtensa/constsynth_3insns.c | 11 +++++++ 2 files changed, 42 insertions(+) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index 0f586b09dfb..ac52c015a94 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -1142,6 +1142,37 @@ xtensa_constantsynth (rtx dst, HOST_WIDE_INT srcval) xtensa_constantsynth_rtx_ADDSUBX, divisor)) return 1; + + /* loading simm12 followed by left/right bitwise rotation: + MOVI + SSAI + SRC. */ + if ((srcval & 0x001FF800) == 0 + || (srcval & 0x001FF800) == 0x001FF800) + { + int32_t v; + + for (shift = 1; shift < 12; ++shift) + { + v = (int32_t)(((uint32_t)srcval >> shift) + | ((uint32_t)srcval << (32 - shift))); + if (xtensa_simm12b(v)) + { + emit_move_insn (dst, GEN_INT (v)); + emit_insn (gen_rotlsi3 (dst, dst, GEN_INT (shift))); + return 1; + } + } + for (shift = 1; shift < 12; ++shift) + { + v = (int32_t)(((uint32_t)srcval << shift) + | ((uint32_t)srcval >> (32 - shift))); + if (xtensa_simm12b(v)) + { + emit_move_insn (dst, GEN_INT (v)); + emit_insn (gen_rotrsi3 (dst, dst, GEN_INT (shift))); + return 1; + } + } + } } return 0; diff --git a/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c b/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c index f3c4a1c7c15..831288c7ddd 100644 --- a/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c +++ b/gcc/testsuite/gcc.target/xtensa/constsynth_3insns.c @@ -21,4 +21,15 @@ void test_3(int *p) *p = 192437; } +struct foo +{ + unsigned int b : 10; + unsigned int g : 11; + unsigned int r : 11; +}; +void test_4(struct foo *p, unsigned int v) +{ + p->g = v; +} + /* { dg-final { scan-assembler-not "l32r" } } */