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[75.76.18.234]) by smtp.gmail.com with ESMTPSA id cf11-20020a05622a400b00b0039ee562799csm10222928qtb.59.2022.11.23.13.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:13:45 -0800 (PST) From: Nathan Barrett-Morrison Cc: nathan.morrison@timesys.com, greg.malysa@timesys.com, Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org (open list:SPI NOR SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/2] mtd: spi-nore: core: Add in framework for 8S-8S-8S Octal STR mode Date: Wed, 23 Nov 2022 16:13:34 -0500 Message-Id: <20221123211335.126417-2-nathan.morrison@timesys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221123211335.126417-1-nathan.morrison@timesys.com> References: <20221123211335.126417-1-nathan.morrison@timesys.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750323241088799871?= X-GMAIL-MSGID: =?utf-8?q?1750323241088799871?= While trying to bring up an Octal SPI device in STR mode, I found that there is currently no support for 8S-8S-8S. This patch adds the necessary, additional logic for doing so. Signed-off-by: Nathan Barrett-Morrison --- drivers/mtd/spi-nor/core.c | 57 ++++++++++++++++++++++++++++++++++++-- drivers/mtd/spi-nor/core.h | 5 +++- 2 files changed, 59 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index bee8fc4c9f07..66665c1bebd7 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2253,7 +2253,8 @@ static int spi_nor_set_addr_nbytes(struct spi_nor *nor) { if (nor->params->addr_nbytes) { nor->addr_nbytes = nor->params->addr_nbytes; - } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) { + } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR || + nor->read_proto == SNOR_PROTO_8_8_8) { /* * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So * in this protocol an odd addr_nbytes cannot be used because @@ -2335,7 +2336,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; struct spi_nor_erase_map *map = ¶ms->erase_map; - const u8 no_sfdp_flags = nor->info->no_sfdp_flags; + const u16 no_sfdp_flags = nor->info->no_sfdp_flags; u8 i, erase_mask; if (no_sfdp_flags & SPI_NOR_DUAL_READ) { @@ -2359,6 +2360,13 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) SNOR_PROTO_1_1_8); } + if (no_sfdp_flags & SPI_NOR_OCTAL_STR_READ) { + params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8; + spi_nor_set_read_settings(¶ms->reads[SNOR_HWCAPS_READ_8_8_8], + 0, 20, SPINOR_OP_READ_FAST, + SNOR_PROTO_8_8_8); + } + if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) { params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR], @@ -2366,6 +2374,12 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) SNOR_PROTO_8_8_8_DTR); } + if (no_sfdp_flags & SPI_NOR_OCTAL_STR_PP) { + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8; + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8], + SPINOR_OP_PP, SNOR_PROTO_8_8_8); + } + if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) { params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; /* @@ -2631,6 +2645,38 @@ static int spi_nor_init_params(struct spi_nor *nor) return 0; } +/** spi_nor_octal_str_enable() - enable Octal STR I/O if needed + * @nor: pointer to a 'struct spi_nor' + * @enable: whether to enable or disable Octal STR + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_octal_str_enable(struct spi_nor *nor, bool enable) +{ + int ret; + + if (!nor->params->octal_str_enable) + return 0; + + if (!(nor->read_proto == SNOR_PROTO_8_8_8 && + nor->write_proto == SNOR_PROTO_8_8_8)) + return 0; + + if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE)) + return 0; + + ret = nor->params->octal_str_enable(nor, enable); + if (ret) + return ret; + + if (enable) + nor->reg_proto = SNOR_PROTO_8_8_8; + else + nor->reg_proto = SNOR_PROTO_1_1_1; + + return 0; +} + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @enable: whether to enable or disable Octal DTR @@ -2691,6 +2737,12 @@ static int spi_nor_init(struct spi_nor *nor) return err; } + err = spi_nor_octal_str_enable(nor, true); + if (err) { + dev_dbg(nor->dev, "octal STR mode not supported\n"); + return err; + } + err = spi_nor_quad_enable(nor); if (err) { dev_dbg(nor->dev, "quad mode not supported\n"); @@ -2714,6 +2766,7 @@ static int spi_nor_init(struct spi_nor *nor) if (nor->addr_nbytes == 4 && nor->read_proto != SNOR_PROTO_8_8_8_DTR && + nor->read_proto != SNOR_PROTO_8_8_8 && !(nor->flags & SNOR_F_4B_OPCODES)) { /* * If the RESET# pin isn't hooked up properly, or the system diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 85b0cf254e97..56795db872c2 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -359,6 +359,7 @@ struct spi_nor_otp { * Table. * @otp: SPI NOR OTP info. * @octal_dtr_enable: enables SPI NOR octal DTR mode. + * @octal_str_enable: enables SPI NOR octal STR mode. * @quad_enable: enables SPI NOR quad mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. * @convert_addr: converts an absolute address into something the flash @@ -508,7 +509,7 @@ struct flash_info { #define NO_CHIP_ERASE BIT(7) #define SPI_NOR_NO_FR BIT(8) - u8 no_sfdp_flags; + u16 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) #define SECT_4K BIT(1) #define SPI_NOR_DUAL_READ BIT(3) @@ -516,6 +517,8 @@ struct flash_info { #define SPI_NOR_OCTAL_READ BIT(5) #define SPI_NOR_OCTAL_DTR_READ BIT(6) #define SPI_NOR_OCTAL_DTR_PP BIT(7) +#define SPI_NOR_OCTAL_STR_READ BIT(8) +#define SPI_NOR_OCTAL_STR_PP BIT(9) u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0) From patchwork Wed Nov 23 21:13:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nathan Barrett-Morrison X-Patchwork-Id: 25217 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp3033015wrr; Wed, 23 Nov 2022 13:19:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf7vHa9nRVs0EyMXu1J5d88/T4ayzg3YukTkO26qnc7vcr3K97H1WxLEadRDYH5sOGZP3UC3 X-Received: by 2002:aa7:c788:0:b0:458:b9f9:9fba with SMTP id n8-20020aa7c788000000b00458b9f99fbamr10569534eds.305.1669238345600; Wed, 23 Nov 2022 13:19:05 -0800 (PST) ARC-Seal: i=1; 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[75.76.18.234]) by smtp.gmail.com with ESMTPSA id cf11-20020a05622a400b00b0039ee562799csm10222928qtb.59.2022.11.23.13.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:13:46 -0800 (PST) From: Nathan Barrett-Morrison Cc: nathan.morrison@timesys.com, greg.malysa@timesys.com, Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org (open list:SPI NOR SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/2] mtd: spi-nor: issi: Add in support for IS25LX256 chip, operating in Octal STR mode Date: Wed, 23 Nov 2022 16:13:35 -0500 Message-Id: <20221123211335.126417-3-nathan.morrison@timesys.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221123211335.126417-1-nathan.morrison@timesys.com> References: <20221123211335.126417-1-nathan.morrison@timesys.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750323267149218379?= X-GMAIL-MSGID: =?utf-8?q?1750323267149218379?= Adds the is25lx256 entry to the nor_parts table along with the additional STR enablement fixups and logic Signed-off-by: Nathan Barrett-Morrison --- drivers/mtd/spi-nor/issi.c | 101 +++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 89a66a19d754..89f3cdd51075 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -8,6 +8,15 @@ #include "core.h" +#define SPINOR_OP_STR_RD 0x8B /* Fast Read opcode in DTR mode */ +#define SPINOR_OP_STR_PP 0x82 /* Octal Input Fast Program */ +#define SPINOR_OP_RD_ANY_REG 0x85 /* Read volatile register */ +#define SPINOR_OP_WR_ANY_REG 0x81 /* Write volatile register */ +#define SPINOR_REG_CFR0V 0x00 /* For setting octal DTR mode */ +#define SPINOR_REG_CFR1V 0x01 /* For setting dummy cycles */ +#define SPINOR_OCT_STR 0xc7 /* Enable Octal DTR. */ +#define SPINOR_EXSPI 0xff /* Enable Extended SPI (default) */ + static int is25lp256_post_bfpt_fixups(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, @@ -29,6 +38,94 @@ static const struct spi_nor_fixups is25lp256_fixups = { .post_bfpt = is25lp256_post_bfpt_fixups, }; +static int spi_nor_issi_octal_str_enable(struct spi_nor *nor, bool enable) +{ + struct spi_mem_op op; + u8 *buf = nor->bouncebuf; + int ret; + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + if (enable) + *buf = SPINOR_OCT_STR; + else + *buf = SPINOR_EXSPI; + + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), + SPI_MEM_OP_ADDR(enable ? 3 : 4, + SPINOR_REG_CFR0V, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, buf, 1)); + + if (!enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_8); + else + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_1); + + + ret = spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + + /* Read flash ID to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), + buf, 1)); + + if (enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_8); + else + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_1_1_1); + + + ret = spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + if (memcmp(buf, nor->info->id, nor->info->id_len)) + return -EINVAL; + + return 0; +} + +static void is25lx256_default_init(struct spi_nor *nor) +{ + nor->params->octal_str_enable = spi_nor_issi_octal_str_enable; +} + +static void is25lx256_post_sfdp_fixup(struct spi_nor *nor) +{ + /* Fixup read command to 8 dummy cycles, 1S-1S-8S */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8; + spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8], + 0, 8, SPINOR_OP_STR_RD, + SNOR_PROTO_1_1_8); + + /* Fixup page program command to 1S-1S-8S */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8; + spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8], + SPINOR_OP_STR_PP, SNOR_PROTO_1_1_8); + + /* + * The BFPT quad enable field is set to a reserved value so the quad + * enable function is ignored by spi_nor_parse_bfpt(). Make sure we + * disable it. + */ + nor->params->quad_enable = NULL; +} + +static struct spi_nor_fixups is25lx256_fixups = { + .default_init = is25lx256_default_init, + .post_sfdp = is25lx256_post_sfdp_fixup, +}; + static void pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map = &nor->params->erase_map; @@ -74,6 +171,10 @@ static const struct flash_info issi_nor_parts[] = { NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) .fixups = &is25lp256_fixups }, + { "is25lx256", INFO(0x9d5a19, 0, 128 * 1024, 256) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_OCTAL_STR_PP | SPI_NOR_OCTAL_STR_READ) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE) + .fixups = &is25lx256_fixups }, /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2)