From patchwork Wed Nov 23 11:22:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 24915 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2730598wrr; Wed, 23 Nov 2022 03:30:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf7nH7O/FPLFSaqrScsN40u4QBSjET0jR3hn2tKlv55RAduwHDzZve3v9xLqPZnzgaRi01e+ X-Received: by 2002:a05:6a00:1348:b0:56b:e27f:76ee with SMTP id k8-20020a056a00134800b0056be27f76eemr8877169pfu.31.1669203031981; Wed, 23 Nov 2022 03:30:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669203031; cv=none; d=google.com; s=arc-20160816; b=zUxRu/PP3VwAp6Qc/iCP9zg1tIVjyGK0CzoWPcOy0HUqxHYevFAzuEWPKWKrbX2oFU p4V0Cre7+JVxBvF2p/qi4wuBC5/9+p2wVeeFEEjAfYw7VWO24yIMU2UCoAPCYbhVn4im On6nUKsAzuXDCeJXY1mQCU/7R+hQPP7TjSK0HQMnrdld0EYoAw9BmP0D8TsYsBIyAbva WkocwJUA+VghV0hbtsBtqZ1Xa5PGngGURe5TYZppSwWjtdeWauHT1MZoMwmi9zX3g6wO JKCZ8Fi4F/gcFwlCF3RYHpig0R49Z05lf4YxxWIsgZKNmBjol1AE1R2g6Jyt4iHEmvSj uZoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XP6vZYFDPWIn6pNXbO5iMAQrZK8MIxGZAjIhLsRpOUw=; b=TjX0buYTg1SkEznjvuWeWd0f2tmBoHpPzgM4Jq7Wveg7CzH48eQkMEXgxNS8A9i950 qRt2oSrAw+UyPrSyR62zOd1q4gZlAcvbgBwSz7Y4OJPUOjuWMCW361RC3Y9q/LwqctyQ o/xi6LGxO0eGteXBq8odWqM8UQVnhpalL7MaH47/xofYQZMnD4CeHJhYc3wGrWCoZHqi A29H9pF7GztCNcp2Sjhucp7x8BTEq4X00A10NUIr1y2UgXts6IoZWEceJXkiUd0rVj22 pyzQejMaNcz/FMqc2rlivO3ppjtS2b/BEq3ZaxcZyO7OkuHW5a/iqYoSUWAA/Sl9Jbg/ UlCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=oK5naAVE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v25-20020a634819000000b0046ec3853223si17394430pga.1.2022.11.23.03.30.19; Wed, 23 Nov 2022 03:30:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=oK5naAVE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236863AbiKWLXE (ORCPT + 99 others); Wed, 23 Nov 2022 06:23:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236771AbiKWLXB (ORCPT ); Wed, 23 Nov 2022 06:23:01 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE0CE720A4; Wed, 23 Nov 2022 03:22:59 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0C7336602A81; Wed, 23 Nov 2022 11:22:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669202578; bh=FcSDDQGVTs48svm5UE5nMhv131uY876jiQjW7TXgWaU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oK5naAVE5uEHv0KpuMCyjmE2US5BHWlS+VmyM1RRdJMTJhQpW3g4Yeb8pkoR+ByJY s6izPlBLuchQtwkn1snjWH/zHjjLWZ9QsnevmlWE3vciTXLHu7Ydwn58D3jlN/R8L5 4/uATYxBMbiL5EplmQsA/CxYM6atBYbKt4YmpHSId+mAi4kU8RVhc4dI4VPeGC/3Ns ySP+IS9qJfH4hSbl8MWfFYf1SKCdHusTwG/RpHpRX1FdOtrCT0Tq0Fqs+Yn3h7XNDw LxZ8/zRA9dxBVKC7jT8Yof0iaaG1kr51n92J/lhhnqxeNfR92ojmHImfXoHVvT4T3B RXS6AveDC2PbQ== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v2 1/4] dt-bindings: interrupt-controller: mediatek,cirq: Migrate to dt schema Date: Wed, 23 Nov 2022 12:22:46 +0100 Message-Id: <20221123112249.98281-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> References: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750286238217856956?= X-GMAIL-MSGID: =?utf-8?q?1750286238217856956?= Migrate mediatek,cirq.txt to dt schema as mediatek,mtk-cirq.yaml. While at it, I've also fixed some typos that were present in the original txt binding, as it was suggesting that the compatible string would have "mediatek,cirq" as compatible but, in reality, that's supposed to be "mediatek,mtk-cirq" instead. Little rewording on property descriptions also happened for them to be more concise. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../interrupt-controller/mediatek,cirq.txt | 33 --------- .../mediatek,mtk-cirq.yaml | 67 +++++++++++++++++++ 2 files changed, 67 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt deleted file mode 100644 index 5865f4f2c69d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Mediatek 27xx cirq - -In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to -work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC. -The external interrupts (outside MCUSYS) will feed through CIRQ and connect -to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive -interrupts and generate a pulse signal to parent interrupt controller when -flush command is executed. With CIRQ, MCUSYS can be completely turned off -to improve the system power consumption without losing interrupts. - -Required properties: -- compatible: should be one of - - "mediatek,mt2701-cirq" for mt2701 CIRQ - - "mediatek,mt8135-cirq" for mt8135 CIRQ - - "mediatek,mt8173-cirq" for mt8173 CIRQ - and "mediatek,cirq" as a fallback. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- reg: Physical base address of the cirq registers and length of memory - mapped region. -- mediatek,ext-irq-range: Identifies external irq number range in different - SOCs. - -Example: - cirq: interrupt-controller@10204000 { - compatible = "mediatek,mt2701-cirq", - "mediatek,mtk-cirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&sysirq>; - reg = <0 0x10204000 0 0x400>; - mediatek,ext-irq-start = <32 200>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml new file mode 100644 index 000000000000..4f1132c077ff --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Interrupt Controller + +maintainers: + - Youlin Pei + +description: + In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to + work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC. + The external interrupts (outside MCUSYS) will feed through CIRQ and connect + to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive + interrupts and generate a pulse signal to parent interrupt controller when + flush command is executed. With CIRQ, MCUSYS can be completely turned off + to improve the system power consumption without losing interrupts. + + +properties: + compatible: + items: + - enum: + - mediatek,mt2701-cirq + - mediatek,mt8135-cirq + - mediatek,mt8173-cirq + - const: mediatek,mtk-cirq + + reg: + maxItems: 1 + + '#interrupt-cells': + const: 3 + + interrupt-controller: true + + mediatek,ext-irq-range: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: First CIRQ interrupt + - description: Last CIRQ interrupt + description: + Identifies the range of external interrupts in different SoCs + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - mediatek,ext-irq-range + +additionalProperties: false + +examples: + - | + #include + + cirq: interrupt-controller@10204000 { + compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq"; + reg = <0x10204000 0x400>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&sysirq>; + mediatek,ext-irq-range = <32 200>; + }; From patchwork Wed Nov 23 11:22:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 24917 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2730674wrr; Wed, 23 Nov 2022 03:30:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf6/+ENrLCMyHKGnJuRRmQg466c91CpTbhHRyAAYAZlZ6TYOF5wkk9SHGC2FYPHu9irhmDvu X-Received: by 2002:a17:90a:4313:b0:212:e24e:16b3 with SMTP id q19-20020a17090a431300b00212e24e16b3mr35580542pjg.69.1669203042579; Wed, 23 Nov 2022 03:30:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669203042; cv=none; d=google.com; s=arc-20160816; b=uq4IbZBDzW/RwLB4z/se+/rkAOnJeZXqj7AsXe6Z1aigM7oRGtUNDCSmDON7+QHq3Q gNVjlDHwxzz8tK2sgdAczA3fO3T2a1v9/WJ8iN+GucTcNV0Ay+Y1nR+HJGP9sqZPniLG cdgBrjZhCXwXtbucFZVmnWQ2ZYi4IOTA1nApT9JSqY4wPYjMtC4f664iBRylwf/gTKTn mGxJ8V8BmRj9DMoRwJH1itkkgkV1K8qzwow6MY4BGX1GkBrSKZFqvryIyRkOxtvUvRqH zhQ1ew/borc9zpUJsj/C/1Y5dP5YdjqP7HMUXAZE0LrpU40QHQoQFqHVEVISMLfEFpwY effQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AQy/AVpcf6nocqEPr2r2lilyVn9dXFeimCksJLoRHuc=; b=eW6viklEti2hikv/1ep0+CSEfWctib1JsdJutw2eYWSmtFqMkf8m5JoCLbmYmuouy3 UlEOXEfNpOoA/UdKuD2LIIbF8N0ikMmWQmMok9fko5rDFHAA1rNsBMHzezkRkMAEPzKt zVkxamkDDBOVcOtfteJDBku/txYORn1nrkPwvHuWqaynDsMKHbNCL3BbTbmT2NKgAbpA bwykUWq2pEm+0bdVg5EMOi9nijCChCRIfdY1bvUUx5VakqAEvQgZsjwKsVlcCkAkMhtr VKgAzkmS1wcu9QM6eWS5I32c31s0uEsnBtqyBJRb/LjF+GPONGrnVL6UXWmFmmVx/K+A Jy/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=IEO4VhcC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ls10-20020a17090b350a00b0020d4dc7fa97si1805243pjb.110.2022.11.23.03.30.29; Wed, 23 Nov 2022 03:30:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=IEO4VhcC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236766AbiKWLXP (ORCPT + 99 others); Wed, 23 Nov 2022 06:23:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236782AbiKWLXC (ORCPT ); Wed, 23 Nov 2022 06:23:02 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B1FB72128; Wed, 23 Nov 2022 03:23:00 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C0EA86602AA1; Wed, 23 Nov 2022 11:22:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669202579; bh=NwKmpaNcpbD7LP5LEcTP4r+ZafVpwkZH2doF2FPT2FA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IEO4VhcCJqOVvSnNfKrgM/79lZKPBHuXXAjSFloFJTCeQRCN7qhCP7cMj//jK8Cxl E+CSWnWfFosMFC0zYkWwidESQ51LlagQYHo2jKcCbjEYwuQgLM5X69YdxwofqIOX/x VSJ6qrW5/0h1HEdYixVM5EpdjcqE5xCJElopRDNaR6cCHZXyjO24ikD5Jqpdyj96Xa GjAjz/1kw8YduVJ3gNhelUhd+a6eVnel8nLOBbbwjPcX15fCVhdLPCAT5F6fHrsuqJ YrIfxQWj8zr7H/vSmqy6m9NM56xaRKt5GrzwYd3Ouu7mGH1kXU4wbLBeAZbdwN8NM0 n9D1ohwg4uf5A== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno , Krzysztof Kozlowski Subject: [PATCH v2 2/4] dt-bindings: interrupt-controller: mediatek,cirq: Document MT8192 Date: Wed, 23 Nov 2022 12:22:47 +0100 Message-Id: <20221123112249.98281-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> References: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750286249632182525?= X-GMAIL-MSGID: =?utf-8?q?1750286249632182525?= Add compatible to support the SYS_CIRQ controller found on MT8192. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../bindings/interrupt-controller/mediatek,mtk-cirq.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml index 4f1132c077ff..fdcb4d8db818 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2701-cirq - mediatek,mt8135-cirq - mediatek,mt8173-cirq + - mediatek,mt8192-cirq - const: mediatek,mtk-cirq reg: From patchwork Wed Nov 23 11:22:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 24918 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2730691wrr; Wed, 23 Nov 2022 03:30:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf5JL/cjJ43ipvYIHy40eQ7L5cWdngqRp8mC0IMeRExKqB+LwFRzvfA8YE8zuTKeKuC4K0po X-Received: by 2002:a17:902:8217:b0:186:a5a7:cc3d with SMTP id x23-20020a170902821700b00186a5a7cc3dmr8171852pln.42.1669203043864; Wed, 23 Nov 2022 03:30:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669203043; cv=none; d=google.com; s=arc-20160816; b=zpUmHYvpxh4rSMK3GuMjOFUkzmOnUO+PWHglMLdhWYNGPUYfLQsXHA+jLi8Ao6AzpI Lyv2AQzBjYjl+Um7O3d/3WlRApYzKyoXmU1OYWCHM+mujh4baZ52WecaRBa40lIbQZp8 Mg7229DPSKEw4zI7DjObGsigs9ob4CT85/4soR0PNxHbazSroaWcimfUqNDVbIeclAqH 5fnRsy5/dcZsn5kgmGOQ+/ZdXQ4x7ZNPGUCiwGVEeiL3R5/c1FrJjKtCqhZsmwYNRxZW qa9bfDhmx1Nwrc8tTUKzsIYtA5RFu0uzXfzaDaHrp0EM/d0haYgh9SIXmRUCdv5Brm6s CG0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LhbrjQZbYhHn2g0+i2QtWopM9nry/S/jHRoyDq8716I=; b=LBdShfnOxb2zXsMb9ewWSx+xjRM0UW67kj3Oacu8Lw1pw1RfpljOuwpgstSNXr8NQ1 PE5S1Z7PLEDVZA9OB+V/5DZbQgFMQ49h9h4vH9HHg8qBJmWLiJB0ev5oC9lK/bPPEt8T ELkvBdwmqX8QewOkWGqKA1O3+/kjFPQxWMjOorVjoWn2iGzHBpjL28ZURfazRw3TH0o5 v2KTs5E96b6OyYgF7Mp/d6HxbJI8eSVzWqgqAMhWg02aRXt95yDiNJavkj8J9K3Srpl0 fK7iJUDHVLKHhAcVpW++7QqNSlRypVfMW1nh3ABiBWhpjcZyrC6hCQj3ZafEdRHnLNPT HJNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Ya21qjtu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a3-20020a1709027e4300b001889ad3ed98si14341583pln.462.2022.11.23.03.30.31; Wed, 23 Nov 2022 03:30:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Ya21qjtu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236950AbiKWLXW (ORCPT + 99 others); Wed, 23 Nov 2022 06:23:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236860AbiKWLXE (ORCPT ); Wed, 23 Nov 2022 06:23:04 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F4BB74CF6; Wed, 23 Nov 2022 03:23:01 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8C0796602ACF; Wed, 23 Nov 2022 11:22:59 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669202580; bh=EJD6I92pNgZOKf1m2pbzHsK9AlMSapcDK1LvROWOq0M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ya21qjtuxUFM+5FEgG20Rs6g74UDEH3ts3Hd60N6n3REVkhXycLdCqILmpfeK8W1F lKc4T8aRIy1/X9JII8eIcGTiAEqYI2l0ifDIoTc95P7m7uU2YrUzdvLmGdXlsVNefS Eq8AP362tyBB2/8QMqcRi4v/v4gjsO13RLL1UWfBDqOMlc6/XlI4zyeZSopCYt//8G 5X+PFZ4e6i890DkG8CFKynvsSopdp90/A5UHo6SJp5xNZgxNM2Ke4ncVfcE36N36Vk RZcqnHk8XoXkaEle5+CIUnJWraO6bVeCpQSWQ6HNX8YW09PEWdIMAZ678OguNKv2F8 F6ZNlwY1AYnfA== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v2 3/4] irqchip: irq-mtk-cirq: Move register offsets to const array Date: Wed, 23 Nov 2022 12:22:48 +0100 Message-Id: <20221123112249.98281-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> References: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750286251081149295?= X-GMAIL-MSGID: =?utf-8?q?1750286251081149295?= In preparation to add support for new SoCs having a different register layout, add an enumeration that documents register offsets and move the definitions for the same to a u32 array; Selecting the right register offsets array is done by adding an of_device_id array containing all of the currently supported compatible strings pointing to the "v1" offsets array (as data): since no devicetree declares the `mediatek,mtk-cirq` compatible without a SoC-specific one, it wasn't necessary to provide any legacy fallback. Every usage of the aforemementioned definitions was changed to get a register address through a newly introduced `mtk_cirq_reg()` accessor. This change brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/irqchip/irq-mtk-cirq.c | 78 ++++++++++++++++++++++++++-------- 1 file changed, 61 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index 9bca0918078e..4d873d2ba0fd 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -15,14 +15,29 @@ #include #include -#define CIRQ_ACK 0x40 -#define CIRQ_MASK_SET 0xc0 -#define CIRQ_MASK_CLR 0x100 -#define CIRQ_SENS_SET 0x180 -#define CIRQ_SENS_CLR 0x1c0 -#define CIRQ_POL_SET 0x240 -#define CIRQ_POL_CLR 0x280 -#define CIRQ_CONTROL 0x300 +enum mtk_cirq_reg_index { + CIRQ_STA, + CIRQ_ACK, + CIRQ_MASK_SET, + CIRQ_MASK_CLR, + CIRQ_SENS_SET, + CIRQ_SENS_CLR, + CIRQ_POL_SET, + CIRQ_POL_CLR, + CIRQ_CONTROL +}; + +static const u32 mtk_cirq_regs_v1[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x40, + [CIRQ_MASK_SET] = 0xc0, + [CIRQ_MASK_CLR] = 0x100, + [CIRQ_SENS_SET] = 0x180, + [CIRQ_SENS_CLR] = 0x1c0, + [CIRQ_POL_SET] = 0x240, + [CIRQ_POL_CLR] = 0x280, + [CIRQ_CONTROL] = 0x300, +}; #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 @@ -32,18 +47,28 @@ struct mtk_cirq_chip_data { void __iomem *base; unsigned int ext_irq_start; unsigned int ext_irq_end; + const u32 *offsets; struct irq_domain *domain; }; static struct mtk_cirq_chip_data *cirq_data; -static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset) +static inline void __iomem *mtk_cirq_reg(struct mtk_cirq_chip_data *chip_data, + enum mtk_cirq_reg_index idx, + unsigned int cirq_num) +{ + void __iomem *reg = chip_data->base + chip_data->offsets[idx]; + + return reg + (cirq_num / 32) * 4; +} + +static void mtk_cirq_write_mask(struct irq_data *data, enum mtk_cirq_reg_index idx) { struct mtk_cirq_chip_data *chip_data = data->chip_data; unsigned int cirq_num = data->hwirq; u32 mask = 1 << (cirq_num % 32); - writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4); + writel_relaxed(mask, mtk_cirq_reg(chip_data, idx, cirq_num)); } static void mtk_cirq_mask(struct irq_data *data) @@ -160,6 +185,7 @@ static const struct irq_domain_ops cirq_domain_ops = { #ifdef CONFIG_PM_SLEEP static int mtk_cirq_suspend(void) { + void __iomem *reg; u32 value, mask; unsigned int irq, hwirq_num; bool pending, masked; @@ -200,31 +226,34 @@ static int mtk_cirq_suspend(void) continue; } + reg = mtk_cirq_reg(cirq_data, CIRQ_ACK, i); mask = 1 << (i % 32); - writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4); + writel_relaxed(mask, reg); } /* set edge_only mode, record edge-triggerd interrupts */ /* enable cirq */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); + reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL, 0); + value = readl_relaxed(reg); value |= (CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, reg); return 0; } static void mtk_cirq_resume(void) { + void __iomem *reg = mtk_cirq_reg(cirq_data, CIRQ_CONTROL, 0); u32 value; /* flush recorded interrupts, will send signals to parent controller */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); - writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL); + value = readl_relaxed(reg); + writel_relaxed(value | CIRQ_FLUSH, reg); /* disable cirq */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); + value = readl_relaxed(reg); value &= ~(CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, reg); } static struct syscore_ops mtk_cirq_syscore_ops = { @@ -240,10 +269,18 @@ static void mtk_cirq_syscore_init(void) static inline void mtk_cirq_syscore_init(void) {} #endif +static const struct of_device_id mtk_cirq_of_match[] = { + { .compatible = "mediatek,mt2701-cirq", .data = &mtk_cirq_regs_v1 }, + { .compatible = "mediatek,mt8135-cirq", .data = &mtk_cirq_regs_v1 }, + { .compatible = "mediatek,mt8173-cirq", .data = &mtk_cirq_regs_v1 }, + { /* sentinel */ } +}; + static int __init mtk_cirq_of_init(struct device_node *node, struct device_node *parent) { struct irq_domain *domain, *domain_parent; + const struct of_device_id *match; unsigned int irq_num; int ret; @@ -274,6 +311,13 @@ static int __init mtk_cirq_of_init(struct device_node *node, if (ret) goto out_unmap; + match = of_match_node(mtk_cirq_of_match, node); + if (!match) { + ret = -ENODEV; + goto out_unmap; + } + cirq_data->offsets = match->data; + irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1; domain = irq_domain_add_hierarchy(domain_parent, 0, irq_num, node, From patchwork Wed Nov 23 11:22:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 24916 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2730612wrr; Wed, 23 Nov 2022 03:30:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf6d66FeG8nEw2MPRntiaIC5E3yOv6pTH5x0k1pouQJ4SQX/vnePmcSzl9nQZbDjB8+2z79D X-Received: by 2002:aa7:9149:0:b0:574:5637:8172 with SMTP id 9-20020aa79149000000b0057456378172mr2563375pfi.2.1669203033014; Wed, 23 Nov 2022 03:30:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669203033; cv=none; d=google.com; s=arc-20160816; b=lbhCwpN+7rPe66MOyOHk3HdifdIrCfepdQrsH/lM4w4yG8FyDdjgh4LRPd+ESJpo5y pZ9Fk0/bOaIw5X79akXdVavqWM737RUm5sC+W3jpgReJmmt4oRqiqHxxvUM6NcK81jad B6qcQNzL2MzwTpB+oLLsl4OyEzOUQTBqQszoLEWMbmTC47jeFlHO1GsR3tKgAeekWPFk FzrF+3jzVrul7Q2XQ0bnBvM/EjuQ3+x1Gij6q3VqPR+K7nn7NdP0YZCB3hdA4uZyiQtc Ik1q9C8zPnnmifBnkNN6nj85PUefhm7wcC2QstJ1ieCXXSFgxj35I8JKF+X0v65T1HqT R7eA== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id k9-20020a170902d58900b0017f59ed2dfasi17638030plh.63.2022.11.23.03.30.20; Wed, 23 Nov 2022 03:30:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=V20LmNqE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237148AbiKWLX3 (ORCPT + 99 others); Wed, 23 Nov 2022 06:23:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236527AbiKWLXH (ORCPT ); Wed, 23 Nov 2022 06:23:07 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F6DD769FA; Wed, 23 Nov 2022 03:23:02 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4C7426602AE2; Wed, 23 Nov 2022 11:23:00 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1669202580; bh=SS5h0AcRIuCYZwAghSxIqcJiZsZkfQ+w6DNodr6pz3o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V20LmNqEDP+RZ0vAsiU/DQZGF5/FzpEzVBLshk46yMDkXxGYO4LWXx9JEi0+gutz8 7kkJmsbuS0HechadCgfeRB/dAcVA+ZGOHCZdkS6XOipqkEsbdkZ+W80o0YoLoZryIg E+rNNVZNt9nbw0qBMh3Axy7Y0Do+7bzWppxD8u7S4leSJnC7gqdZFLMOZAKAx7RWo3 nzHCHgq83zmjzyDz+ettN+5uq7XAQBcTtioiPlt1XLAKPiDWkdLlfGEXmH1f2XU2m7 oVFRA55Z8wDuOJOMAzg/E+QXMHFj31rhFH7LxhejhrrflUQsKd/Y7jneWSXQLWo7tz lvioMV7HT09qg== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v2 4/4] irqchip: irq-mtk-cirq: Add support for System CIRQ on MT8192 Date: Wed, 23 Nov 2022 12:22:49 +0100 Message-Id: <20221123112249.98281-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> References: <20221123112249.98281-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750286239374463150?= X-GMAIL-MSGID: =?utf-8?q?1750286239374463150?= On some SoCs the System CIRQ register layout is slightly different, as there are more registers per function and in some cases other differences later in the layout: this is seen on at least MT8192, but it's also valid for some other "contemporary" SoCs both for Chromebooks and for smartphones. Add the new "v2" register layout and use it if the compatible "mediatek,mt8192-cirq" is found. Signed-off-by: AngeloGioacchino Del Regno --- drivers/irqchip/irq-mtk-cirq.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index 4d873d2ba0fd..57452d389b47 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -39,6 +39,18 @@ static const u32 mtk_cirq_regs_v1[] = { [CIRQ_CONTROL] = 0x300, }; +static const u32 mtk_cirq_regs_v2[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x80, + [CIRQ_MASK_SET] = 0x180, + [CIRQ_MASK_CLR] = 0x200, + [CIRQ_SENS_SET] = 0x300, + [CIRQ_SENS_CLR] = 0x380, + [CIRQ_POL_SET] = 0x480, + [CIRQ_POL_CLR] = 0x500, + [CIRQ_CONTROL] = 0x600, +}; + #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 #define CIRQ_FLUSH 0x4 @@ -273,6 +285,7 @@ static const struct of_device_id mtk_cirq_of_match[] = { { .compatible = "mediatek,mt2701-cirq", .data = &mtk_cirq_regs_v1 }, { .compatible = "mediatek,mt8135-cirq", .data = &mtk_cirq_regs_v1 }, { .compatible = "mediatek,mt8173-cirq", .data = &mtk_cirq_regs_v1 }, + { .compatible = "mediatek,mt8192-cirq", .data = &mtk_cirq_regs_v2 }, { /* sentinel */ } };