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Peter Anvin" , , Subject: [PATCH v4 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Date: Wed, 23 Nov 2022 18:08:47 +0800 Message-ID: <20221123100850.22969-2-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123100850.22969-1-rtanwar@maxlinear.com> References: <20221123100850.22969-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750282610262344961?= X-GMAIL-MSGID: =?utf-8?q?1750282610262344961?= Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Addditionally, add description which was missing in text file and add few more required standard properties which were also missing in text file. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 62 +++++++++++++++++++ .../intel,ce4100-lapic.yaml | 49 +++++++++++++++ 3 files changed, 111 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible = "intel,ce4100-ioapic"; - #interrupt-cells = <2>; - - Device's interrupt property: - - interrupts =

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible = "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..25d549220c2a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) + +maintainers: + - Rahul Tanwar + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for I/O APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible = "intel,ce4100-ioapic"; + reg = <0xfec00000 0x1000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml new file mode 100644 index 000000000000..88f320ef4616 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Rahul Tanwar + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for local APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-lapic + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible = "intel,ce4100-lapic"; + reg = <0xfee00000 0x1000>; + }; From patchwork Wed Nov 23 10:08:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24862 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2707183wrr; Wed, 23 Nov 2022 02:32:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf6oflQ/FfBwT8UE1U/vly4Wgxt+Flf/JhJq404ECwKvkDsQguBT9yIHnY1RxXdcik6Dm/gO X-Received: by 2002:a17:902:e383:b0:186:9c70:9b7d with SMTP id g3-20020a170902e38300b001869c709b7dmr8450617ple.3.1669199577298; Wed, 23 Nov 2022 02:32:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669199577; cv=none; d=google.com; s=arc-20160816; b=cx2285h5SxXiisPN0k2Nri31otces3h6dGa/+JufDnB1d34n7432YpbhPdTXqvYeRx j8Sc2He7x6VmE94km2SxrHA8ZoGEcrZh8EOOKbFBhqqGA16ukdy/GFP5cJW2fDG40662 uMS7x1Cyw7yBw/hIUXDfzvRVb86S94VbOmU39CqangkPT2MviY1vlYyDz/GDMuXQvV3x jpH0PlidsCkHSqxLKFCFSBzPqGEERqiIY7qV4dS+MYmDA8Vn8Cg6xbsWntbg8Ll9+PIB nxcFCPOXqQzTrQnMrKBJC9ygwv3agzN92Tk0BXo5GNW+LpsI7arD+D6KF4XsJehOKaSp MEog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xYvIQAHPDOiWXe8EWBzkMn7p0TefXGQ9AkwC3ZjhxhU=; b=DwzSsP6DeJfxvSTkpvG5w3Xmqeu4qklFIZs4lA5JE34SE8NoR3Ij/jQIMLxpA9yNSE 42qHgumM1SxdfQxcSSpE3qqtsDmUO1arjjlWEJgjPofQ3b21xGqsyXd05lSa1qyTyXjF 1Ufo5zngvDDtC8Sc+8Gi+nK+6+j9jJgYvxphEHWb25WyoVTypYdlW3x9FChVWLuIsGPx OMyRa+N375FATUYToHiAyJ8yOdigWRkzQhUZZN+wHj1rUlV2a9qfmfYWCi0y1OSScUcT 9U/mKYDOFFFw1BJPspSs0Tku7ydpAwgUj5VdG80dadlL3/uhNnNibZGMECss1/gCyjlr lt4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=ecVqpYYv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , , Subject: [PATCH v4 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Date: Wed, 23 Nov 2022 18:08:48 +0800 Message-ID: <20221123100850.22969-3-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123100850.22969-1-rtanwar@maxlinear.com> References: <20221123100850.22969-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750282616202803589?= X-GMAIL-MSGID: =?utf-8?q?1750282616202803589?= Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml index 88f320ef4616..ef47cb657335 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -35,6 +35,19 @@ properties: reg: maxItems: 1 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. + For ACPI or MPS spec compliant systems, it is figured out by some read + only bit field/s available in their respective defined data structures. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt delivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -46,4 +59,5 @@ examples: lapic0: interrupt-controller@fee00000 { compatible = "intel,ce4100-lapic"; reg = <0xfee00000 0x1000>; + intel,virtual-wire-mode; }; From patchwork Wed Nov 23 10:08:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24865 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2707198wrr; Wed, 23 Nov 2022 02:32:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf4wRnhnv0Go/w4pWQ42DmYpM8AZSSM79nM3Fedmn9oVYyKM817GTtJycxhmRCCxwlPaWydP X-Received: by 2002:a17:902:ab8d:b0:187:1e83:2505 with SMTP id f13-20020a170902ab8d00b001871e832505mr11743135plr.132.1669199578456; Wed, 23 Nov 2022 02:32:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669199578; cv=none; d=google.com; s=arc-20160816; b=Ut/v0qdWvVvb6d1WnsjHEbQsSq81TvvPeab303/KqX3E3uzEZi1imINNN2CWM9fTFG G6Pzij2LwMSgkBk0DTpHwBDE1gslZck+3TDE37ywS8eijvH3CQ/2fV2pOi5I6BsfJhjf /WTxlHPzX/Ci+4WOA1t+Pm+eG++C7+HDSQlfY6WYGQMQXHI87ftJ7B/9/K459QuKBG0w 7psRGPEL4H1U2oRQv4iP4tKY4kHnXNv0NlSPJ9h5J+3voHHbeaopTynwdSSeMbBYFDcg Y4dlZsBggEaKiYyyi99uQUv+e0undAXP/pjBxt30a+rmcW4aUzuASbAskelBScKdaFjF DZgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AkBrFNa8JXU1rnG3IW0QD6QbjBzAOYoAULmyjQGwhog=; b=cB5Unj/wHJ4P1V/7Gw7SZ33J90LZHQ4e4GRNRyC8e+LBI9EKRF/j4Dknx1oLPXtPQZ f9/vKHoFQvPwsWpOv3Fl4uDwS3n62n+Ku8ZuvAXgQ3VyVcQobdXYBMsvVGw+UBMFOCOI yNn7GSjOp/WTa0v2x0/UOWHtbrV+BSrzipl13cpvMnpHh4t9Eh0I0KVgy0Vwv/QQpiYS YLZSzvXRQRZI/j6BVb5s/AcW0NqoRvFjoeAPMmW1bgGGPbT1ErfOG8P6nonYG04czhpt YBOK+ENkMEFpbPH3gZk+0JXNaT4VRN4+2K7gGb3KUIaAFanLtTRb0PnF9Xxo30ma0ns9 Yl2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=IeCorsSJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , , Subject: [PATCH v4 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Date: Wed, 23 Nov 2022 18:08:49 +0800 Message-ID: <20221123100850.22969-4-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123100850.22969-1-rtanwar@maxlinear.com> References: <20221123100850.22969-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750282617219482338?= X-GMAIL-MSGID: =?utf-8?q?1750282617219482338?= Use latest available pr_lvl() instead of older printk(KERN_LVL) Just a upgrade of print utilities usage no functional changes. Reviewed-by: Andy Shevchenko Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..fcc6f1b7818f 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *dn) ret = of_address_to_resource(dn, 0, &r); if (ret) { - printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); + pr_err("Can't obtain address from device node %pOF.\n", dn); return; } mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); @@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void) of_ioapic = 1; return; } - printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); + pr_err("Error: No information about IO-APIC in OF.\n"); } #else static void __init dtb_ioapic_setup(void) {} From patchwork Wed Nov 23 10:08:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24866 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2707230wrr; Wed, 23 Nov 2022 02:33:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf6PM7BUAaj95pEad8sMeLHlPaQ+wD92UI3jdSrD03bgUxc4rxbDQFFfZBnMbGtLg8vdMZcM X-Received: by 2002:a17:902:c7d1:b0:179:b756:5b60 with SMTP id r17-20020a170902c7d100b00179b7565b60mr11755397pla.22.1669199582424; Wed, 23 Nov 2022 02:33:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669199582; cv=none; d=google.com; s=arc-20160816; b=l/aZeB9+m13TeqeDDJqbwK3W13uzjNWW5lWFacmmjpcnbMPU9dhKwCSNDmjtlSX/si wIM785zODarkvJfzdBtyTrpIINnuQRNyi/yCwLJI/xdwhpp5cMfwsPCLRIgYqom4Irhf TRDdeDEShwS/AgxVok30cPTTFc5ihgVeZ9hegaSlGUs51bh6+nM571L+0iqyzMHjf4or HxfCwksGw5gSSgWpaQjWblisDKF3lyy6AOUFh4SLQaJ5zy9y6i995VUl9gDuQxUg9Ahl LfyBDwLKqhawNvBk0wIxmlGbfrOaYdJLM6jru8KAeR3s9QJEPIr4N//WkCRA2d4FMn+R tY3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Mc2NS0olCt0qUzsLi0zWfYaDeL0jAmHwQjCqJZ5SsT8=; b=jJnRfO0/7s+YXISldttwCVlKSYzFOsTEpYw6hfEQq9F5kqXYdXLoCkn62tYN3TH3Tn /+BfR0aM6G0iUonaK5kt/f+JuQlFV3SMX8VS7TLkLm1AOhJRplPlvrjd/o/zPjDOu8r1 mmCQyXEX2WJUUgPj/zqAbgSxz37Scr5V56SpvMjlzzNKQGJQ9tYJ5ZRFfZqNNxVgPUBG JCrHpoLJ5YcQQJ5nCWIVVOleQ5EDJaocRh0zvzph2yOoapKzHclANr4TAjTLAhvmHGOa o3T+gYJ7F/8oKPdy2Np1p3ilTkN+x9nw6nvCPciUBaTcytzVeURCf878VNxNM/Br7YIB XlxA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=RcvdiO6Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , , Subject: [PATCH v4 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Date: Wed, 23 Nov 2022 18:08:50 +0800 Message-ID: <20221123100850.22969-5-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123100850.22969-1-rtanwar@maxlinear.com> References: <20221123100850.22969-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750282621383475499?= X-GMAIL-MSGID: =?utf-8?q?1750282621383475499?= Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This causes boot time crash for platforms which do not use 8259 compliant legacy PIC. Add support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Signed-off-by: Rahul Tanwar Reviewed-by: Andy Shevchenko --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config = 1; - pic_mode = 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + pr_info("Virtual Wire compatibility mode.\n"); + pic_mode = 0; + } else { + pr_info("IMCR and PIC compatibility mode.\n"); + pic_mode = 1; + } + register_lapic_address(lapic_addr); }