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Peter Anvin" , Subject: [PATCH v4 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Date: Wed, 23 Nov 2022 17:38:17 +0800 Message-ID: <20221123093820.21161-2-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750279546246907384?= X-GMAIL-MSGID: =?utf-8?q?1750279546246907384?= Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Addditionally, add description which was missing in text file and add few more required standard properties which were also missing in text file. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 62 +++++++++++++++++++ .../intel,ce4100-lapic.yaml | 49 +++++++++++++++ 3 files changed, 111 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible = "intel,ce4100-ioapic"; - #interrupt-cells = <2>; - - Device's interrupt property: - - interrupts =

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible = "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..25d549220c2a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) + +maintainers: + - Rahul Tanwar + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for I/O APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible = "intel,ce4100-ioapic"; + reg = <0xfec00000 0x1000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml new file mode 100644 index 000000000000..88f320ef4616 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Rahul Tanwar + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See [1] Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. + + This schema defines bindings for local APIC interrupt controller. + + [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + +properties: + compatible: + const: intel,ce4100-lapic + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible = "intel,ce4100-lapic"; + reg = <0xfee00000 0x1000>; + }; From patchwork Wed Nov 23 09:38:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24831 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2689538wrr; Wed, 23 Nov 2022 01:45:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf6BdcqnnSzTmVl+1WKugSLZF7MfpmT8odudAzEtavPYW7cixmUE6T6XcVr/0yhyi9W290FA X-Received: by 2002:a05:6402:2065:b0:469:82d0:ca4b with SMTP id bd5-20020a056402206500b0046982d0ca4bmr12483404edb.242.1669196705724; Wed, 23 Nov 2022 01:45:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669196705; cv=none; d=google.com; s=arc-20160816; b=uXcrBv7IwL2cOYvDVT6M8W6ZjMjdKoH11H7f0RkCaLF0lEzXWdp1pMDOhwN7dGtxGd 9uz6+EfKUHyNAwkKT5igwDkycd+liurdpsWOyLfo+X5h3NEnlQbxBN13jItJapNDiuiQ n+VusTpa9LFOYxuxACdSaGHIFRdt6slfo4yCr8RnwLxetSsTWT4PjXqnoWHjuffpD+sB vcHN4dItxh6MzFZF1CaXmXnNVmw6hxYoGlRTKpOHYM/0SdudNZywSzw4jhMLQmhEjTKd 2EexztAiMfpqrXoy7fiefu6XlBCI8/yfLr3EpLZNdfnU9yHEnDT4SF0JPtu08Ev9iolC GJDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xYvIQAHPDOiWXe8EWBzkMn7p0TefXGQ9AkwC3ZjhxhU=; b=mN0ssLVpEzxdQ0I8703atP5arGh3naRHwE69M7i9hdtHyl5lr7LUOOuPrS8gV6GoAQ WkiRlmU+nnDVBmVanKKZX4AvBosuovzwsJeBrvk2aCC1U/rzidg1BXHzqAXNucK5jJ13 uuOEG9cx+BR0fX5sDvZv3AzZqh1j2wED5lV4CuM0C24I8VWyOvkeZjIcMUtWqWg6sAWs YjKLewLnncoVxOMfkPoWFt5AV1NQQWakAyaNTDKhO9OCawRgQM9Yf3Gwlgm/whrKo6P4 A2dhIHY4ihnk7d1BNaYplDVwDOa7cyLJrgbKWybX3J6wQpaiuurEFIOZmhf7j2D+CqBc u4VA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=WnYVCqLM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Subject: [PATCH v4 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Date: Wed, 23 Nov 2022 17:38:18 +0800 Message-ID: <20221123093820.21161-3-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750279604811571286?= X-GMAIL-MSGID: =?utf-8?q?1750279604811571286?= Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml index 88f320ef4616..ef47cb657335 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -35,6 +35,19 @@ properties: reg: maxItems: 1 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. + For ACPI or MPS spec compliant systems, it is figured out by some read + only bit field/s available in their respective defined data structures. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt delivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -46,4 +59,5 @@ examples: lapic0: interrupt-controller@fee00000 { compatible = "intel,ce4100-lapic"; reg = <0xfee00000 0x1000>; + intel,virtual-wire-mode; }; From patchwork Wed Nov 23 09:38:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24829 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2689302wrr; Wed, 23 Nov 2022 01:44:24 -0800 (PST) X-Google-Smtp-Source: AA0mqf4R096zQaKtRpXJy7Ay+Ny5VDiQ1rNAURLP9X1y1AkdDqkiZ15w9dlch7xvbZn9kIsA7GTM X-Received: by 2002:a17:906:f2cf:b0:7ad:975f:b576 with SMTP id gz15-20020a170906f2cf00b007ad975fb576mr23065444ejb.49.1669196664538; Wed, 23 Nov 2022 01:44:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669196664; cv=none; d=google.com; s=arc-20160816; b=ivS2CphvzjA9vfZB8tP8k+uqFVOGrEv8FnmYyfjEJaMJ72jJDc298coQrRXJNySkHS rDAEfOwgW56T5BRpZ/mrkQoOLd5Twj3+maeEO4At88+QmrkIEMXxfoTej4lAd5LxmIkn oPRGw6FVei+bypOsqmN8i3MQ4pjWprklXlwJME4U+SpfKZfaVa87lxidRNwmJSXAQpWv cyhNtLUwHwf+roBhxEjkw14UIOBjB08ARyXoRqYjNkYm/OYP44gwK0O8XKsQquaSQY5z tLhxzdJmDAsQ26A4mGEZRKbLnVhZ1hiTVVh3Kotf30hwixBSDDzPx9CnWlnCgfULVO6W 9XlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AkBrFNa8JXU1rnG3IW0QD6QbjBzAOYoAULmyjQGwhog=; b=KZFVd427GKi5wu11CaA9XtAV1zy24RdbWeNbaWfCjeyOWNedxsKqP87MhBI+FBjFcx z2rlRS8pcEIYmHxwpyExSvwpSGj3+Up8+A88XuKDLlonS9bK9q5eUx9FCRAzZ1cULNJv n9w6ayis/vqR6Ld7H2eXQ5yb7SnnL39e63JNpMdB90Qq1GxEMKRvOUqgni1/KF6Z1afN xWduwAZa/Ls4/Xs9HR2RFRx9iWD8N4t34lZh+GuFjSJOe2TKsQCQsPpGbageBeKpaQ3Y CU4yuHfs7ArUEK1pwAeab6/1lkCYmJsHprF1ugDIYqdGZtNEwiOyJ3LstiOY9745qj8G PC8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=JdyvyQft; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Subject: [PATCH v4 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Date: Wed, 23 Nov 2022 17:38:19 +0800 Message-ID: <20221123093820.21161-4-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750279561775917848?= X-GMAIL-MSGID: =?utf-8?q?1750279561775917848?= Use latest available pr_lvl() instead of older printk(KERN_LVL) Just a upgrade of print utilities usage no functional changes. Reviewed-by: Andy Shevchenko Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..fcc6f1b7818f 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *dn) ret = of_address_to_resource(dn, 0, &r); if (ret) { - printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); + pr_err("Can't obtain address from device node %pOF.\n", dn); return; } mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); @@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void) of_ioapic = 1; return; } - printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); + pr_err("Error: No information about IO-APIC in OF.\n"); } #else static void __init dtb_ioapic_setup(void) {} From patchwork Wed Nov 23 09:38:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24830 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2689303wrr; Wed, 23 Nov 2022 01:44:25 -0800 (PST) X-Google-Smtp-Source: AA0mqf531P0ErE2zRdUYqwzbDksH7Ariy7G8QDK1yYeqWcPmt1AANiYEG7Y2E6icTCzeULJ2XnDi X-Received: by 2002:a17:906:9255:b0:7ad:c66e:ad9d with SMTP id c21-20020a170906925500b007adc66ead9dmr22262426ejx.413.1669196664828; Wed, 23 Nov 2022 01:44:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669196664; cv=none; d=google.com; s=arc-20160816; b=QRgwet7Taj8EwISyVf2qCyYWcWiElRK5xxywOCI+4BxAjkcH4rtze+qQ7Ow9nljSYX xAqKcMU39DP7YlRfMlP8N80zxgtB1dsgZVA6uu2jAhZ/mJkJG5IMBNB37lXKdJ0hd1e6 V4WFVrnXs1BrUGYFHCwapCjR4qj1ihhinmsMsr6+k6NP/3tnLtTkyY8cCPZVrRoVjbEC Oe0SPcm8hSS9Ku/DxmuIo+/76VYQav0ch5HM5m5mfjtr1xGrip/xf9D1QKLXQiN+EfpU NZpoaZKlFsbmXqu6N+K0c08kyfq4tRWvf1FCKg7mNhyfCr7s9K4vG/+LIY7kJ6bmeiWr 2lhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Mc2NS0olCt0qUzsLi0zWfYaDeL0jAmHwQjCqJZ5SsT8=; b=vpCBXViwbXNoNTIqEBAO5MHELVsmulqH0VtdwltAp+pyFN6awsosp1r6LsggdWI+5f G3xmMMGfkMGvE0zC3uhQMgwGn/cUZkN6qvCaZBZg+1dhCUaSWwVF98PCBzhYELEbJYx3 DsaLSQ8J465UbMsMNYfQM6R/9FrscYE/yT0MYmAcdVAldY6wjYopheTsdCIT2fjIV/M6 tnxkW2/2oZd8QA00zDK/USldk3CPdKYkbrMwVRrnWM0JyVhUj6Ev5WcWCfkF7kngTeDs bl+nES01McgnqtT5erYq/oR/quI6K4fgr6Tcxa7fbURLDy0PI5KYaJ1B6I8ucUr0dvMN VfdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=An+fYJ1a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Subject: [PATCH v4 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Date: Wed, 23 Nov 2022 17:38:20 +0800 Message-ID: <20221123093820.21161-5-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123093820.21161-1-rtanwar@maxlinear.com> References: <20221123093820.21161-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750279561516786964?= X-GMAIL-MSGID: =?utf-8?q?1750279561516786964?= Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This causes boot time crash for platforms which do not use 8259 compliant legacy PIC. Add support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config = 1; - pic_mode = 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + pr_info("Virtual Wire compatibility mode.\n"); + pic_mode = 0; + } else { + pr_info("IMCR and PIC compatibility mode.\n"); + pic_mode = 1; + } + register_lapic_address(lapic_addr); }