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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m9-20020a170906848900b007418a1e877dsi11287241ejx.580.2022.11.22.23.50.19; Tue, 22 Nov 2022 23:50:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T1b7VEEl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236062AbiKWHsz (ORCPT + 99 others); Wed, 23 Nov 2022 02:48:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235616AbiKWHsp (ORCPT ); Wed, 23 Nov 2022 02:48:45 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28052ECCE9 for ; Tue, 22 Nov 2022 23:48:42 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id q96-20020a17090a1b6900b00218b8f9035cso1113806pjq.5 for ; Tue, 22 Nov 2022 23:48:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qEZJoTwhQ3gMKVRNOyr1QQaSSeZV4Cc6rt58FdaM0ug=; b=T1b7VEEleMjpIKF5hl4CzQavZ639wHFKorulZTx9Bb+TUJk7XU1LPMm0Gmn87Gfthm Rg38SkGksnP/4/docKQY/s+m+Rykbi4GkvR/yUEGQbhcAE79KpcYUDTJs/WYpwFK/foo ApG3F5JLqDiloW216TJHQa/z71tQpld0df179spbUCTuZ8uwsexIYQeXguhU/+qQKJ+8 Dsl/AY7xbLFJ3kUUY9nRMHdyUs9+O8DNi0VNHm9NKNDSgZzHyOozOuyZlEAvrmikYXJd xxUoxdL/E5nbuoR1H1kuYbKW3E5YYiQURmoTtieCAGuYxV3JZRh3iHBclzc6N6tfJZy1 v73g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qEZJoTwhQ3gMKVRNOyr1QQaSSeZV4Cc6rt58FdaM0ug=; b=xWYmDCDOcAdNFGh/Py34ym781peiEe0jF5HYfHyJUlEnQNSKpy92m+ClE7zaIuQjoS X5XXiJSRpAmiqz40sYcPwUrjpuWd3446gehSF0ivCI2L2IsdsiIsL1SE7FbOlfEtcxFm 82CJGedUnvqnHxnXoKvrIYmBWdJjI226/s09dVUuBfN1lKvim52XY084tY0F2Zjp4xa6 qB5GxfqTQ5C6xUq/6EHVSbQmVh8Hy4fDC27P6YvhZ0J4r9elNbyinx8l0GEZl5MQqi8+ pdR3b3y8Z+bA0OU2BBz8jahKNcZcz3SLn9ICA9HSL1fh5d8Hn+0hPIOu71d2xJ1JPdB9 tudw== X-Gm-Message-State: ANoB5pmR9FUleEBTPc4mzZ1VfLOjzgCV9yGmkXMF7f4HcbZtzCs1UVkN E1sZoBjpNsl503u4nU0/rR/K X-Received: by 2002:a17:90a:ca13:b0:218:cf25:1e7a with SMTP id x19-20020a17090aca1300b00218cf251e7amr6783916pjt.29.1669189721600; Tue, 22 Nov 2022 23:48:41 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:40 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 01/20] phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions Date: Wed, 23 Nov 2022 13:18:07 +0530 Message-Id: <20221123074826.95369-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750272412309711320?= X-GMAIL-MSGID: =?utf-8?q?1750272412309711320?= Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 130 ++++++++++++------------ 1 file changed, 65 insertions(+), 65 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index c08d34ad1313..047f06c3313a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -107,7 +107,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, }; -static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { +static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -156,12 +156,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; -static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { +static const struct qmp_phy_init_tbl msm8996_ufs_tx[] = { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; -static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { +static const struct qmp_phy_init_tbl msm8996_ufs_rx[] = { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -175,7 +175,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), }; -static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { +static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -231,12 +231,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; -static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { +static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), }; -static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { +static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), @@ -254,7 +254,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), }; -static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { +static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f), @@ -266,7 +266,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ }; -static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { +static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), @@ -308,13 +308,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; -static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { +static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), }; -static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { +static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -333,7 +333,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), }; -static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { +static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -344,7 +344,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; -static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -374,7 +374,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; -static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -383,7 +383,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; -static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -421,7 +421,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { }; -static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -431,7 +431,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; -static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { +static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), @@ -461,7 +461,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; -static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { +static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), @@ -473,7 +473,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), }; -static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { +static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), @@ -513,7 +513,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), }; -static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { +static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), @@ -660,12 +660,12 @@ static const char * const qmp_phy_vreg_l[] = { static const struct qmp_phy_cfg msm8996_ufs_cfg = { .lanes = 1, - .serdes_tbl = msm8996_ufs_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), - .tx_tbl = msm8996_ufs_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), - .rx_tbl = msm8996_ufs_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), + .serdes_tbl = msm8996_ufs_serdes, + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes), + .tx_tbl = msm8996_ufs_tx, + .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx), + .rx_tbl = msm8996_ufs_rx, + .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx), .clk_list = msm8996_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -685,14 +685,14 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sdm845_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), - .tx_tbl = sdm845_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), - .rx_tbl = sdm845_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), - .pcs_tbl = sdm845_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), + .serdes_tbl = sdm845_ufsphy_serdes, + .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx_tbl = sdm845_ufsphy_tx, + .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx), + .rx_tbl = sdm845_ufsphy_rx, + .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs_tbl = sdm845_ufsphy_pcs, + .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs), .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -709,14 +709,14 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .lanes = 1, - .serdes_tbl = sm6115_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), - .tx_tbl = sm6115_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), - .rx_tbl = sm6115_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), - .pcs_tbl = sm6115_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), + .serdes_tbl = sm6115_ufsphy_serdes, + .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx_tbl = sm6115_ufsphy_tx, + .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx), + .rx_tbl = sm6115_ufsphy_rx, + .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs_tbl = sm6115_ufsphy_pcs, + .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs), .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -732,14 +732,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sm8150_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), - .tx_tbl = sm8150_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), - .rx_tbl = sm8150_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), - .pcs_tbl = sm8150_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .serdes_tbl = sm8150_ufsphy_serdes, + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx_tbl = sm8150_ufsphy_tx, + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx), + .rx_tbl = sm8150_ufsphy_rx, + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs_tbl = sm8150_ufsphy_pcs, + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs), .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -754,14 +754,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl = sm8350_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl = sm8350_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl = sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl = sm8350_ufsphy_serdes, + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl = sm8350_ufsphy_tx, + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl = sm8350_ufsphy_rx, + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl = sm8350_ufsphy_pcs, + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -776,14 +776,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sm8350_ufsphy_serdes_tbl, - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), - .tx_tbl = sm8350_ufsphy_tx_tbl, - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), - .rx_tbl = sm8350_ufsphy_rx_tbl, - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), - .pcs_tbl = sm8350_ufsphy_pcs_tbl, - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), + .serdes_tbl = sm8350_ufsphy_serdes, + .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx_tbl = sm8350_ufsphy_tx, + .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx), + .rx_tbl = sm8350_ufsphy_rx, + .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs_tbl = sm8350_ufsphy_pcs, + .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs), .clk_list = sm8450_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, From patchwork Wed Nov 23 07:48:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24766 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2648844wrr; Tue, 22 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f10-20020a056402004a00b0046a2ce37129si954299edu.616.2022.11.22.23.51.41; Tue, 22 Nov 2022 23:52:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pJQMn8gl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235767AbiKWHs7 (ORCPT + 99 others); Wed, 23 Nov 2022 02:48:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236051AbiKWHst (ORCPT ); Wed, 23 Nov 2022 02:48:49 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B013ECCE9 for ; Tue, 22 Nov 2022 23:48:48 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id p12so15930349plq.4 for ; Tue, 22 Nov 2022 23:48:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Su1NIZYU8/terDobSHxKGADJDrW1hfmKOqGKgPRAUt8=; b=pJQMn8glJWI/WtsSCZuR38phcR3RnPDZadpfmuWniRa+NG+YvaOMtJ3Rjz3Au6AcBi B8YclqGtNRSuQ8m8xU3tIwwhWGbDWSqlFbVsOFamvEA5VzhCrbeW9i1MJe1PRuDfqsjT kC4gtRUSSkafguTsnMlZJvdh4fsR74fdDHh2IPs/p7hTG/Ssx9KPZ97qmG8gnDMo+ryl UqjUn4XX0bNNAOm7Dg/cRUXV7woD6xSOawfsaXsDTQ0Ak8u0udpAlRSxFhJmeuViw/Ku i8zRL2RuCSHZ1Whqb92iUAngplF4sZyMZbf+4rRMuOP48lQRhBmksse2bKXrj235QKiS rOCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Su1NIZYU8/terDobSHxKGADJDrW1hfmKOqGKgPRAUt8=; b=YmLwKdYE8NghPFvxTwKULx4WL7BuYj96S5a8oN9DplhYTPGBbX9+XbN64/RA4bEJQA bYCLnL6Z6T4C1/Af6dIIg0mPphlQ7dUBBfgqwS8F6OfvPRHQeBNqehO90fvxOHm8+A/S BJqsd2rznZ8qE+x11jgv+rc9m0EMXnZsy9MiSSO3ZxqnR4eYcHIHMeUvJHG+6nDcF6Xv kI0vkldmJWyDRUuV1ozlndLNmzKcyBQ7QMJnObw/YvuK3FZkhLjY++lWjqtkGByFrKMu XsQFOexrqJtJHsxWVuWT8AAZL9YaYCp7ro/3owfwxMntnxcyjvvU96dZlcLmjynqExy1 QBjA== X-Gm-Message-State: ANoB5pm/tCkfGnEAD865RNAaAq2wI+7xsWEvaoF3rdokQPehGCT6By8O 3kd06kblJ5UQFiPj2v7saHIV X-Received: by 2002:a17:902:f707:b0:176:b0ce:3472 with SMTP id h7-20020a170902f70700b00176b0ce3472mr20126577plo.169.1669189727526; Tue, 22 Nov 2022 23:48:47 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:46 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 02/20] phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions Date: Wed, 23 Nov 2022 13:18:08 +0530 Message-Id: <20221123074826.95369-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750272493898553949?= X-GMAIL-MSGID: =?utf-8?q?1750272493898553949?= Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 047f06c3313a..443f2714a8f1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -107,7 +107,7 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, }; -static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = { +static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), @@ -156,12 +156,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), }; -static const struct qmp_phy_init_tbl msm8996_ufs_tx[] = { +static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), }; -static const struct qmp_phy_init_tbl msm8996_ufs_rx[] = { +static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), @@ -657,15 +657,15 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", }; -static const struct qmp_phy_cfg msm8996_ufs_cfg = { +static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { .lanes = 1, - .serdes_tbl = msm8996_ufs_serdes, - .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes), - .tx_tbl = msm8996_ufs_tx, - .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx), - .rx_tbl = msm8996_ufs_rx, - .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx), + .serdes_tbl = msm8996_ufsphy_serdes, + .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx_tbl = msm8996_ufsphy_tx, + .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx), + .rx_tbl = msm8996_ufsphy_rx, + .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx), .clk_list = msm8996_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -1146,7 +1146,7 @@ static int qmp_ufs_create(struct device *dev, struct device_node *np, int id, static const struct of_device_id qmp_ufs_of_match_table[] = { { .compatible = "qcom,msm8996-qmp-ufs-phy", - .data = &msm8996_ufs_cfg, + .data = &msm8996_ufsphy_cfg, }, { .compatible = "qcom,msm8998-qmp-ufs-phy", .data = &sdm845_ufsphy_cfg, From patchwork Wed Nov 23 07:48:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24772 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2649158wrr; Tue, 22 Nov 2022 23:53:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf765LDyKAKplcviNzV0It7AQnZfwlrrS6+sRe9Vdjj+IVBniA3tRR7oAH/A+jPV4PI/FKu9 X-Received: by 2002:aa7:d4c8:0:b0:469:5d86:ee4d with SMTP id t8-20020aa7d4c8000000b004695d86ee4dmr7403964edr.192.1669189985639; Tue, 22 Nov 2022 23:53:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669189985; cv=none; d=google.com; s=arc-20160816; b=a/apwiWFe0UbdZjs0DQS1cYRsZH66TFtwPSl8RUVbpIsBQUsMyXpGP7sbbGiGoIAdo 953erpefvQTMxOLKY3vfgX3VjCDS/DdpScfEYTKNZZ5F2X1taBmvFoLnktRPjL7d4TdE GErFrQ+eS7bjZWCe2rGYKfjImI+0tZ0LDMMgVZGfbiDW8WBc9g59lpXruqxX8m7GNxzx QmPtMz/u17m2j6GD80DEFjNp7ciVbUHstjXEJsDdOCDMLuan3VJvCkwwSR3RYJtA+TN1 wYX5sscDrhAEg+gv12NqGfzgSuYGj3kLg1uY7s+OEFPk+UmBFVzC0rSDObnNWripO9sv u3gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ikUhsMB1K+IImCkguofeQ85gazjJuE8IZCvzMOqkVlc=; b=UxWnLn3USDzXnBetlz33ZfofJDbv2sbvoYnpkScE2vtEWBQVozXv7LUxxPs5AEQNWS ptePbLQsiHRps9ZyuvmP9tnbxLz/rxZnvhQsv9VkItOkGtGXBsYq5Nd/3DUp2BFx6LA2 0N4p/XS2Peg/y7X+0nXYhDy/CnLR2TqxhzlitmUwxxuqqXDLDhKPeDgfjNuZZAmg56jC 4qsrXEKkI8w7J9hQhp/lhY/jDjI2gyNjZlSGyAMxZNdgl385Fvurhvd7Oc/AzLvnH5ln NSauW6SsNOZfO5CG0hzdTeq7nUcSmyyzLV1oL9L7UWNwS3X8Vs9ZoL7rbJRyi8XdzRnb 4Oow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N6BWzgRM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n26-20020aa7d05a000000b00469c73c9605si4192848edo.269.2022.11.22.23.52.41; Tue, 22 Nov 2022 23:53:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N6BWzgRM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236126AbiKWHtD (ORCPT + 99 others); Wed, 23 Nov 2022 02:49:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236054AbiKWHsz (ORCPT ); Wed, 23 Nov 2022 02:48:55 -0500 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BDAFFA717 for ; Tue, 22 Nov 2022 23:48:54 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id 62so16061459pgb.13 for ; Tue, 22 Nov 2022 23:48:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ikUhsMB1K+IImCkguofeQ85gazjJuE8IZCvzMOqkVlc=; b=N6BWzgRM3GU2/ZA+dngSkO6sddxPS8QvVv9bGitcc/SXgncaMWgeCWJNRTPBh9w0Fp HoELivWACbVF6BP8dLXxT8Cq4N5u//RgqiIK+iDDXqhASkd4P2A+DWcUIIL53EkqKMO+ yL/tT6pYGM2SiugPqnnE9k++/AT6+gXji7fHMAzv9gxe94fAopacgp8kwNsE6a5VpNTD LsKA29379+w5qrrgDNv22B6ccCpUwDVrrR3Eg3xlIW1kwCvW/kfTZAsO08FPtuB0ARtX na4jAKntKm1PDnVZ06+cxi/B1/Z5hSfmWEqTVVWbHur9zwoWIhQt3FHiWpxOKNi2TeVK hhKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ikUhsMB1K+IImCkguofeQ85gazjJuE8IZCvzMOqkVlc=; b=RDgzQOwC7Gf+xLbDLhJSvqGVJmz8JmNfQzxQtN8AlnB5uVSgA2+D2rZXSHnGgzNkGO 1XHsRlIIeBpWikS0eNyvM9rD+LahDa/rLPp8asXopCuhDaglY2tS+IFoqX1w3AccMJrD 7kqFjDLIYzYPxceQMmvgX3ZasmE5/mNPlDa6ovuNl5R76ph8qm1pq3G1s9kon9x+Fict dBLb/uc6Xkj/b4G2ipIfzhCyOUt18tjoT7qx7KIK21SGMJN16OlACbbslKY1j90rkIzn iq4J5CoV+SHcABHUKqTbeEBxqSSc9HOYj21NLvMfFDc8VExZDBDUfUvL0UtrXIQYMvMw uYcg== X-Gm-Message-State: ANoB5pmFiKVhp8R4GBnTpncV9KMVW5BN1KfveOCBIO3UGFXdHPkYIot4 vw9lA8AexQ0UOw8n0VSGBaoP X-Received: by 2002:a63:f003:0:b0:45f:bf86:c917 with SMTP id k3-20020a63f003000000b0045fbf86c917mr25393662pgh.201.1669189733521; Tue, 22 Nov 2022 23:48:53 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:52 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 03/20] phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct Date: Wed, 23 Nov 2022 13:18:09 +0530 Message-Id: <20221123074826.95369-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750272558098663339?= X-GMAIL-MSGID: =?utf-8?q?1750272558098663339?= As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 192 ++++++++++++++---------- 1 file changed, 112 insertions(+), 80 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 443f2714a8f1..3b7b36e32f5d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -531,19 +531,24 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +struct qmp_phy_cfg_tbls { + /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes; + int serdes_num; + const struct qmp_phy_init_tbl *tx; + int tx_num; + const struct qmp_phy_init_tbl *rx; + int rx_num; + const struct qmp_phy_init_tbl *pcs; + int pcs_num; +}; + /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { int lanes; - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ - const struct qmp_phy_init_tbl *serdes_tbl; - int serdes_tbl_num; - const struct qmp_phy_init_tbl *tx_tbl; - int tx_tbl_num; - const struct qmp_phy_init_tbl *rx_tbl; - int rx_tbl_num; - const struct qmp_phy_init_tbl *pcs_tbl; - int pcs_tbl_num; + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_cfg_tbls tbls; /* clock ids to be requested */ const char * const *clk_list; @@ -660,12 +665,14 @@ static const char * const qmp_phy_vreg_l[] = { static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { .lanes = 1, - .serdes_tbl = msm8996_ufsphy_serdes, - .serdes_tbl_num = ARRAY_SIZE(msm8996_ufsphy_serdes), - .tx_tbl = msm8996_ufsphy_tx, - .tx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_tx), - .rx_tbl = msm8996_ufsphy_rx, - .rx_tbl_num = ARRAY_SIZE(msm8996_ufsphy_rx), + .tbls = { + .serdes = msm8996_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), + .tx = msm8996_ufsphy_tx, + .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx), + .rx = msm8996_ufsphy_rx, + .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), + }, .clk_list = msm8996_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), @@ -685,14 +692,16 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sdm845_ufsphy_serdes, - .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes), - .tx_tbl = sdm845_ufsphy_tx, - .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx), - .rx_tbl = sdm845_ufsphy_rx, - .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx), - .pcs_tbl = sdm845_ufsphy_pcs, - .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs), + .tbls = { + .serdes = sdm845_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), + .tx = sdm845_ufsphy_tx, + .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), + .rx = sdm845_ufsphy_rx, + .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), + .pcs = sdm845_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -709,14 +718,16 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .lanes = 1, - .serdes_tbl = sm6115_ufsphy_serdes, - .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes), - .tx_tbl = sm6115_ufsphy_tx, - .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx), - .rx_tbl = sm6115_ufsphy_rx, - .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx), - .pcs_tbl = sm6115_ufsphy_pcs, - .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs), + .tbls = { + .serdes = sm6115_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), + .tx = sm6115_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), + .rx = sm6115_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), + .pcs = sm6115_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -732,14 +743,16 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sm8150_ufsphy_serdes, - .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes), - .tx_tbl = sm8150_ufsphy_tx, - .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx), - .rx_tbl = sm8150_ufsphy_rx, - .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx), - .pcs_tbl = sm8150_ufsphy_pcs, - .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs), + .tbls = { + .serdes = sm8150_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx = sm8150_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), + .rx = sm8150_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs = sm8150_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -754,14 +767,16 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sm8350_ufsphy_serdes, - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl = sm8350_ufsphy_tx, - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl = sm8350_ufsphy_rx, - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl = sm8350_ufsphy_pcs, - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls = { + .serdes = sm8350_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx = sm8350_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), + .rx = sm8350_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs = sm8350_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -776,14 +791,16 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .lanes = 2, - .serdes_tbl = sm8350_ufsphy_serdes, - .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes), - .tx_tbl = sm8350_ufsphy_tx, - .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx), - .rx_tbl = sm8350_ufsphy_rx, - .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx), - .pcs_tbl = sm8350_ufsphy_pcs, - .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs), + .tbls = { + .serdes = sm8350_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), + .tx = sm8350_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), + .rx = sm8350_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), + .pcs = sm8350_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), + }, .clk_list = sm8450_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -826,16 +843,50 @@ static void qmp_ufs_configure(void __iomem *base, qmp_ufs_configure_lane(base, regs, tbl, num, 0xff); } -static int qmp_ufs_serdes_init(struct qmp_phy *qphy) +static void qmp_ufs_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg = qphy->cfg; void __iomem *serdes = qphy->serdes; - const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; - int serdes_tbl_num = cfg->serdes_tbl_num; - qmp_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); + if (!tbls) + return; + + qmp_ufs_configure(serdes, cfg->regs, tbls->serdes, tbls->serdes_num); +} - return 0; +static void qmp_ufs_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tbls *tbls) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *tx = qphy->tx; + void __iomem *rx = qphy->rx; + + qmp_ufs_configure_lane(tx, cfg->regs, tbls->tx, tbls->tx_num, 1); + + if (cfg->lanes >= 2) + qmp_ufs_configure_lane(qphy->tx2, cfg->regs, tbls->tx, tbls->tx_num, 2); + + qmp_ufs_configure_lane(rx, cfg->regs, tbls->rx, tbls->rx_num, 1); + + if (cfg->lanes >= 2) + qmp_ufs_configure_lane(qphy->rx2, cfg->regs, tbls->rx, tbls->rx_num, 2); +} + +static void qmp_ufs_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tbls *tbls) +{ + const struct qmp_phy_cfg *cfg = qphy->cfg; + void __iomem *pcs = qphy->pcs; + + if (!tbls) + return; + + qmp_ufs_configure(pcs, cfg->regs, tbls->pcs, tbls->pcs_num); +} + +static void qmp_ufs_init_registers(struct qmp_phy *qphy, const struct qmp_phy_cfg *cfg) +{ + qmp_ufs_serdes_init(qphy, &cfg->tbls); + qmp_ufs_lanes_init(qphy, &cfg->tbls); + qmp_ufs_pcs_init(qphy, &cfg->tbls); } static int qmp_ufs_com_init(struct qmp_phy *qphy) @@ -933,31 +984,12 @@ static int qmp_ufs_power_on(struct phy *phy) struct qmp_phy *qphy = phy_get_drvdata(phy); struct qcom_qmp *qmp = qphy->qmp; const struct qmp_phy_cfg *cfg = qphy->cfg; - void __iomem *tx = qphy->tx; - void __iomem *rx = qphy->rx; void __iomem *pcs = qphy->pcs; void __iomem *status; unsigned int mask, val, ready; int ret; - qmp_ufs_serdes_init(qphy); - - /* Tx, Rx, and PCS configurations */ - qmp_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); - - if (cfg->lanes >= 2) { - qmp_ufs_configure_lane(qphy->tx2, cfg->regs, - cfg->tx_tbl, cfg->tx_tbl_num, 2); - } - - qmp_ufs_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1); - - if (cfg->lanes >= 2) { - qmp_ufs_configure_lane(qphy->rx2, cfg->regs, - cfg->rx_tbl, cfg->rx_tbl_num, 2); - } - - qmp_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); + qmp_ufs_init_registers(qphy, cfg); ret = reset_control_deassert(qmp->ufs_reset); if (ret) From patchwork Wed Nov 23 07:48:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24761 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2648658wrr; Tue, 22 Nov 2022 23:51:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf67u72Kg4ZtGABwiMz+4uTcBhSmYgeHZN+y13aRS1JMgdnHVRyLTjcel2POW8nsqsV/RWYO X-Received: by 2002:a17:907:9116:b0:78a:16ad:8250 with SMTP id p22-20020a170907911600b0078a16ad8250mr11247018ejq.747.1669189883113; Tue, 22 Nov 2022 23:51:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669189883; cv=none; d=google.com; s=arc-20160816; b=KN6BNHQt98jEpeNL0yd6BuQzVTa6xKhxFqHjiqsNllE69/lkSCdos0b9azKHbT+d50 10Rg7FNkl/YhppgZVFmhTGpx7AHQVaVLxaJdhbaE2s1sRJk8vu6mKVM5lO76/bjea9TK SIKv/tWcn6XixTlGazJvlqfZjDzrDAMapqaq2fIwmKBY5+RAvCIlyPG7Ks3REX6GaZgz EEGr/4P6AqH4WTtOpULcz5W9k84k8pJTXAfEOc9I65a0tY0WauMQfL/pH72mdFDMIaB4 0YAEDeTHt0l+CmEosYf+2jxAxZa0QTDcVo3QfMwcdSrAVr/Xq+5BHgLxgnlOxzR+xGsZ 7ilQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=17DUm1BHWO+9+pCruDSwXwFA2DWaV0LvIvFJmkLFp/8=; b=WOaMA0FI5Mkkijw+o2975AViD/pw8KKzwamB1qdlEHUxX44/O5pM+KT08YIIBjcgob dcgJ/L34wK+L/ktd8dQ57KT7szyTBb+BBZkrBc9xLyFaFOUec6mwQ5eN5VdNYMLVc8p/ X2LYzOYCWpq9tqkhHZqPXVxIVzDarG4FigZODflnAHoZIMhopKz0RXJ11QW9ccqrG/dL 4CB1mxWbf6kzD8bBn857010zODGQMsLNCssEnRkcIksBaTgcYLuesTvcm4KTaVZMiBDZ XEGCTnnRoBs58K4bvO15w7Op985VV2ZzangWLUPLC6kQqvXBUZjkRuND8eQ4/K4Sr0jb jyVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=szHgLObi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id z16-20020a170906715000b007aeef4dd9cfsi11308828ejj.908.2022.11.22.23.50.59; Tue, 22 Nov 2022 23:51:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=szHgLObi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236125AbiKWHtc (ORCPT + 99 others); Wed, 23 Nov 2022 02:49:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236054AbiKWHtJ (ORCPT ); Wed, 23 Nov 2022 02:49:09 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3E65FA731 for ; Tue, 22 Nov 2022 23:49:00 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id r18so16078239pgr.12 for ; Tue, 22 Nov 2022 23:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=17DUm1BHWO+9+pCruDSwXwFA2DWaV0LvIvFJmkLFp/8=; b=szHgLObizdRjU8Uhq446KGApvra49ApA5BIcru3Ey/6Do2T56DSsWvR5g9jLZHc476 MSlgWT8MIf8p+f/sxml/uIYI/OfERwdOxx5UrTrYqsRwWRZFHtuRDyZJ5Rx4UxQu9KFi bHD+ee5c55d9SFNG5Pwp6XrqCpbVMI7Noo/UYKv4oy6hdO4XzjAQT10xIo8VNGpS1lk0 Z20HdS4+82s4XqLdrE2uV7dVCOiPbh7w+y4ldF3k1iYZtAtLx40Dsl+kKesa4AdfKKoU pHw3S/F4iNp6nK3l1atD4eXQ9Qt72dI6wxGZlj7nTc6si+4kweYwgd/xG8XerHXUsBmF dhZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=17DUm1BHWO+9+pCruDSwXwFA2DWaV0LvIvFJmkLFp/8=; b=4J7Hjgsv7V/Nap/mhJRAagi1NDvQTUG2dWeQ75ychb4I0hHY04OtS9gOglIQQB8ova U3OFZQB3MJfXuOTOXPSNJYxLuc8qXKjjsf6ZZUzzNAZGSIBQwqYv0OMt1AO+pUIOatMa CAfIbg0zXnMiLSI6h4qpxYuyHfsaaq/WTOZQ2wTmP2ZWTmBwmL3tBbM2hUmMURN+9FLQ A1MOrx4EkfNp42ZnYSTs7XbxnOTukqo2YSju5xT3C8pawBjoUnqLPN7e7VUucP/MIFE2 jPskaR/hBE4LkxIhVdeTT3873h+2Ipf132D1wM8VpIRoizvoNkiQE6IW2P0Kaj5DBnkv ZbIw== X-Gm-Message-State: ANoB5plQb7n2tBTWBzpgSIN0ya4C5jdSaph2lHvwooAXDbBInKuePMqp VG+u4EKXCc8WU62o2iT7FyuZ X-Received: by 2002:a63:5007:0:b0:45f:beda:4116 with SMTP id e7-20020a635007000000b0045fbeda4116mr8165671pgb.618.1669189739616; Tue, 22 Nov 2022 23:48:59 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:48:58 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 04/20] phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode Date: Wed, 23 Nov 2022 13:18:10 +0530 Message-Id: <20221123074826.95369-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750272450763316941?= X-GMAIL-MSGID: =?utf-8?q?1750272450763316941?= Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 3b7b36e32f5d..694b1d6c1f9c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -20,6 +20,8 @@ #include #include +#include + #include #include "phy-qcom-qmp.h" @@ -549,6 +551,8 @@ struct qmp_phy_cfg { /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tbls tbls; + /* Additional sequence for HS Series B */ + const struct qmp_phy_cfg_tbls tbls_hs_b; /* clock ids to be requested */ const char * const *clk_list; @@ -582,6 +586,7 @@ struct qmp_phy_cfg { * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) * @pcs_misc: iomapped memory space for lane's pcs_misc * @qmp: QMP phy to which this lane belongs + * @mode: PHY mode configured by the UFS driver */ struct qmp_phy { struct phy *phy; @@ -594,6 +599,7 @@ struct qmp_phy { void __iomem *rx2; void __iomem *pcs_misc; struct qcom_qmp *qmp; + u32 mode; }; /** @@ -885,6 +891,8 @@ static void qmp_ufs_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tbls static void qmp_ufs_init_registers(struct qmp_phy *qphy, const struct qmp_phy_cfg *cfg) { qmp_ufs_serdes_init(qphy, &cfg->tbls); + if (qphy->mode == PHY_MODE_UFS_HS_B) + qmp_ufs_serdes_init(qphy, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qphy, &cfg->tbls); qmp_ufs_pcs_init(qphy, &cfg->tbls); } @@ -1073,6 +1081,15 @@ static int qmp_ufs_disable(struct phy *phy) return qmp_ufs_exit(phy); } +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct qmp_phy *qphy = phy_get_drvdata(phy); + + qphy->mode = mode; + + return 0; +} + static int qmp_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) { struct qcom_qmp *qmp = dev_get_drvdata(dev); @@ -1108,6 +1125,7 @@ static int qmp_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) static const struct phy_ops qcom_qmp_ufs_ops = { .power_on = qmp_ufs_enable, .power_off = qmp_ufs_disable, + .set_mode = qmp_ufs_set_mode, .owner = THIS_MODULE, }; From patchwork Wed Nov 23 07:48:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24760 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2648657wrr; Tue, 22 Nov 2022 23:51:22 -0800 (PST) X-Google-Smtp-Source: AA0mqf5isVcxF2scqqjJZgJtznuTljx4aO+Cz1I/J9EcucPlRrMRACtjvctXw32omqfm/QkYYoFM X-Received: by 2002:a05:6402:f91:b0:469:82f7:5013 with SMTP id eh17-20020a0564020f9100b0046982f75013mr13082103edb.234.1669189882206; Tue, 22 Nov 2022 23:51:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669189882; cv=none; d=google.com; s=arc-20160816; b=A4u/fOlBGhEg3bcm+mawWsb46ROZBVZspIzw5YnH3xPWmZuQVXUmM5AYUYV3pM8F/L sBRF9aprFXiG0fZ3SOunrZUVzIixYpUZ9S49+tchrPPs2hTA9FXhEM2Azjx0aiBAa0wR KEARnXcXRkgMOIQIb1l4SdWEAk27+WOdOaJb2O5I72e8S9tdYr2fzixkaVbMDQ4Ju+3D Y83+bx0E0GaQ7av199D7FWftnogh7hKKyOr4RKiAe+ZWiUBMLC+Mvo+ZUqubczt926yf 1ame0Ev2922IVNYBmb0Ji3ASCBkA/xzl8TLZiiD89Ki9EE1b2lViw/3BKSJEbbQ4eTQ+ +nEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lZ+MoCrzv+gfQQlMeW5WbAnmXRNL0HTRmdnVMxPl0cY=; b=n+ZrNmxNZxvhtauBgGsgzh5vY3GT2rOT98Elt8lKHXythZe7aMpNtsSVtEcuNDpOU2 yDkYDYkIFY+L2zL7R3qb8dpO/y8L0nvc12+j4AAoXfaypft2qx301yj+QZnvtcWxKBiA Id+wEyGVwMPgOSbNPLudaLedlDSE8iGwyr9ruX2CGlq6f2DgbemAHEygZXA2X7MSucI3 y+Vd3s5xbcLR1h2xPq0EQIdsAmIcierdBVd2uFMLr1x0emg1xyB6UC/UTYwavJIeLRO/ Y5u5LguGHpfRsIj/cwALX0K4i0GXRTblOEHstU/DGZWUXKuXfH8jqhNQ/IslkNNoQrqi xHYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rTVDZnzC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 694b1d6c1f9c..1b6e76bf82e5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -553,6 +553,8 @@ struct qmp_phy_cfg { const struct qmp_phy_cfg_tbls tbls; /* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b; + /* Additional sequence for HS G4 */ + const struct qmp_phy_cfg_tbls tbls_hs_g4; /* clock ids to be requested */ const char * const *clk_list; @@ -587,6 +589,7 @@ struct qmp_phy_cfg { * @pcs_misc: iomapped memory space for lane's pcs_misc * @qmp: QMP phy to which this lane belongs * @mode: PHY mode configured by the UFS driver + * @submode: PHY submode configured by the UFS driver */ struct qmp_phy { struct phy *phy; @@ -600,6 +603,7 @@ struct qmp_phy { void __iomem *pcs_misc; struct qcom_qmp *qmp; u32 mode; + u32 submode; }; /** @@ -894,7 +898,11 @@ static void qmp_ufs_init_registers(struct qmp_phy *qphy, const struct qmp_phy_cf if (qphy->mode == PHY_MODE_UFS_HS_B) qmp_ufs_serdes_init(qphy, &cfg->tbls_hs_b); qmp_ufs_lanes_init(qphy, &cfg->tbls); + if (qphy->submode == UFS_HS_G4) + qmp_ufs_lanes_init(qphy, &cfg->tbls_hs_g4); qmp_ufs_pcs_init(qphy, &cfg->tbls); + if (qphy->submode == UFS_HS_G4) + qmp_ufs_pcs_init(qphy, &cfg->tbls_hs_g4); } static int qmp_ufs_com_init(struct qmp_phy *qphy) @@ -1086,6 +1094,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) struct qmp_phy *qphy = phy_get_drvdata(phy); qphy->mode = mode; + qphy->submode = submode; return 0; } From patchwork Wed Nov 23 07:48:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24763 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2648791wrr; Tue, 22 Nov 2022 23:51:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf5/Ql8HfKZYQSJ4O5Hnj4vkaQvkmKYAOIElDkI3aXVGhhCYgjxYYveya4g3wuEa9TLt4lm4 X-Received: by 2002:a17:906:3982:b0:7ad:8bc6:46e7 with SMTP id h2-20020a170906398200b007ad8bc646e7mr24226847eje.28.1669189914257; Tue, 22 Nov 2022 23:51:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669189914; cv=none; d=google.com; s=arc-20160816; b=voI4C2iNCmEMqbzZEHPl/omhvsL4d56nuCr2JYmu47FH6SJ4lDqxC3wCjxT/vEiDV4 SxlBOLImu5rGya7u9YbUFMyHiK5vBcwNyq4quv85aZ7jnnVIunfLUVK6J0GHjBy8ecfu OltWbs79jWMyhVtcbH4TDbGEZTWG8N+yhTwmBWiHc4EdDbpip+UEP6llHaKXip2lRMGw dB3wOmFT45u2yE+xX1TGHrJGB74cXpRluSE7ZjYOzqMcZtI/ApCbC+ovfwU5aK0x/hcC MqZYTFE7MSN1UrJzwXV1VgNVD6axaMJzj7RX+30JIeETZmrZJ83LqPSIHvSc8rLs4s6u l//g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=c56xjSGwfmMkQ772Tv3sbW08SSFT7wB9ddz0u8vdom0=; b=cisrAx5O8t1vPuJIQ7lJYnRTCGJqz5U380D5X0BwuKowAHnIkzXuBSV5BRBBqgIv+b fMDjUkb1VRoLV06CWB7FQFsN5mw6TJ46p6ug0t1ySemej48UflvDNsmorFfPgP911d04 /0Zqgr8aCBe/kA9q4e+aaqJGlpMlHk8/GzwjABudrSPLCZdHkZGPHqCR5A615xYxaoB/ W+Hibc5ZMWe7oUtD9fPv5HUR3hR3mbBkkLPvcBubUrUBL2M6Z7gymKVaLBtchpj37tYV 2yEVAiLM8J8/5CCnUbIbX38wrBShrxFARdiFSEJ0U9JTGngDOutmVtsvvLWxRTf8m4n+ Jwuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=li29VgAj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 33 +++++++++++++++++++++---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 1b6e76bf82e5..f6a962df9df1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -228,8 +228,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), +}; - /* Rate B */ +static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), }; @@ -305,8 +306,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), +}; - /* Rate B */ +static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), }; @@ -371,8 +373,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; - /* Rate B */ +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), }; @@ -420,7 +423,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), - }; static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { @@ -458,8 +460,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), +}; - /* Rate B */ +static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), }; @@ -712,6 +715,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .pcs = sdm845_ufsphy_pcs, .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), }, + .tbls_hs_b = { + .serdes = sdm845_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -738,6 +745,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .pcs = sm6115_ufsphy_pcs, .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), }, + .tbls_hs_b = { + .serdes = sm6115_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -763,6 +774,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .pcs = sm8150_ufsphy_pcs, .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), }, + .tbls_hs_b = { + .serdes = sm8150_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -787,6 +802,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .pcs = sm8350_ufsphy_pcs, .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b = { + .serdes = sm8350_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, @@ -811,6 +830,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .pcs = sm8350_ufsphy_pcs, .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), }, + .tbls_hs_b = { + .serdes = sm8350_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), + }, .clk_list = sm8450_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, From patchwork Wed Nov 23 07:48:13 2022 Content-Type: text/plain; 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Hence, add the required register settings using the tables_hs_g4 struct instance. Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index f6a962df9df1..98ebaf898a50 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -388,6 +388,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), }; +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), @@ -425,6 +429,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), }; +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), @@ -435,6 +458,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -778,6 +806,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .serdes = sm8150_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 = { + .tx = sm8150_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), + .rx = sm8150_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), + .pcs = sm8150_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, .clk_list = sdm845_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, From patchwork Wed Nov 23 07:48:14 2022 Content-Type: text/plain; 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Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 66 ++++++++++++++++++++++++- 1 file changed, 65 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 98ebaf898a50..d39ee28fb6a3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -463,6 +463,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), }; +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), +}; + static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), @@ -825,6 +853,42 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .phy_status = PHYSTATUS, }; +static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { + .lanes = 2, + + .tbls = { + .serdes = sm8150_ufsphy_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), + .tx = sm8150_ufsphy_tx, + .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), + .rx = sm8150_ufsphy_rx, + .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), + .pcs = sm8150_ufsphy_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8150_ufsphy_hs_b_serdes, + .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8250_ufsphy_hs_g4_tx, + .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), + .rx = sm8250_ufsphy_hs_g4_rx, + .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), + .pcs = sm8150_ufsphy_hs_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), + }, + .clk_list = sdm845_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .phy_status = PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .lanes = 2, @@ -1288,7 +1352,7 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { .data = &sm8150_ufsphy_cfg, }, { .compatible = "qcom,sm8250-qmp-ufs-phy", - .data = &sm8150_ufsphy_cfg, + .data = &sm8250_ufsphy_cfg, }, { .compatible = "qcom,sm8350-qmp-ufs-phy", .data = &sm8350_ufsphy_cfg, From patchwork Wed Nov 23 07:48:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24765 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2648810wrr; Tue, 22 Nov 2022 23:51:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf5UUx0l3tmDeTeq4Tzx6MpiPOETvBHYbtteqIganHgmJxeY4nnXdawVOjIRHhpHd1sQPdE5 X-Received: by 2002:a17:906:19d6:b0:7ac:9917:c9c6 with SMTP id h22-20020a17090619d600b007ac9917c9c6mr6071368ejd.325.1669189919042; Tue, 22 Nov 2022 23:51:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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Hence, add the required register settings using the tables_hs_g4 struct instance. Signed-off-by: Manivannan Sadhasivam --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 48 +++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h index bcca23493b7e..3aa4232f84a6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -13,6 +13,7 @@ #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index d39ee28fb6a3..7a77db3196db 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -592,6 +592,46 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), }; +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), + QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), +}; + +static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), + /* + * Following registers are not required for HS-G4 mode, but since these + * are already programmed as part of previous init sequence, we'll program + * again with reset values. + */ + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x2d), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xb0), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xff), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x15), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), + QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), +}; + struct qmp_phy_cfg_tbls { /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes; @@ -934,6 +974,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .serdes = sm8350_ufsphy_hs_b_serdes, .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), }, + .tbls_hs_g4 = { + .tx = sm8350_ufsphy_g4_tx, + .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), + .rx = sm8350_ufsphy_g4_rx, + .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), + .pcs = sm8350_ufsphy_g4_pcs, + .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), + }, .clk_list = sm8450_ufs_phy_clk_l, .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, From patchwork Wed Nov 23 07:48:16 2022 Content-Type: text/plain; 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But in this driver, goto statements are used for just returning the error code in many places. This really makes it hard to read the code. So let's get rid of those goto statements and just return the error code directly. Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++--------------------- 1 file changed, 41 insertions(+), 59 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8ad1415e10b6..7cd996ac180b 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) { - int err = 0; + int err; struct device *dev = host->hba->dev; if (host->is_lane_clks_enabled) @@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", host->rx_l0_sync_clk); if (err) - goto out; + return err; err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", host->tx_l0_sync_clk); @@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) goto disable_rx_l1; host->is_lane_clks_enabled = true; - goto out; + + return 0; disable_rx_l1: clk_disable_unprepare(host->rx_l1_sync_clk); @@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) clk_disable_unprepare(host->tx_l0_sync_clk); disable_rx_l0: clk_disable_unprepare(host->rx_l0_sync_clk); -out: + return err; } @@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", &host->rx_l0_sync_clk, false); if (err) - goto out; + return err; err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", &host->tx_l0_sync_clk, false); if (err) - goto out; + return err; /* In case of single lane per direction, don't read lane1 clocks */ if (host->hba->lanes_per_direction > 1) { err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", &host->rx_l1_sync_clk, false); if (err) - goto out; + return err; err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", &host->tx_l1_sync_clk, true); } -out: - return err; + + return 0; } static int ufs_qcom_check_hibern8(struct ufs_hba *hba) @@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) if (!host->core_reset) { dev_warn(hba->dev, "%s: reset control not set\n", __func__); - goto out; + return 0; } reenable_intr = hba->is_irq_enabled; @@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) if (ret) { dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", __func__, ret); - goto out; + return ret; } /* @@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) hba->is_irq_enabled = true; } -out: - return ret; + return 0; } static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct phy *phy = host->generic_phy; - int ret = 0; + int ret; bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B; /* Reset UFS Host Controller and PHY */ @@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) if (ret) { dev_err(hba->dev, "%s: phy init failed, ret = %d\n", __func__, ret); - goto out; + return ret; } /* power on phy - start serdes and phy's power and clocks */ @@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) out_disable_phy: phy_exit(phy); -out: + return ret; } @@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, u32 hs, u32 rate, bool update_link_startup_timer) { - int ret = 0; struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct ufs_clk_info *clki; u32 core_clk_period_in_ns; @@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, * Aggregation logic. */ if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) - goto out; + return 0; if (gear == 0) { dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); - goto out_error; + return -EINVAL; } list_for_each_entry(clki, &hba->clk_list_head, list) { @@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, } if (ufs_qcom_cap_qunipro(host)) - goto out; + return 0; core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; @@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rA)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; } else if (rate == PA_HS_MODE_B) { @@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(hs_fr_table_rB)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; } else { dev_err(hba->dev, "%s: invalid rate = %d\n", __func__, rate); - goto out_error; + return -EINVAL; } break; case SLOWAUTO_MODE: @@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, "%s: index %d exceeds table size %zu\n", __func__, gear, ARRAY_SIZE(pwm_fr_table)); - goto out_error; + return -EINVAL; } tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; break; case UNCHANGED: default: dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); - goto out_error; + return -EINVAL; } if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != @@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, */ mb(); } - goto out; -out_error: - ret = -EINVAL; -out: - return ret; + return 0; } static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, @@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, 0, true)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); - err = -EINVAL; - goto out; + return -EINVAL; } if (ufs_qcom_cap_qunipro(host)) @@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, break; } -out: return err; } @@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, if (!dev_req_params) { pr_err("%s: incoming dev_req_params is NULL\n", __func__); - ret = -EINVAL; - goto out; + return -EINVAL; } switch (status) { @@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, if (ret) { pr_err("%s: failed to determine capabilities\n", __func__); - goto out; + return ret; } /* enable the device ref clock before changing to HS mode */ @@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, ret = -EINVAL; break; } -out: + return ret; } @@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), &pa_vs_config_reg1); if (err) - goto out; + return err; /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ - err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), (pa_vs_config_reg1 | (1 << 12))); - -out: - return err; } static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) @@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); if (!host) { - err = -ENOMEM; dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); - goto out; + return -ENOMEM; } /* Make a two way bind between the qcom host and the hba */ @@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->rcdev.owner = dev->driver->owner; host->rcdev.nr_resets = 1; err = devm_reset_controller_register(dev, &host->rcdev); - if (err) { + if (err) dev_warn(dev, "Failed to register reset controller\n"); - err = 0; - } if (!has_acpi_companion(dev)) { host->generic_phy = devm_phy_get(dev, "ufsphy"); @@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN; ufs_qcom_get_default_testbus_cfg(host); err = ufs_qcom_testbus_config(host); - if (err) { + if (err) + /* Failure is non-fatal */ dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); - err = 0; - } - goto out; + return 0; out_variant_clear: ufshcd_set_variant(hba, NULL); -out: + return err; } @@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); if (err) - goto out; + return err; core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; core_clk_ctrl_reg |= clk_cycles; @@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; - err = ufshcd_dme_set(hba, + return ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); -out: - return err; } static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) @@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, if (err || !dev_req_params) { ufshcd_uic_hibern8_exit(hba); - goto out; + return err; } ufs_qcom_cfg_timers(hba, @@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, ufshcd_uic_hibern8_exit(hba); } -out: - return err; + return 0; } static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, From patchwork Wed Nov 23 07:48:17 2022 Content-Type: text/plain; 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So there is no reason to use a WARN_ON on the "id". Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 7cd996ac180b..8bb0f4415f1a 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -895,8 +895,6 @@ ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) { struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_assert_reset(host->hba); /* provide 1ms delay to let the reset pulse propagate. */ usleep_range(1000, 1100); @@ -908,8 +906,6 @@ ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); - /* Currently this code only knows about a single reset. */ - WARN_ON(id); ufs_qcom_deassert_reset(host->hba); /* From patchwork Wed Nov 23 07:48:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24768 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2648973wrr; Tue, 22 Nov 2022 23:52:31 -0800 (PST) X-Google-Smtp-Source: AA0mqf7WjkB1tc2Av0Lrc9X4wzZRPmq5kDla8h2K21xj6ptvhv3/CsbLUl7soqXqxII3DHedehjH X-Received: by 2002:a05:6402:b4e:b0:469:7e00:525d with SMTP id bx14-20020a0564020b4e00b004697e00525dmr13093597edb.157.1669189951228; Tue, 22 Nov 2022 23:52:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669189951; cv=none; d=google.com; s=arc-20160816; b=UxutAcIZzPHGNhY9MlXO+7QkFcyuJE9nfLG8TO+J6j+zb/Q/HlmFLUQ+Lyuojb6IwZ /9rmsVV3NvRviWfYw7nMDlzjCtoQKlG3EwOGFKZf5UMEk8kS/T+13pFj8MX+S+Z4zkmm mQj0gS47JFZS/qgGDsEE4V2oYJm5pXj/VupfQ4g5W1bItwfisr8vYMWAmo4iMkVlJe8n +R0gxOf0WPmflXkomATT7lfSPxfCuaNKCMBqEX3UIm69ILKeqN1diBCbNVXCuKwi3bPE BlMB7GH/P2mHhvCD4e7/bewOSgiWfYBafcRAKfU6GjSTuJox9nIdj+651e6hYmfS2fDA B3MQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Bgs3s1G1jssoUlSih9AtMddjkl0seI8sJyhiWnXePTs=; b=nhzw7/XtfQmd5X0MAKQKTuQ3CvBfqbAm08/wo2kyejPIz64dMRCNeRtKOtMEPxuja4 c5UIHo0s3j3X21fWbROc/Bodt+zDQs/E2FlcAjPtEA6uCCaO2cnkV/zaOVLrj9q4KkMu /GsYI7wl5nT6GsmIytoUPdzfY6j7JHVhAcXvsZPgM5+/QDWWF0ppIe5VeEkFqN5wFvEk 8yC+7Hf62xaTn8EiSA8+G6l8S+1kTAX4/3svGLk0nMJdMysQcOfT6dKrT3sMry6tRKWk OPtAHwCpBQxq3ATx/FHjVElNuvUhWRDhOjldHHwHSY5ybtWBRhpXgRjHBoYa00Als+et uigA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wUq6WL4d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 44466a395bb5..9d96ac71b27f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -17,12 +17,9 @@ #define DEFAULT_CLK_RATE_HZ 1000000 #define BUS_VECTOR_NAME_LEN 32 -#define UFS_HW_VER_MAJOR_SHFT (28) -#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT) -#define UFS_HW_VER_MINOR_SHFT (16) -#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT) -#define UFS_HW_VER_STEP_SHFT (0) -#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT) +#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28) +#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16) +#define UFS_HW_VER_STEP_MASK GENMASK(15, 0) /* vendor specific pre-defined parameters */ #define SLOW 1 @@ -76,24 +73,28 @@ enum { #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) /* bit definitions for REG_UFS_CFG1 register */ -#define QUNIPRO_SEL 0x1 -#define UTP_DBG_RAMS_EN 0x20000 +#define QUNIPRO_SEL BIT(0) +#define UFS_PHY_SOFT_RESET BIT(1) +#define UTP_DBG_RAMS_EN BIT(17) #define TEST_BUS_EN BIT(18) #define TEST_BUS_SEL GENMASK(22, 19) #define UFS_REG_TEST_BUS_EN BIT(30) +#define UFS_PHY_RESET_ENABLE 1 +#define UFS_PHY_RESET_DISABLE 0 + /* bit definitions for REG_UFS_CFG2 register */ -#define UAWM_HW_CGC_EN (1 << 0) -#define UARM_HW_CGC_EN (1 << 1) -#define TXUC_HW_CGC_EN (1 << 2) -#define RXUC_HW_CGC_EN (1 << 3) -#define DFC_HW_CGC_EN (1 << 4) -#define TRLUT_HW_CGC_EN (1 << 5) -#define TMRLUT_HW_CGC_EN (1 << 6) -#define OCSC_HW_CGC_EN (1 << 7) +#define UAWM_HW_CGC_EN BIT(0) +#define UARM_HW_CGC_EN BIT(1) +#define TXUC_HW_CGC_EN BIT(2) +#define RXUC_HW_CGC_EN BIT(3) +#define DFC_HW_CGC_EN BIT(4) +#define TRLUT_HW_CGC_EN BIT(5) +#define TMRLUT_HW_CGC_EN BIT(6) +#define OCSC_HW_CGC_EN BIT(7) /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ -#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */ +#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\ TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\ @@ -101,17 +102,11 @@ enum { TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN) /* bit offset */ -enum { - OFFSET_UFS_PHY_SOFT_RESET = 1, - OFFSET_CLK_NS_REG = 10, -}; +#define OFFSET_CLK_NS_REG 0xa /* bit masks */ -enum { - MASK_UFS_PHY_SOFT_RESET = 0x2, - MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF, - MASK_CLK_NS_REG = 0xFFFC00, -}; +#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0) +#define MASK_CLK_NS_REG GENMASK(23, 10) /* QCOM UFS debug print bit mask */ #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0) @@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, { u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); - *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT; - *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT; - *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT; + *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver); + *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver); + *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver); }; static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE), + REG_UFS_CFG1); /* * Make sure assertion of ufs phy reset is written to @@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) { - ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET, - 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1); + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE), + REG_UFS_CFG1); /* * Make sure de-assertion of ufs phy reset is written to From patchwork Wed Nov 23 07:48:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24769 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2648994wrr; Tue, 22 Nov 2022 23:52:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf61ueWcWdFsP+TWPG+UDC0CHABb1pCGCGHbRkXVGb5bt3YoGcQx7rzt/8B9ewo8DkgM0U5P X-Received: by 2002:a05:6402:4147:b0:461:b2b1:9702 with SMTP id x7-20020a056402414700b00461b2b19702mr8832614eda.274.1669189954002; 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Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 8bb0f4415f1a..38e2ed749d75 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1441,9 +1441,9 @@ static int ufs_qcom_probe(struct platform_device *pdev) /* Perform generic probe */ err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); if (err) - dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err); + return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); - return err; + return 0; } /** From patchwork Wed Nov 23 07:48:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24771 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2649111wrr; Tue, 22 Nov 2022 23:52:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf4ZfQdZDLWNanrN6mxl6YIcktOJiMJKh881v7RzbAOn9bbBf3XdInWKrdbx0FFteFTiniIl X-Received: by 2002:a17:906:1614:b0:78d:4e5b:ffaa with SMTP id m20-20020a170906161400b0078d4e5bffaamr6453367ejd.455.1669189975225; Tue, 22 Nov 2022 23:52:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669189975; cv=none; d=google.com; s=arc-20160816; b=pelz4nKjXPeo6p51hV0wuiY3NPDppLwDPWmArQiC4YcFVbyz5vL/2j7fowgnSRO6EE e/Y3+Okpto1+IuRrp/MtwD+cpwNtLis6QPhI+8uHH7+IKNdk/uoPkTyUl7yJivI+CLWx 0Mtfc/kUopxzxbItpBW9NtVnq7wzOiBFg/lbEnOFscoWZHoXwhk7DLoAjXRFki4GytDk jN2yP+4ytl0j53CRfAdHU8IV6akM0hw1JijXLAgScFd5vCXlIqLQ0AfjGE1j57xZYCdc vUpBxYfRFkw4SNVhfIEjsgnWvH6v05Brwt3xZ9jP8c3SLENtzy4SYYpCwPnx+QxHLH7B uCsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dxBfeAGPJSh5Y/5FKQg+M0y4cyLZHfyLwZKtosIJVD4=; b=yWzWu/c+qCLY4IVDnJrlvyC2lu9wf1SUt/fwg5E9pUZbGZaF2+Bw6sEuDlipUGwLdS G4vtSnbuH4JbMvUxfyYg3pE/etea3kudzvCZt4EOQgX2gbwh1V9VE+ESY9MH2LobZgOs 3kRaENrCCe/ACFPycopJwrYTb5asXdhwdqDoUtZv49ndD92cfn/GwKL5EPDdLSHnpZtX WlP6fgV2nHuUEhKQ9vbLQe8OxIqRyfb2QYVYooxuaBuuwtngd8A3FpnxsTL5958xMnqH E5uu4YGJ2hOHHQnukyZ8VEJV+Epq8xT4Syfwr5v2GdVxfaAREUY4iNnZfGsS6ScqR8Ly C19Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hvohjQO8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Since the existing register, RETRY_TIMER_REG is not used anywhere, it is safe to use the new name. Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 9d96ac71b27f..7fe928b82753 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -33,7 +33,8 @@ enum { REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4, REG_UFS_LOCAL_PORT_ID_REG = 0xC8, REG_UFS_PA_ERR_CODE = 0xCC, - REG_UFS_RETRY_TIMER_REG = 0xD0, + /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */ + REG_UFS_PARAM0 = 0xD0, REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8, REG_UFS_CFG1 = 0xDC, REG_UFS_CFG2 = 0xE0, From patchwork Wed Nov 23 07:48:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24773 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2649213wrr; Tue, 22 Nov 2022 23:53:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf76qIwRM+AYq24StvEN/JcyRbId8D4+cw2bWV6BK5gayRloAXcfucmEYy8HJl0nUClewid6 X-Received: by 2002:a17:906:2e83:b0:78d:b3f0:b5c0 with SMTP id o3-20020a1709062e8300b0078db3f0b5c0mr23421193eji.141.1669189996326; Tue, 22 Nov 2022 23:53:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669189996; cv=none; d=google.com; s=arc-20160816; b=oHcq7HC+Hve5SNx14kdVgWHZnj49qpUdbd86YeWAjDSVSX2s5Q8aoI6IM5Bnw4A1T4 A5Mpf/xM4nVzeWZ7eSgmNGIXg+pv+ukQbsekIbf4r1Ky0aCku+hMZPEICvgDs1HrYAsM 2oJp0MgQFo0bidkBMDA6rzvAXjLVGixiyN+CyVYwcuZvq4Kls4hrNcO9gdi7fE4WZF45 b4fJhPplw9VMDHvcM/R2F1HGMnLicSJJPHk3G8CZlw47gmMWUqoE5XqDl7nS/kPJd+gI SLo2+xPwDOXABW3wYzEwL28qgFvnym7X6aQlYQVAQeqWjl55F7QFhJxe/8vdB5om504h aJ0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=I2Xd0gDlZp0b1F7R46Bn1beu0377yVMDIxRd9gxYrRE=; b=sAhBXWrxw6+Xr0s7pdIBfcLJn7ngfLLpieXDoKQeEXGZTtqvOgN2K6hQt1jPTBW5zV FU7uCcfpYvFFUTax7Odfcbf8OND315vB/K2/eWht3o/cO2puodY52U0xUf6aXktygO/d 5E/xtA2PA+6evtIq/ZkpVaRUghV5OaxM+Q7kJlBNXEI5hKh4WF4bhh3R/S5bjEeSsc4f mQCqNI3YemveABID62rayqRfNzBhz64Zy6qXkc9OhiW6Omhwp62x/Wt4zojjLvp6+zbM i9A6jTmoW7CP5OWVhizslzDaEbxaGAM1avxQiGW35wkPVErP2UA6ff9bVhbw7VQcN3a7 PLcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j4a2IZ4M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/core/ufshcd-priv.h | 6 ++++++ include/ufs/ufshcd.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index f68ca33f6ac7..37260c1af9f0 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -226,6 +226,12 @@ static inline void ufshcd_vops_config_scaling_param(struct ufs_hba *hba, hba->vops->config_scaling_param(hba, p, data); } +static inline void ufshcd_vops_reinit_notify(struct ufs_hba *hba) +{ + if (hba->vops && hba->vops->reinit_notify) + hba->vops->reinit_notify(hba); +} + extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; /** diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 9f28349ebcff..09927a011a84 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -297,6 +297,7 @@ struct ufs_pwr_mode_info { * @config_scaling_param: called to configure clock scaling parameters * @program_key: program or evict an inline encryption key * @event_notify: called to notify important events + * @reinit_notify: called to notify UFS core reinit */ struct ufs_hba_variant_ops { const char *name; @@ -335,6 +336,7 @@ struct ufs_hba_variant_ops { const union ufs_crypto_cfg_entry *cfg, int slot); void (*event_notify)(struct ufs_hba *hba, enum ufs_event_type evt, void *data); + void (*reinit_notify)(struct ufs_hba *); }; /* clock gating state */ From patchwork Wed Nov 23 07:48:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2649269wrr; Tue, 22 Nov 2022 23:53:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf6R+O7LL7YurguouxQD4hHotLF9Ko1nu7vm/NwdJ3XIXjhZmhxVP5+ZdsHTXXXsIoe3UqVA X-Received: by 2002:a63:e907:0:b0:477:5e25:baf4 with SMTP id i7-20020a63e907000000b004775e25baf4mr14114197pgh.544.1669190007603; Tue, 22 Nov 2022 23:53:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669190007; cv=none; d=google.com; s=arc-20160816; b=j31F81pgm5XFAXdMkKvrJL2/qewWl+25RqQh2ELIjAZBZ8txWkAH/8kjQ0TgFEf3H0 mhP5jDcupk+xgZqZwZ+xng77yRyVEC1OWBGoGEC1RHFIuPj5qX0LeMRNqau8uk4QjZEx Yg/4w9wvRYabwZlK4FknHaE4P320Rq0XO+T6RtVqiO9mCtnz7BUnIiT+tZLu55WmzabA IUZdqEigoJW2jwq2ll6Bu3Bw76ZKUKRVFLCZRWawk4W9HPoBy9pSuOReHxPqjxtz4hD/ LiJ08NmgMuLWF3fgoi3w5NxSTqnAsxvyntzLp5ER6Dp1JVEc5PZlKu03LoaHLhCgxvei hDcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/Xs9R7SPzAS5pOWZNCxb7jU9uBO2AEwyHCVEvHAOYro=; b=U2nZ6dSavTpzhX27X/UpCvyqOdBuncYqHHzLye0rRpP7guUSx04sRAU0I0DG1L/pR7 B+iGlCmDUWCbpP+AJ6BEzF9x5Rs5X4EMnbcwQYWW1b20ud3P9WbaTTx7PORgDp8D9nJ+ GGT6k/KlFDM1cXSUyw6QwmJBNNREf75CPsdGZdAW0xHe/SLnmxyCxSvqiHZG7hZq64Ze C0BoK06BU5g+1+srIBBve7q89ks9Q/pf854Tf413ojmQTqSJtG2NQwiwIPvBX5/EcMDO fNPs7iGG2ivqGeErNNjzZDY66uJigijnH3AnPtmbegjKT/MfnunwW+yTZcMjBuesGq2z ideQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xnIcVBVV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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So add support for that in UFS core by introducing a new quirk (UFSHCD_CAP_REINIT_AFTER_MAX_GEAR_SWITCH) and doing the reinitialization, if the quirk is enabled by the controller driver. Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/core/ufshcd.c | 63 +++++++++++++++++++++++++++++---------- include/ufs/ufshcd.h | 6 ++++ 2 files changed, 53 insertions(+), 16 deletions(-) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 7256e6c43ca6..c44ffb63d48f 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -8161,27 +8161,18 @@ static int ufshcd_add_lus(struct ufs_hba *hba) return ret; } -/** - * ufshcd_probe_hba - probe hba to detect device and initialize it - * @hba: per-adapter instance - * @init_dev_params: whether or not to call ufshcd_device_params_init(). - * - * Execute link-startup and verify device initialization - */ -static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) { int ret; - unsigned long flags; - ktime_t start = ktime_get(); hba->ufshcd_state = UFSHCD_STATE_RESET; ret = ufshcd_link_startup(hba); if (ret) - goto out; + return ret; if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) - goto out; + return ret; /* Debug counters initialization */ ufshcd_clear_dbg_ufs_stats(hba); @@ -8192,12 +8183,12 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) /* Verify device initialization by sending NOP OUT UPIU */ ret = ufshcd_verify_dev_init(hba); if (ret) - goto out; + return ret; /* Initiate UFS initialization, and waiting until completion */ ret = ufshcd_complete_dev_init(hba); if (ret) - goto out; + return ret; /* * Initialize UFS device parameters used by driver, these @@ -8206,7 +8197,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) if (init_dev_params) { ret = ufshcd_device_params_init(hba); if (ret) - goto out; + return ret; } ufshcd_tune_unipro_params(hba); @@ -8227,11 +8218,51 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) if (ret) { dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +/** + * ufshcd_probe_hba - probe hba to detect device and initialize it + * @hba: per-adapter instance + * @init_dev_params: whether or not to call ufshcd_device_params_init(). + * + * Execute link-startup and verify device initialization + */ +static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) +{ + ktime_t start = ktime_get(); + unsigned long flags; + int ret; + + ret = ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; + + if (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) { + /* Reset the device and controller before doing reinit */ + ufshcd_device_reset(hba); + ufshcd_hba_stop(hba); + ufshcd_vops_reinit_notify(hba); + ret = ufshcd_hba_enable(hba); + if (ret) { + dev_err(hba->dev, "Host controller enable failed\n"); + ufshcd_print_evt_hist(hba); + ufshcd_print_host_state(hba); goto out; } - ufshcd_print_pwr_info(hba); + + /* Reinit the device */ + ret = ufshcd_device_init(hba, init_dev_params); + if (ret) + goto out; } + ufshcd_print_pwr_info(hba); + /* * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) * and for removable UFS card as well, hence always set the parameter. diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 09927a011a84..d3e8aa7a4207 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -595,6 +595,12 @@ enum ufshcd_quirks { * auto-hibernate capability but it's FASTAUTO only. */ UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, + + /* + * This quirk needs to be enabled if the host controller needs + * to reinit the device after switching to maximum gear. + */ + UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, }; enum ufshcd_caps { From patchwork Wed Nov 23 07:48:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2649442wrr; Tue, 22 Nov 2022 23:54:09 -0800 (PST) X-Google-Smtp-Source: AA0mqf5/YZGWcHkzo0iPE2gvfwm1lxk23QvXGuYOQIXbPcxSlW6r1v0A24dkegCw+c7ZlUMKCNPS X-Received: by 2002:a17:90a:e512:b0:218:9685:81fe with SMTP id t18-20020a17090ae51200b00218968581femr20725601pjy.190.1669190048875; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ij7-20020a170902ab4700b001893efd3e00si1323328plb.49.2022.11.22.23.53.56; Tue, 22 Nov 2022 23:54:08 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q4uifVNU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236398AbiKWHwH (ORCPT + 99 others); Wed, 23 Nov 2022 02:52:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236373AbiKWHvX (ORCPT ); Wed, 23 Nov 2022 02:51:23 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B6AAFAE90 for ; Tue, 22 Nov 2022 23:50:16 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id io19so15926490plb.8 for ; Tue, 22 Nov 2022 23:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jQW21UMpMMT39kQGkUZ44Bi2KAiI76Uffz4R9s7ZIY4=; b=Q4uifVNUG8xLZiw0nKZzqWhlsFQVjN7R7zmwgdRS/fTSn0Pz18mv37YJD39o+JlZ+U YX50U9RmFIiBE5gaK+qWmu8dehcTfKoU1BOe+NxgY/P8qv4PehJ3qfZDfW4HwQ/uSNLF SO5irDbKFTLjuwkrCMMdtgUjo/xb1StQ14ri1Bxv1UkA/bIwjVqyt+gMUVpvegQ+Peff qG4EAibX1FxdFxy8A92f6uSiv92YFS5FM3PH+5SGqa7OLIVqu/yGOPBW3106ZA1Dj0nN or6T2UMyGk7jCA89uhNo+9K4YwS8Q70+I2BoLGhEhoS19d02r0QG25cSU+dfJA25+76c lyFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jQW21UMpMMT39kQGkUZ44Bi2KAiI76Uffz4R9s7ZIY4=; b=XawdXNDNiiIuX+ymI08p49Quae3LrqBEpi+0xzqrXWHD4BuMxnL2hdOWumuGEbN1tn yFGCgV+L88JDQIJRq/wZofa6hfKN9XrYdj7Mj1ujLUn26yr1yRWYhScPe9idg2I0CRiU fnJJ3Y7mpY9eW7lmRm5HUaYKYfB3esGlioyVPQfqxt1axwa555MIFbRqycBLnvt6ICE6 xgytyCv6NwwyVAsDDa/gAvVYpw7OCuwhvoOGXHHozKgrGnayKToa36Asorw5CxYgjU9v dvKZ3o5xkxr+aV15WjZfnrWKE0BN2moUReTVm7PjkPFqZMIiVtLp2Wbgr2EY6EtJZWT6 fgpA== X-Gm-Message-State: ANoB5plDxj6R0rIP0SCKQWI5DKaSeXDyRuxSPiWIKJ/zkcul+3ERHK4G SsHylPh/KcBlI+cLhVyt73an X-Received: by 2002:a17:90a:d811:b0:213:aa8:dda with SMTP id a17-20020a17090ad81100b002130aa80ddamr30077911pjv.111.1669189815878; Tue, 22 Nov 2022 23:50:15 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:15 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 17/20] scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear Date: Wed, 23 Nov 2022 13:18:23 +0530 Message-Id: <20221123074826.95369-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750272624685074560?= X-GMAIL-MSGID: =?utf-8?q?1750272624685074560?= In the preparation of adding support for new gears, let's move the logic that finds the gear for each platform to a new function. This helps with code readability and also allows the logic to be used in other places of the driver in future. While at it, let's make it clear that this driver only supports symmetric gear setting (hs_tx_gear == hs_rx_gear). Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 38e2ed749d75..919b6eae439d 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -278,6 +278,25 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba) return 0; } +static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + if (host->hw_ver.major == 0x1) { + /* + * HS-G3 operations may not reliably work on legacy QCOM + * UFS host controller hardware even though capability + * exchange during link startup phase may end up + * negotiating maximum supported gear as G3. + * Hence downgrade the maximum supported gear to HS-G2. + */ + return UFS_HS_G2; + } + + /* Default is HS-G3 */ + return UFS_HS_G3; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -692,19 +711,8 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, ufshcd_init_pwr_dev_param(&ufs_qcom_cap); ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; - if (host->hw_ver.major == 0x1) { - /* - * HS-G3 operations may not reliably work on legacy QCOM - * UFS host controller hardware even though capability - * exchange during link startup phase may end up - * negotiating maximum supported gear as G3. - * Hence downgrade the maximum supported gear to HS-G2. - */ - if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_tx_gear = UFS_HS_G2; - if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2) - ufs_qcom_cap.hs_rx_gear = UFS_HS_G2; - } + /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ + ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, dev_max_params, From patchwork Wed Nov 23 07:48:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24776 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2649485wrr; Tue, 22 Nov 2022 23:54:20 -0800 (PST) X-Google-Smtp-Source: AA0mqf53UoM0H+fe6hO3xv6u/vB18ea7GcPgWzkYpR7j5QhskhXaxaZcnfSvx44SYsdJU8SOnZP6 X-Received: by 2002:a63:110e:0:b0:477:86c1:640d with SMTP id g14-20020a63110e000000b0047786c1640dmr7750362pgl.223.1669190060108; Tue, 22 Nov 2022 23:54:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669190060; cv=none; d=google.com; s=arc-20160816; b=wx+XawPIYn1rkKgVGkITshKvQEoVpoAP/Sz8TYzdR27u2pirY0+eisKS424dEkY8t3 4d1FaM/erlklLDWEG9RI5BMjFvZ/QCxq5k8pUmbfzPx3mmd9FP+UafuIGQmpm0jDar76 KfcZwUKGFM39DmAgiCnZjLUkrSSYSKqgNKEAVCs7KTCo3BO0R85DrQLK0+iUaPEdShgT Ita3nuMV/ZR9Hpw1IZPWeIrbnZHQ+RD+WcSzpthIg6yRq9BHXJiu5WMCC1xOSIMnxgP7 2FOyISDf66nmtzE3ZQXF6vThRfq75W+x1ta51axI64BHeS3W7ef1vsgC3JHnQKlvBCvs qXaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Uk4luKF8t4ifNKen4Qh4OvqAisGjZ8ae5pMGODayTWw=; b=CIr4O2wVcyZ0LMNoBDTLTSiHuUp040rYvA3PLpo3YlZZqjqoZRs4qKzoQoyiolESJq QSF48TYjGs7BypldBXgiaHN9nJDBce7N7BYiKVy/xU3MJOn3PVs3ZQsSmejacpoEEKH4 CF5RgwWqudVM/dV+f6EuXVWN1JdnxVqzkmCuoz9Jbtta8x4e0jIYTHXkjBb9NKgJr7As xGTVmrpVTVmNEUU5JyfrAKnAmZDEN7QzqHjuPp5eW11Zrelqdr1/2HxveMfJ37cOIuND 8r+Wu/kGlocmfKGVy4VGgPDURiMvndM0HuI+zHEPIL4BR5S8MIQnJBHBFbQK5FlIdw/T FDiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N1BMzP3f; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Hence, add support for it by enabling the UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH quirk, implementing reinit_notify() callback and using the agreed gear speed for setting the PHY mode. Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 26 ++++++++++++++++++++++---- drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 919b6eae439d..3efef2f36e69 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -302,7 +302,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct phy *phy = host->generic_phy; int ret; - bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B; /* Reset UFS Host Controller and PHY */ ret = ufs_qcom_host_reset(hba); @@ -310,9 +309,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) dev_warn(hba->dev, "%s: host reset returned %d\n", __func__, ret); - if (is_rate_B) - phy_set_mode(phy, PHY_MODE_UFS_HS_B); - /* phy initialization - calibrate the phy */ ret = phy_init(phy); if (ret) { @@ -321,6 +317,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) return ret; } + phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); + /* power on phy - start serdes and phy's power and clocks */ ret = phy_power_on(phy); if (ret) { @@ -723,6 +721,9 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, return ret; } + /* Use the agreed gear */ + host->hs_gear = dev_req_params->gear_tx; + /* enable the device ref clock before changing to HS mode */ if (!ufshcd_is_hs_mode(&hba->pwr_info) && ufshcd_is_hs_mode(dev_req_params)) @@ -836,6 +837,9 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); } + + if (host->hw_ver.major > 0x3) + hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; } static void ufs_qcom_set_caps(struct ufs_hba *hba) @@ -1044,6 +1048,12 @@ static int ufs_qcom_init(struct ufs_hba *hba) dev_warn(dev, "%s: failed to configure the testbus %d\n", __func__, err); + /* + * Power up the PHY using the minimum supported gear (UFS_HS_G2). + * Switching to max gear will be performed during reinit if supported. + */ + host->hs_gear = UFS_HS_G2; + return 0; out_variant_clear: @@ -1410,6 +1420,13 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, } #endif +static void ufs_qcom_reinit_notify(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + phy_power_off(host->generic_phy); +} + /* * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations * @@ -1433,6 +1450,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { .device_reset = ufs_qcom_device_reset, .config_scaling_param = ufs_qcom_config_scaling_param, .program_key = ufs_qcom_ice_program_key, + .reinit_notify = ufs_qcom_reinit_notify, }; /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 7fe928b82753..4b00c67e9d7f 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -217,6 +217,8 @@ struct ufs_qcom_host { struct reset_controller_dev rcdev; struct gpio_desc *device_reset; + + u32 hs_gear; }; static inline u32 From patchwork Wed Nov 23 07:48:25 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id j3-20020a170902da8300b00186a2d376afsi1686700plx.273.2022.11.22.23.54.57; Tue, 22 Nov 2022 23:55:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BOIqJRhD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236433AbiKWHwU (ORCPT + 99 others); Wed, 23 Nov 2022 02:52:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236406AbiKWHv1 (ORCPT ); Wed, 23 Nov 2022 02:51:27 -0500 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5853DFBAAC for ; Tue, 22 Nov 2022 23:50:28 -0800 (PST) Received: by mail-pg1-x530.google.com with SMTP id 62so16063948pgb.13 for ; Tue, 22 Nov 2022 23:50:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=glMEmrKRq4os3IrGzZuvFW519vUHu5A1N8n6PQVGzlQ=; b=BOIqJRhDIjAKXMdP0E72f+a3Mm553ME26QYgvjzRlnw5V6BDIRXLMaF1se86tGbYQB ZKJSBLv7ClSBzIHeOGPty5hmKbwaBrkAZyu5V7cAXRjG5/gkyz6zJVwZsudzNbC9l4sX xGxB/hxYu0PBYiO+yoCyjYeMiJMGg99bn5EY+aEng7GPz83FRjYFs/kI3QkayzRoFvhW wfs9iSr4xEj+gPjd1lE6V0ENFCIGqFFvmzEws69pHbHcVtxSZqsQQo4soZY0JUzY4sMe KDFqmpqix67JN0Z5Q/X7RLjj2iVbNpbHIil8wCaS62qxF0o21h88N9YOigHsix7vCpN1 62LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=glMEmrKRq4os3IrGzZuvFW519vUHu5A1N8n6PQVGzlQ=; b=76pRlo23PA1x+2f7TPyGoeQFZ/r11kAO2faWmzC4BVHgAX/PAU/cgEg00grhH0vcJK EpxK2zQhKa9z4qbMUANPu1gWdSV3hq/Q6MNYo3mm09iMWNw79SZuT+Tg1xtk33d2jMVj qpP3+ud8g06mobGUBQAcmsUnhYHAb2qLFqFB4c/WWe/lVeIk8V+J1SiauZ2G5/8GYifT K9lRwBJbIA2u9AGyd4lBQli8zX2z3vw7ePGsgDa8K16VzTVGKNK9fqiqFIEuBU6mX1rD Aufml0jT5wbnbybvkmmEmwLdNsLntjuRZBbgJUOGrdxGt300n9binyGDuTnw16ozWlD7 9Zag== X-Gm-Message-State: ANoB5pndQcmLKJmNMTzzpa22LC/v8SJWIFnNJp2mGA7Hp5j1XD0F/d0z tJ5rNLGJIklWDT4biIcLU1fX X-Received: by 2002:a63:5359:0:b0:46f:3dfb:87e1 with SMTP id t25-20020a635359000000b0046f3dfb87e1mr9010367pgl.290.1669189827640; Tue, 22 Nov 2022 23:50:27 -0800 (PST) Received: from localhost.localdomain ([117.202.191.0]) by smtp.gmail.com with ESMTPSA id s16-20020a170902a51000b001869f2120a5sm13334059plq.34.2022.11.22.23.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 23:50:26 -0800 (PST) From: Manivannan Sadhasivam To: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, vkoul@kernel.org Cc: quic_cang@quicinc.com, quic_asutoshd@quicinc.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org, dmitry.baryshkov@linaro.org, ahalaney@redhat.com, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 19/20] scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms Date: Wed, 23 Nov 2022 13:18:25 +0530 Message-Id: <20221123074826.95369-20-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> References: <20221123074826.95369-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750272689065923688?= X-GMAIL-MSGID: =?utf-8?q?1750272689065923688?= Starting from Qcom UFS version 4.0, vendor specific REG_UFS_PARAM0 register can be used to determine the maximum gear supported by the controller. Reviewed-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/ufs/host/ufs-qcom.c | 2 ++ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 3efef2f36e69..607fddb7b4c3 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -291,6 +291,8 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) * Hence downgrade the maximum supported gear to HS-G2. */ return UFS_HS_G2; + } else if (host->hw_ver.major >= 0x4) { + return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); } /* Default is HS-G3 */ diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 4b00c67e9d7f..dd3abd23ec22 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -94,6 +94,10 @@ enum { #define TMRLUT_HW_CGC_EN BIT(6) #define OCSC_HW_CGC_EN BIT(7) +/* bit definitions for REG_UFS_PARAM0 */ +#define MAX_HS_GEAR_MASK GENMASK(6, 4) +#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x)) + /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */ #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */ From patchwork Wed Nov 23 07:48:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 24778 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2649864wrr; Tue, 22 Nov 2022 23:55:26 -0800 (PST) X-Google-Smtp-Source: AA0mqf7jnUZ8JMTPiGvtcQvTk/Q8MCP29+9Cci1YEspUh4QIBIggFNq0qQqndwDIp5FrNvpR1/Nm X-Received: by 2002:a17:903:486:b0:186:95ca:1e4c with SMTP id jj6-20020a170903048600b0018695ca1e4cmr8180876plb.13.1669190126257; Tue, 22 Nov 2022 23:55:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669190126; cv=none; d=google.com; s=arc-20160816; b=yumMmobT5kDgTiqUy5NJXLD232aBwxiIYzVJrKmILEpnfs5WTeu8dG5iEhGDh4PKJh 3O/YjMlGxzcXuOA7CaagF/946xOseKxxYfB031Z3VuHhm1YeR/AV/fHfFLR8b88gvqoU 4sRsgfIvHYkcbhSaMV3ATGLAEX8o9UZ41u4mTmlSkZnYJAIjtwr0xOKEJ3NteYpSsHJO RAqiAuEuQdh/SWS4XcFkmK83hDDv1EEtcT7s/PUJi0nTFdY2pD7vKkxuAZxf10fr/PC2 mUcHAptCSYdNSsRBRw1jzKh04KJn8Yy3KKONdR8kbkx+qkhfdxYDCARTAR82o04SDSOr cWBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6pljquG0hkdcBPdXIDtkq1v6aN8iyQB1w4S/2qg/cek=; b=mSFnJnPcIEQ6+KZJeciSGRsO4jG86bIqVL7Hhk2nsESndSCMQnpgGqEezr4qvRbxEq cAnP2YgmgRhtAkIR0XF6y8/oEv9rYBbbVJEvppSXCzBt+R5vgLftiw81oefykW0zSEPP EIivk9ZeMoPlzfKCLNk4DJ80frHbgaOTlT52CQyP/nP36aMM02Q7lDVlEL+oE/PHDQIG 0RbIG4FtgjvhIGRgq1/5VmeOwzbXlZXTTsz+q34I5swrba/iwS7GLh+B71oUapxOx06B sRfKU6DTbMSYbIccuzdv6Ljkk8ffFvV8RucW2BAnf/REns0rPW7i8MyOUvH6oFnDeejy Fz2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=riPHLLSP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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I'd like to step up to maintain the driver and its binding. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..149fd6daf52b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21097,6 +21097,14 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/ufs/host/ufs-mediatek* +UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER QUALCOMM HOOKS +M: Manivannan Sadhasivam +L: linux-arm-msm@vger.kernel.org +L: linux-scsi@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +F: drivers/ufs/host/ufs-qcom.c + UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER RENESAS HOOKS M: Yoshihiro Shimoda L: linux-renesas-soc@vger.kernel.org