From patchwork Tue Nov 22 15:53:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 24440 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2293290wrr; Tue, 22 Nov 2022 08:00:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf6FfGn+5Y2Gnm9ApZkLyloF512ocO4Ip3IE2MwIu9PFaOqrnngvj1xCYyCySkIgQCIcTzsn X-Received: by 2002:a63:1054:0:b0:42b:9219:d14e with SMTP id 20-20020a631054000000b0042b9219d14emr4746923pgq.176.1669132838106; Tue, 22 Nov 2022 08:00:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669132838; cv=none; d=google.com; s=arc-20160816; b=JRnimxCZa8sVyScVVXoG6muV2j9Q3rHfjSGVj7iLRde49RRJo/KAYTbGePEeuJ+ZMS ce09Pzz5JekCsZ7/35LazCCKrW7W34ogKj1QpItfANLYMXjUJ07cIXcfKo8fF44AiFsS hoFLVZ/OneerFhGJaMOdZAfD4pvCLkjIPzzTC9Y6cxz8Ca7HJR+E6MWJIPOyEMfscgb6 BUDIDlzmJpKCjhrt4pizhD/FLILgXRswerY5xk+wFk21kd9hlS54suSIeAMuXYsg3A2r dvXqyt9Fovgkq6RYhm2b6KVXakCbxl0X7s2KQTChTfEko3d1jaGehQc3hWIEBADw+g13 tKpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=agyc7s6h16IO6Q24kCBwX6rl76erMQSODes1pYlgfmg=; b=ZdHokyRfO1KoRdBdEThibkx7+X3LxXV8aTVfTC8XKbc1aYMmJmj53C/EqcNmAu9AkJ EoBBHPbyxYNxFZNTqXAJTu0Wek3BfjaepIpJpFIYtAbirgXGOGZQi50dRKZ+8hwrBAGT KQxvG10u98ZeVsjLh/oq31yZSSQoJ7HvS0wFbaaLfPomUl38d3XRX4/GBwdUitB0uMt9 pLIIvMQMw/Fk5VkOeYr89F6PX7hy5SSoKDnEYI1ckdsbp0uOVOZqvp7nTc/+CJWcQqyn ICs19yZHV3VjCeuor6hTsvvL8opwwqozcUJ5yeKxahBolAAt7wkv+Nhku9FeaKTRMm5O JFSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kvgOBGhV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 2-20020a630b02000000b004498b9c8d34si14954423pgl.682.2022.11.22.08.00.23; Tue, 22 Nov 2022 08:00:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kvgOBGhV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233942AbiKVPxd (ORCPT + 99 others); Tue, 22 Nov 2022 10:53:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233626AbiKVPx3 (ORCPT ); Tue, 22 Nov 2022 10:53:29 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BB3E48779; Tue, 22 Nov 2022 07:53:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669132408; x=1700668408; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YUJ7EdYfUOaMRwptVpLuSUm6x5AoT6ZUjcLdR6MstiY=; b=kvgOBGhVXFJVFRcBO54KKqM/RGEUdFFFFxBpezx7FOXgnyg0ew0q/Qp9 2sV586QTDlHRV9xxYAgBIcnMWV5hAI3B1O+Y9wWzADOJzQTgnNhHDyA/u 3lZNVZYDN9bhsI5u31pP64xXb82ypEgm/C+n/hwE9IJBtUv3uy1lYaDVy axBlJkSjNqoBGXFQ0HERl10eSrBlxhe+SYba8hmnUpf5XCEnuhKE1QBWd fm+QnllWbcCIoJjgIz1GUJJ8aMZdiVm3VzYj1P3hCRSQaxWVljYVJqpHm TczU7eBHyCAseqmM0kEamdoyUD4srK8omwMstoGgvIk+nrZetiqzf9jrx Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="313877730" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="313877730" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 07:53:28 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="816142053" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="816142053" Received: from iweiny-mobl.amr.corp.intel.com (HELO localhost) ([10.209.130.75]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 07:53:27 -0800 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas Cc: Ira Weiny , Lukas Wunner , Alison Schofield , Vishal Verma , Jonathan Cameron , Gregory Price , "Li, Ming" , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [PATCH V2 1/2] PCI/DOE: Remove the pci_doe_flush_mb() call Date: Tue, 22 Nov 2022 07:53:23 -0800 Message-Id: <20221122155324.1878416-2-ira.weiny@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221122155324.1878416-1-ira.weiny@intel.com> References: <20221122155324.1878416-1-ira.weiny@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750212634766756725?= X-GMAIL-MSGID: =?utf-8?q?1750212634766756725?= From: Ira Weiny Each struct doe_mb is managed as part of the PCI device. They can't go away as long as the PCI device exists. pci_doe_flush_mb() was set up to flush the workqueue and prevent any further submissions to the mailboxes when the PCI device goes away. Unfortunately, this was fundamentally flawed. There was no guarantee that a struct doe_mb remained after pci_doe_flush_mb() returned. Therefore, the doe_mb state could be invalid when those threads waiting on the workqueue were flushed. Fortunately the current code is safe because all callers make a synchronous call to pci_doe_submit_task() and maintain a reference on the PCI device. For these reasons, pci_doe_flush_mb() will never be called while tasks are being processed and there is no use for it. Remove the dead code around pci_doe_flush_mb(). Signed-off-by: Ira Weiny --- drivers/pci/doe.c | 48 ++++------------------------------------------- 1 file changed, 4 insertions(+), 44 deletions(-) diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c index e402f05068a5..260313e9052e 100644 --- a/drivers/pci/doe.c +++ b/drivers/pci/doe.c @@ -24,10 +24,9 @@ /* Timeout of 1 second from 6.30.2 Operation, PCI Spec r6.0 */ #define PCI_DOE_TIMEOUT HZ -#define PCI_DOE_POLL_INTERVAL (PCI_DOE_TIMEOUT / 128) +#define PCI_DOE_POLL_INTERVAL 8 -#define PCI_DOE_FLAG_CANCEL 0 -#define PCI_DOE_FLAG_DEAD 1 +#define PCI_DOE_FLAG_DEAD 0 /** * struct pci_doe_mb - State for a single DOE mailbox @@ -53,15 +52,6 @@ struct pci_doe_mb { unsigned long flags; }; -static int pci_doe_wait(struct pci_doe_mb *doe_mb, unsigned long timeout) -{ - if (wait_event_timeout(doe_mb->wq, - test_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags), - timeout)) - return -EIO; - return 0; -} - static void pci_doe_write_ctrl(struct pci_doe_mb *doe_mb, u32 val) { struct pci_dev *pdev = doe_mb->pdev; @@ -82,12 +72,9 @@ static int pci_doe_abort(struct pci_doe_mb *doe_mb) pci_doe_write_ctrl(doe_mb, PCI_DOE_CTRL_ABORT); do { - int rc; u32 val; - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); - if (rc) - return rc; + msleep_interruptible(PCI_DOE_POLL_INTERVAL); pci_read_config_dword(pdev, offset + PCI_DOE_STATUS, &val); /* Abort success! */ @@ -278,11 +265,7 @@ static void doe_statemachine_work(struct work_struct *work) signal_task_abort(task, -EIO); return; } - rc = pci_doe_wait(doe_mb, PCI_DOE_POLL_INTERVAL); - if (rc) { - signal_task_abort(task, rc); - return; - } + msleep_interruptible(PCI_DOE_POLL_INTERVAL); goto retry_resp; } @@ -383,21 +366,6 @@ static void pci_doe_destroy_workqueue(void *mb) destroy_workqueue(doe_mb->work_queue); } -static void pci_doe_flush_mb(void *mb) -{ - struct pci_doe_mb *doe_mb = mb; - - /* Stop all pending work items from starting */ - set_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags); - - /* Cancel an in progress work item, if necessary */ - set_bit(PCI_DOE_FLAG_CANCEL, &doe_mb->flags); - wake_up(&doe_mb->wq); - - /* Flush all work items */ - flush_workqueue(doe_mb->work_queue); -} - /** * pcim_doe_create_mb() - Create a DOE mailbox object * @@ -450,14 +418,6 @@ struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset) return ERR_PTR(rc); } - /* - * The state machine and the mailbox should be in sync now; - * Set up mailbox flush prior to using the mailbox to query protocols. - */ - rc = devm_add_action_or_reset(dev, pci_doe_flush_mb, doe_mb); - if (rc) - return ERR_PTR(rc); - rc = pci_doe_cache_protocols(doe_mb); if (rc) { pci_err(pdev, "[%x] failed to cache protocols : %d\n", From patchwork Tue Nov 22 15:53:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 24441 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2293288wrr; Tue, 22 Nov 2022 08:00:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf6i2nXTtFxtzsFLo2khIieP+3prQSGEPqzxf7z59BKNMkbAYxhcsjSKdDj/XcdvYxMoRofg X-Received: by 2002:a17:903:300a:b0:188:f6c8:2ca9 with SMTP id o10-20020a170903300a00b00188f6c82ca9mr5199270pla.6.1669132838038; Tue, 22 Nov 2022 08:00:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669132838; cv=none; d=google.com; s=arc-20160816; b=zBMGLkYF+30fH1YlrrozAMg2t5l4BSCFJxkRSa//DjEvjJDQzAqbC0bU8A2FfISMLB Z6BbMnYaTl/QWemXsZLx07BBNSJqJmRCA6YdNZlyNxJEtms3KinOjbe38h0bP9fqDzC9 N1wadqbjUYt7poxqzXNR7zkhhEfbHtvmJJfVgZWFZbIyEkDYFyxdP8l2wQs0jbxWY/D9 ADhEsxYlkLssUEAYClirdNzk2N2f/dy+JTQjgeODpJicepp26zlreGu3M9g7jC7zpyOn ptQMDOu1QgzZQoWMuK+6I7pQN5HxmnTUwdGJ7ay1+189HJDpG+Bfj1GumPtrSC9NUeJV nhLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YmWhOaOi9HE5/O8RaSbXAnV96GJCY/JQstCoOxzkA1M=; b=kMXxxBcKolE0EFxnInWYkr2lrHOLngePLqJPFy5OF6QAH1PCKdm/TnKiBXbuHwdEJf v07GZC28D+mGEbAlc1BXZ2J/mrTqvrbhdWqHvx8Wh8Tyeeq/tB9tUgkm6VvbneWgx9Vu RMxu1m3flqM1SjQGiOamrX/MWWx2Nn3SiO7MylajLdPUq02dcE0S7ESe+tx6I6t5f605 v8wngEOxRqta5pM8aUN7K+G1+kH8pN3mcIPyiUdygJ6/zTunurCtCEcYct9s60oEP7BD bJhF5KBSUzKgXCxUCMK9IYe6na5wKW5eDhqMBNzzJEsKfCs9ZlbzjnXGhxgI+yUJ/vBE JgkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=P9dnHHFv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id pg16-20020a17090b1e1000b002009ed52bf6si15700801pjb.19.2022.11.22.08.00.23; Tue, 22 Nov 2022 08:00:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=P9dnHHFv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233099AbiKVPxh (ORCPT + 99 others); Tue, 22 Nov 2022 10:53:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232516AbiKVPxb (ORCPT ); Tue, 22 Nov 2022 10:53:31 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D638749085; Tue, 22 Nov 2022 07:53:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1669132409; x=1700668409; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zR92HT6l0wORMTKoYqbinxwelXlw+3flVIh/hVHRHdg=; b=P9dnHHFvK6vv4ILF/GI95bIT+ihkheCXogOkXRWkyog4DW9L9aD15b// YmvXYNT7LKNJHu6otAkdyxgqD2zFaGSFaacm2K66E1+APQzIOYso9lZI3 s/HrjUEGV3GckxpzNpsfk+Qqb7uWa48YL8cyHvj14LJ5Ck99vkA1Ak6ah +mmJd0BrTglWeWzuugoI9LczNOjiTYv9h9Vule0Am5eqPU9DFZZoIxDSE 5raZ3rLPp7AFMlhSoEe/1TgTKJQbSzv8Lc3xeuxKIfNP9Tn49AjuDPlw+ kxviKpbsJr4F+6IsvmoZwB3A2mUqRAEsXMJng3mxZxDW+H3AGe+FmkkDr Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="313877733" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="313877733" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 07:53:29 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10539"; a="816142057" X-IronPort-AV: E=Sophos;i="5.96,184,1665471600"; d="scan'208";a="816142057" Received: from iweiny-mobl.amr.corp.intel.com (HELO localhost) ([10.209.130.75]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 07:53:28 -0800 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas Cc: Ira Weiny , Gregory Price , Jonathan Cameron , "Li, Ming" , Lukas Wunner , Alison Schofield , Vishal Verma , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: [PATCH V2 2/2] PCI/DOE: Remove asynchronous task support Date: Tue, 22 Nov 2022 07:53:24 -0800 Message-Id: <20221122155324.1878416-3-ira.weiny@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221122155324.1878416-1-ira.weiny@intel.com> References: <20221122155324.1878416-1-ira.weiny@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750212635115733927?= X-GMAIL-MSGID: =?utf-8?q?1750212635115733927?= From: Ira Weiny Gregory Price and Jonathan Cameron reported a bug within pci_doe_submit_task().[1] The issue was that work item initialization needs to be done with either INIT_WORK_ONSTACK() or INIT_WORK() depending on how the work item is allocated. Initially, it was anticipated that DOE tasks were going to need to be submitted asynchronously and the code was designed thusly. Many alternatives were discussed to fix the work initialization issue.[2] However, all current users submit tasks synchronously and this has therefore become an unneeded maintenance burden. Remove the extra maintenance burden by replacing asynchronous task submission with a synchronous wait function.[3] [1] https://lore.kernel.org/linux-cxl/20221014151045.24781-1-Jonathan.Cameron@huawei.com/T/#m88a7f50dcce52f30c8bf5c3dcc06fa9843b54a2d [2] https://lore.kernel.org/linux-cxl/Y3kSDQDur+IUDs2O@iweiny-mobl/T/#m0f057773d9c75432fcfcc54a2604483fe82abe92 [3] https://lore.kernel.org/linux-cxl/Y3kSDQDur+IUDs2O@iweiny-mobl/T/#m32d3f9b208ef7486bc148d94a326b26b2d3e69ff Reported-by: Gregory Price Reported-by: Jonathan Cameron Suggested-by: Dan Williams Suggested-by: "Li, Ming" Signed-off-by: Ira Weiny --- Changes from V1: Dan Williams: Use mutex_lock_interruptible() Adjust comment to lock the doe_mb structure not the code Adjust the locking based on the new series which eliminated PCI_DOE_FLAG_CANCEL. Thanks to Dan for the bulk of the patch. Thanks to Ming for pointing out the need for a lock to prevent more than 1 task from being processed at a time. --- drivers/cxl/core/pci.c | 16 ++------- drivers/pci/doe.c | 75 +++++++++++++---------------------------- include/linux/pci-doe.h | 10 +----- 3 files changed, 28 insertions(+), 73 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 9240df53ed87..58977e0712b6 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -490,21 +490,14 @@ static struct pci_doe_mb *find_cdat_doe(struct device *uport) CXL_DOE_TABLE_ACCESS_TABLE_TYPE_CDATA) | \ FIELD_PREP(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, (entry_handle))) -static void cxl_doe_task_complete(struct pci_doe_task *task) -{ - complete(task->private); -} - struct cdat_doe_task { u32 request_pl; u32 response_pl[32]; - struct completion c; struct pci_doe_task task; }; #define DECLARE_CDAT_DOE_TASK(req, cdt) \ struct cdat_doe_task cdt = { \ - .c = COMPLETION_INITIALIZER_ONSTACK(cdt.c), \ .request_pl = req, \ .task = { \ .prot.vid = PCI_DVSEC_VENDOR_ID_CXL, \ @@ -513,8 +506,6 @@ struct cdat_doe_task cdt = { \ .request_pl_sz = sizeof(cdt.request_pl), \ .response_pl = cdt.response_pl, \ .response_pl_sz = sizeof(cdt.response_pl), \ - .complete = cxl_doe_task_complete, \ - .private = &cdt.c, \ } \ } @@ -525,12 +516,12 @@ static int cxl_cdat_get_length(struct device *dev, DECLARE_CDAT_DOE_TASK(CDAT_DOE_REQ(0), t); int rc; - rc = pci_doe_submit_task(cdat_doe, &t.task); + rc = pci_doe_submit_task_wait(cdat_doe, &t.task); if (rc < 0) { dev_err(dev, "DOE submit failed: %d", rc); return rc; } - wait_for_completion(&t.c); + if (t.task.rv < sizeof(u32)) return -EIO; @@ -554,12 +545,11 @@ static int cxl_cdat_read_table(struct device *dev, u32 *entry; int rc; - rc = pci_doe_submit_task(cdat_doe, &t.task); + rc = pci_doe_submit_task_wait(cdat_doe, &t.task); if (rc < 0) { dev_err(dev, "DOE submit failed: %d", rc); return rc; } - wait_for_completion(&t.c); /* 1 DW header + 1 DW data min */ if (t.task.rv < (2 * sizeof(u32))) return -EIO; diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c index 260313e9052e..41c7bf5794a5 100644 --- a/drivers/pci/doe.c +++ b/drivers/pci/doe.c @@ -18,7 +18,6 @@ #include #include #include -#include #define PCI_DOE_PROTOCOL_DISCOVERY 0 @@ -39,7 +38,7 @@ * @cap_offset: Capability offset * @prots: Array of protocols supported (encoded as long values) * @wq: Wait queue for work item - * @work_queue: Queue of pci_doe_work items + * @lock: Lock state of doe_mb during task processing * @flags: Bit array of PCI_DOE_FLAG_* flags */ struct pci_doe_mb { @@ -48,7 +47,7 @@ struct pci_doe_mb { struct xarray prots; wait_queue_head_t wq; - struct workqueue_struct *work_queue; + struct mutex lock; unsigned long flags; }; @@ -198,7 +197,6 @@ static int pci_doe_recv_resp(struct pci_doe_mb *doe_mb, struct pci_doe_task *tas static void signal_task_complete(struct pci_doe_task *task, int rv) { task->rv = rv; - task->complete(task); } static void signal_task_abort(struct pci_doe_task *task, int rv) @@ -218,10 +216,8 @@ static void signal_task_abort(struct pci_doe_task *task, int rv) signal_task_complete(task, rv); } -static void doe_statemachine_work(struct work_struct *work) +static void exec_task(struct pci_doe_task *task) { - struct pci_doe_task *task = container_of(work, struct pci_doe_task, - work); struct pci_doe_mb *doe_mb = task->doe_mb; struct pci_dev *pdev = doe_mb->pdev; int offset = doe_mb->cap_offset; @@ -278,18 +274,12 @@ static void doe_statemachine_work(struct work_struct *work) signal_task_complete(task, rc); } -static void pci_doe_task_complete(struct pci_doe_task *task) -{ - complete(task->private); -} - static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid, u8 *protocol) { u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX, *index); u32 response_pl; - DECLARE_COMPLETION_ONSTACK(c); struct pci_doe_task task = { .prot.vid = PCI_VENDOR_ID_PCI_SIG, .prot.type = PCI_DOE_PROTOCOL_DISCOVERY, @@ -297,17 +287,13 @@ static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid, .request_pl_sz = sizeof(request_pl), .response_pl = &response_pl, .response_pl_sz = sizeof(response_pl), - .complete = pci_doe_task_complete, - .private = &c, }; int rc; - rc = pci_doe_submit_task(doe_mb, &task); + rc = pci_doe_submit_task_wait(doe_mb, &task); if (rc < 0) return rc; - wait_for_completion(&c); - if (task.rv != sizeof(response_pl)) return -EIO; @@ -359,13 +345,6 @@ static void pci_doe_xa_destroy(void *mb) xa_destroy(&doe_mb->prots); } -static void pci_doe_destroy_workqueue(void *mb) -{ - struct pci_doe_mb *doe_mb = mb; - - destroy_workqueue(doe_mb->work_queue); -} - /** * pcim_doe_create_mb() - Create a DOE mailbox object * @@ -391,25 +370,13 @@ struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset) doe_mb->pdev = pdev; doe_mb->cap_offset = cap_offset; init_waitqueue_head(&doe_mb->wq); + mutex_init(&doe_mb->lock); xa_init(&doe_mb->prots); rc = devm_add_action(dev, pci_doe_xa_destroy, doe_mb); if (rc) return ERR_PTR(rc); - doe_mb->work_queue = alloc_ordered_workqueue("%s %s DOE [%x]", 0, - dev_driver_string(&pdev->dev), - pci_name(pdev), - doe_mb->cap_offset); - if (!doe_mb->work_queue) { - pci_err(pdev, "[%x] failed to allocate work queue\n", - doe_mb->cap_offset); - return ERR_PTR(-ENOMEM); - } - rc = devm_add_action_or_reset(dev, pci_doe_destroy_workqueue, doe_mb); - if (rc) - return ERR_PTR(rc); - /* Reset the mailbox by issuing an abort */ rc = pci_doe_abort(doe_mb); if (rc) { @@ -456,24 +423,25 @@ bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type) EXPORT_SYMBOL_GPL(pci_doe_supports_prot); /** - * pci_doe_submit_task() - Submit a task to be processed by the state machine + * pci_doe_submit_task_wait() - Submit and execute a task * * @doe_mb: DOE mailbox capability to submit to - * @task: task to be queued + * @task: task to be run * - * Submit a DOE task (request/response) to the DOE mailbox to be processed. - * Returns upon queueing the task object. If the queue is full this function - * will sleep until there is room in the queue. - * - * task->complete will be called when the state machine is done processing this - * task. + * Submit and run DOE task (request/response) to the DOE mailbox to be + * processed. * * Excess data will be discarded. * - * RETURNS: 0 when task has been successfully queued, -ERRNO on error + * Context: non-interrupt + * + * RETURNS: 0 when task was executed, the @task->rv holds the status + * result of the executed opertion, -ERRNO on failure to submit. */ -int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task) +int pci_doe_submit_task_wait(struct pci_doe_mb *doe_mb, struct pci_doe_task *task) { + int rc; + if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type)) return -EINVAL; @@ -489,8 +457,13 @@ int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task) return -EIO; task->doe_mb = doe_mb; - INIT_WORK(&task->work, doe_statemachine_work); - queue_work(doe_mb->work_queue, &task->work); + + rc = mutex_lock_interruptible(&doe_mb->lock); + if (rc) + return rc; + exec_task(task); + mutex_unlock(&doe_mb->lock); + return 0; } -EXPORT_SYMBOL_GPL(pci_doe_submit_task); +EXPORT_SYMBOL_GPL(pci_doe_submit_task_wait); diff --git a/include/linux/pci-doe.h b/include/linux/pci-doe.h index ed9b4df792b8..c94122a66221 100644 --- a/include/linux/pci-doe.h +++ b/include/linux/pci-doe.h @@ -30,8 +30,6 @@ struct pci_doe_mb; * @response_pl_sz: Size of the response payload (bytes) * @rv: Return value. Length of received response or error (bytes) * @complete: Called when task is complete - * @private: Private data for the consumer - * @work: Used internally by the mailbox * @doe_mb: Used internally by the mailbox * * The payload sizes and rv are specified in bytes with the following @@ -50,11 +48,6 @@ struct pci_doe_task { u32 *response_pl; size_t response_pl_sz; int rv; - void (*complete)(struct pci_doe_task *task); - void *private; - - /* No need for the user to initialize these fields */ - struct work_struct work; struct pci_doe_mb *doe_mb; }; @@ -72,6 +65,5 @@ struct pci_doe_task { struct pci_doe_mb *pcim_doe_create_mb(struct pci_dev *pdev, u16 cap_offset); bool pci_doe_supports_prot(struct pci_doe_mb *doe_mb, u16 vid, u8 type); -int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task); - +int pci_doe_submit_task_wait(struct pci_doe_mb *doe_mb, struct pci_doe_task *task); #endif