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[2620:137:e000::1:20]) by mx.google.com with ESMTP id oj2-20020a17090b4d8200b001fe1cc52234si14513766pjb.67.2022.11.21.23.41.20; Mon, 21 Nov 2022 23:41:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=dFC6GbAP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232438AbiKVHka (ORCPT + 99 others); Tue, 22 Nov 2022 02:40:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232242AbiKVHkW (ORCPT ); Tue, 22 Nov 2022 02:40:22 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94981B491 for ; Mon, 21 Nov 2022 23:39:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bJ2u7mh9nd2kJ2SvCMIUbxbNtsjSUFYoRollOBUuJAE=; b=dFC6GbAPpM573pcrn5gst2XnY+L432w5W0DYRLYPUtrXc4RdAbX1VkTDfsXSeh1OqvDHJ4 N2unV+4HbIgbRC53hwGi1p8QYX3Q82uACfD992EePRQuMSwl8FcNdwg3Y26GKmULY7ciwa Zll8ZHTk+NqW2cxFTvpmaGO92PTRQ0U5WMSx9Q4wU4l8J9WKTEJEaWPE8TzRHY+myFWXOU XUmPcrnmcsR9s6XB8jgINsi18CLziugKkYpdXd5xwUIRHkLN2vSU3+KG0fBQiQQ0KveAg6 TdtNLVnJ/2/dFdV8gTJ+gaqAejSfcsij+CbxSz0TlNFdWu8cHPTsNq1CJgkN4Q== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-9-8qG2M24zMBahALnruAeT0w-2; Tue, 22 Nov 2022 02:39:21 -0500 X-MC-Unique: 8qG2M24zMBahALnruAeT0w-2 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:17 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 1/4] x86/of: Convert Intel's APIC bindings to YAML schema Date: Tue, 22 Nov 2022 15:39:07 +0800 Message-ID: <0cf089495a422b945ac4fc9c980ddb5429a711c3.1669100394.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750181237949440067?= X-GMAIL-MSGID: =?utf-8?q?1750181237949440067?= Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Addditionally, add description which was missing in text file and add few more required standard properties which were also missing in text file. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 62 +++++++++++++++++++ .../intel,ce4100-lapic.yaml | 49 +++++++++++++++ 3 files changed, 111 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible = "intel,ce4100-ioapic"; - #interrupt-cells = <2>; - - Device's interrupt property: - - interrupts =

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible = "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..da966287eec2 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) + +maintainers: + - Sebastian Andrzej Siewior + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more + details on it. + + This schema defines bindings for I/O APIC interrupt controller. + +properties: + compatible: + const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible = "intel,ce4100-ioapic"; + reg = <0xfec00000 0x1000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml new file mode 100644 index 000000000000..d4b99bf7bf6e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Sebastian Andrzej Siewior + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more + details on it. + + This schema defines bindings for local APIC interrupt controller. + +properties: + compatible: + const: intel,ce4100-lapic + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible = "intel,ce4100-lapic"; + reg = <0xfee00000 0x1000>; + }; From patchwork Tue Nov 22 07:39:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2059332wrr; Mon, 21 Nov 2022 23:41:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf5j4oBIZ3dIB5m6e5pj3PvI+A9XY3AlQZAsQm1Bug7+MH/QL5CnBGMf2Gtiq1jFEqveWT5d X-Received: by 2002:a05:6a00:4501:b0:56b:b049:6c6c with SMTP id cw1-20020a056a00450100b0056bb0496c6cmr6599960pfb.22.1669102918748; Mon, 21 Nov 2022 23:41:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669102918; cv=none; d=google.com; s=arc-20160816; b=0DKk6DlHOV7cgQA7VOVCOFaMJT9KvLAcvY8D6pO4ooIjiqWyJyXp8B+3AhZ8UWJLwz 3ayS0/7+VJEcgScS2LGyBraDrtBqTvy1CRo1s7hfMsdYBfsJkFLVJosDjCxUWsSl2SH2 lbvLpNcP2dh82kMQvAQEq3EbX1xFzD+fEJ9rfc7AY0oeJ+V64cOucNLX13L3MBvtyrJn Kf/YWMXlCzo+Irg0iOXXvRB6MTo871rTdnoUQgz77PGVxr4Bxe/fkN55NGQbjtZSUn87 WCoUmh1nuMT5VLKiugY/PisJBt87jO8u/YSfO3NbB8MLPJd/nfhcdN9GMNq8iT4oGhpd VvaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uGSJ7DPtFsorciAkWhHmN4hRW1hAr3Y9mVSmMvM8cgs=; b=Rici0lwqVa7eOIHkMc83/FQD93y66HUqL+J122/IiM/TZGGG9Ne398I3AExUF651wB x0Ngz3G7Qfah8FqsbF1s1w5KwPjMpUJe7EQN5B5y6EaKTS9+JJ0+33TMReb12Llizuu2 7VLxExk1pIlHsr4+cFy5tiqnks4Lr3ZWp5b6xsu03cHojkStc/KEL4Rr2Covp0V071jB 7g41kMkQdkTzNPemv32FsmYkIJDi2N2g+p5jHBX9wU2qtvIDC4BGF7e6pSyfEXXkW3sA MNnpsryyy7lfwbFA1An+BytqD4ecpBPiANylj6q3I/50r5xX9NyZAGw+8ecjnZmLBCEp NLeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=OXwjCA8E; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml index d4b99bf7bf6e..087f849e31ef 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -35,6 +35,19 @@ properties: reg: maxItems: 1 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. + For ACPI or MPS spec compliant systems, it is figured out by some read + only bit field/s available in their respective defined data structures. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt delivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -46,4 +59,5 @@ examples: lapic0: interrupt-controller@fee00000 { compatible = "intel,ce4100-lapic"; reg = <0xfee00000 0x1000>; + intel,virtual-wire-mode; }; From patchwork Tue Nov 22 07:39:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24176 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2059333wrr; Mon, 21 Nov 2022 23:41:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf4tHQ4qtKUV/paSa5h83S/2KX+TK+AWOTdkBA9K6aEXiR09nh+xB6t0ReqPW7r5HHPMgVOI X-Received: by 2002:a17:902:9686:b0:189:24b3:c54 with SMTP id n6-20020a170902968600b0018924b30c54mr2635752plp.96.1669102918797; Mon, 21 Nov 2022 23:41:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669102918; cv=none; d=google.com; s=arc-20160816; b=Gqk0psjCHeb4hV6GZUxfy3+PCwJGs3TDr1JNZaTU2OJKhxZTqvjQl74qzXt1RrZQe4 zYwa72FJOx8q1SKKQ96td0M3iOav+LwhH/1BHJoitBHnQStwz/vDtJ4xs4qTT54QHJex lQmWiqLfwK9O9vQPhmdooxtRdg4FtBNPnjuNzDzRD4mwvkwxFHU9qEJWkbRAimjyYmsg BpYmJ3HfGoVuxdIo0AviHYc4XApRgGCjzHhtXo9kiO1i7BLRFs2wrEVM3k6vn9nMIW8f cQ7xWasun/v4FLv6xpOLmf6M7S1yYFzphLGpCA+14NFZ11hh6FG68nWOIXR2UaIAOYvi 19zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XtiwGqXBFxhLlETvxktwt1UqNvSglqTHBPfqfwhsYIM=; b=g8Hxq3pUR3uZDjnlXupLmFRGxqd2YttyhcTCeJns72dZR5ojpMuHbC8/Tr9I8MC9TO xuM6I6w5OYtJYZ3e0wjjAMc5Q5OYrKLQu8TH3GyqYgwlXKLG6JTB5v2ZYQqnd0SNxVql /OBloIBUXwUxDSw/9bgudzu2IsI5sSwKDXZh+pqDl28fO3KKwYhXPRBpl5zp7T0Vs35R 578J5pvTFIZU4aMHpjhiYE43pWlcJQ+Pyz1Y2xgl6KkdO3USLPyrIlH4kbo1AjW9GVHY qLFtd3r3lcoA3CEWuylLtVDkyyooExRTGGiZn2GZkDF2Vt/BV3iSUVbZFzgNApn58k8T gbFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=UcP263p6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n6-20020a170902f60600b00188f4d6c28csi13524801plg.167.2022.11.21.23.41.40; Mon, 21 Nov 2022 23:41:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=UcP263p6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232465AbiKVHkf (ORCPT + 99 others); Tue, 22 Nov 2022 02:40:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232429AbiKVHkX (ORCPT ); Tue, 22 Nov 2022 02:40:23 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A18282F02B for ; Mon, 21 Nov 2022 23:39:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102769; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XtiwGqXBFxhLlETvxktwt1UqNvSglqTHBPfqfwhsYIM=; b=UcP263p6N2TG1BS4XSgvYyUErTmv6YA8VCzKnX4jKwyY49R+zQ/dYeYllwvYObWST3djcb XfbT/2DS0pje3R7oCXETGoaeVtF+2/TL5PI34Ay/oUdAQEMuT1g8Wlxu3/pDkoKAEGw6Be cLFSYPK5vFyVIVNgF02U8NCgIhrKvvu8ttMJHfGaAa8ZeBeFAz8kB2EGeobdm6KrCF5OP5 RkAB/2GiBQJND7+XVPsmvm8l2f3b8PKpqazkPmBIx9iyp69gelEG1bYfK3GBQzZdHZ/NsK ccK3XWglzWqjszV23xHAu34VodndVs/7QGBHlCdMoeZu3RbSvGlQxjp9zlZN3g== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-403-ZD30hwUhOOCueD0AViRi6g-1; Tue, 22 Nov 2022 02:39:27 -0500 X-MC-Unique: ZD30hwUhOOCueD0AViRi6g-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:23 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Date: Tue, 22 Nov 2022 15:39:09 +0800 Message-ID: <64a905649accf1b68f03c31a9b6ce205b03c6703.1669100394.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750181262037778226?= X-GMAIL-MSGID: =?utf-8?q?1750181262037778226?= Use latest available pr_lvl() instead of older printk(KERN_LVL) Just a upgrade of print utilities usage no functional changes. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar Reviewed-by: Andy Shevchenko --- arch/x86/kernel/devicetree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..fcc6f1b7818f 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *dn) ret = of_address_to_resource(dn, 0, &r); if (ret) { - printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); + pr_err("Can't obtain address from device node %pOF.\n", dn); return; } mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); @@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void) of_ioapic = 1; return; } - printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); + pr_err("Error: No information about IO-APIC in OF.\n"); } #else static void __init dtb_ioapic_setup(void) {} From patchwork Tue Nov 22 07:39:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Tanwar X-Patchwork-Id: 24178 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2059417wrr; Mon, 21 Nov 2022 23:42:15 -0800 (PST) X-Google-Smtp-Source: AA0mqf6UzaDwoRmdsvcn1iA1K4cbUYKsVoEt9yI0gOnfbxAvS5QrAXLcK0o+or8Pi/u7frEMI1R8 X-Received: by 2002:a17:90a:b946:b0:213:d7cc:39cb with SMTP id f6-20020a17090ab94600b00213d7cc39cbmr30365425pjw.144.1669102934728; Mon, 21 Nov 2022 23:42:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669102934; cv=none; d=google.com; s=arc-20160816; b=Vh/2KGPXoQJAYJPF66OhIBJMpGhLDCjd0+Z25w32DhUJQ8IEYa8G9iLWw15X5s3gpo GeFdr/NTA55azCKv+DErISwh4Isq5ekj6k0u4YzxMRHeWRK5g9jyIAqtKE+MXioiwQzS tpgB/lcuLNLxsn5VVm7+zFsSpFL/MSLURftnDVTzenDQnXUo54o2XYXU4yKSW49G6Ajf Lx/0eGwzNn1G9WmW60O8wunF94uN8+xxpoHXpMBvbI3ccI6cS70ozvG4Zdds5CwAHGNx HiB6IYuh2rOG4YvJFqjej09jptpZ9c9EkCLpzSK3Xb/HhCjx3YUgRKu++dcTrJ8eL+WQ JeQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NIxTZz2RzC+iXQFQE7e0/V45lRrJ5i50zwbfXYW5JwA=; b=Oij+fFBrgMATdQXeT59hO34pIQW8uXMS6UFKmmc+tQ5adyW72X5JOWVmvHAmg5fJyR NAnuO1lSG1vQlWMrcUtdxOVHZiFb+HNmntASFa9YVLzFeqTeQ2eWjhuCvK0oa4Z5TNJs dy2PpWnmbDLqZqAgyTe/BcRsxSk9CO7UFvBuNHzu4mkaxwRORzqGY0+vsw1yzPNd1s+V k7tvMW6nxSVwdT37YO1jbN6wEWEns0Bw2dw7vmisXV2vVI+3LpMcRKV/i3pvj7B77Kz0 rqCYS1sb9SNreYEX2v6MTPn55a047m4fFllFfxQMMq+D6+ddk/IhSoSzyF+rznizd1RN OM9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@maxlinear.com header.s=selector header.b=IsAIDmzi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=maxlinear.com Received: from out1.vger.email (out1.vger.email. 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But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This is a bug for platforms which are OF based but do not use 8259 compliant legacy PIC interrupt controller. Such platforms can not even boot because of this bug/hardcoding. Fix this bug by adding support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC") Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config = 1; - pic_mode = 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + pr_info("Virtual Wire compatibility mode.\n"); + pic_mode = 0; + } else { + pr_info("IMCR and PIC compatibility mode.\n"); + pic_mode = 1; + } + register_lapic_address(lapic_addr); }