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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y5-20020a056402440500b0045138471d7csi11033271eda.375.2022.11.21.06.58.32; Mon, 21 Nov 2022 06:58:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=s1lueuqm; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=MBeTqTJk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231686AbiKUOpG (ORCPT + 99 others); Mon, 21 Nov 2022 09:45:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231912AbiKUOoq (ORCPT ); Mon, 21 Nov 2022 09:44:46 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B109CFEB1; Mon, 21 Nov 2022 06:39:52 -0800 (PST) Message-ID: <20221121140048.344525618@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041570; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VMdi78Ph2ZKt//IeQ4f995Y7xixQx0PVMNetg0nGRuE=; b=s1lueuqmL8rn1uMzqRQQRUHs8j8k/PkQkr2FJayzUfJfBRzHMwnhKu/4YzxQRoJorfRzoU 8rw39T93j+gaLV9OPwyttucgaKM38hHBhQJgqU3caAg8N5/683w2esfJcfBgzRKouh0wqq a+G20BwLFXT7fvCEYMziNoTp/uL+/VDnwrWStO4yh0G5zMRoGqKi/+pHIPtHx/RanKrwjP 8NkqmtSrNGxN2RYeso48vaUquk7W2L35QPy68rsQ3zB9H/0cN4oGgvyinCf0YQyKt7EZ3U OcHFgGyNHeUEHAwZJJsyciQhX8cXeoblH6XN/iaO6a5x4BW6mnqLQKydoyl2Hg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041570; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VMdi78Ph2ZKt//IeQ4f995Y7xixQx0PVMNetg0nGRuE=; b=MBeTqTJkLdnku5CLyv6f0wHkET+DFJKaoKtmUAmidr2fZ2eYNfvQPhyph1fu65IpXbLV59 jqtVa9JpyObax5AA== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 01/40] irqchip/irq-mvebu-icu: Fix works by chance pointer assignment References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:29 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118156423884107?= X-GMAIL-MSGID: =?utf-8?q?1750118156423884107?= Assigning a void pointer which points to a struct to two different data types only works by chance if the second type is the first member of the struct. Replace this works by chance code by using the primary struct pointer. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth Acked-by: Marc Zyngier --- drivers/irqchip/irq-mvebu-icu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/irqchip/irq-mvebu-icu.c +++ b/drivers/irqchip/irq-mvebu-icu.c @@ -151,9 +151,9 @@ static int mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) { - struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d); - struct mvebu_icu *icu = platform_msi_get_host_data(d); unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2; + struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d); + struct mvebu_icu *icu = msi_data->icu; /* Check the count of the parameters in dt */ if (WARN_ON(fwspec->param_count != param_count)) { From patchwork Mon Nov 21 14:39:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23848 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1637366wrr; Mon, 21 Nov 2022 06:59:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf47hSblk1HLfZ2WZRhLk2IB6FQVoMOsyPps8lwQPCvonZ2I6u7MAoCWpak4XpE9M+9ZHowV X-Received: by 2002:a05:6402:538e:b0:468:ea55:ab40 with SMTP id ew14-20020a056402538e00b00468ea55ab40mr16097924edb.323.1669042789127; Mon, 21 Nov 2022 06:59:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669042789; cv=none; d=google.com; s=arc-20160816; b=b60pXNXkTa0G0JsGlVaqH+P/t63Xly4NYwfq8MDPPwQbRYGy/elAzomwC05sRa3fcr IBZujj1ZeESpidpG+PTVWGmKIacYAJhuxHaG+0gZXwfc8f85vyfYU0oBMDIaewViR6Cl TrSSSFWW8t92NxYGiCGLBnGQI6J05fLPZgYJJJ7nCHhCLOX6Vx7jqgOYzaKi4UqVUrO9 sJcAJw9N9mvetzAQqgNcIPHWealKggBrp/deCDkCkGqBESaWyEbdy/Znk+FaAHIby2+1 54uqL/PAmbKa8K3WX/KGVmR3rzuL3yGmrLdw1coog4qv9YBcIADgiI6athiRTL9+ueLB 9fBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=v7+zNHMDfnt2h0cuevH6G6rdERYSvXaLiJHEl/OPzRA=; b=EcZBrqjvDXEXBPfts4RRAeUQWmF9ft4zndEJ6WWoKWzTMXM7Q2j8T1uuyNW+1nsQCM v+RrHq91HJN/QodcVUss2S8Qj1R6fdXGMn6mRMqwFldBieg2E/NKi1NY185Ky3uMiO8J 6ugv5XMb7fw0LxY4n/D2bIwQIHPeiRyKtlzl7x+Wn6tMLYbWjC9YFw5VOaWw7ndNkRww 0zQQX99iRSyte2u36QZW+UrlfqWiARa59Lmf4kG/JzQzIX6Bqc5GqBXn6Krp1hUZn60J lLG0E6whwt12VhF4otl27kxvptwDgH0UCyOlltm2FCOLy7ZZAxD9pRdC7mRSjIFYcCKl +Q6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=BK7De0GL; dkim=neutral (no key) header.i=@linutronix.de header.b=txp+8IF2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=v7+zNHMDfnt2h0cuevH6G6rdERYSvXaLiJHEl/OPzRA=; b=txp+8IF2ph3rlWD25/rWQf/qMPVnVy121ZePaP6MpxEhTz5t7liGLGi/FSqvC7A6KuwZJm qDuDIuLIIkbuwlCA== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 02/40] ACPI/IORT: Make prototype of iort_pmsi_get_dev_id() always available References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:31 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118211828401075?= X-GMAIL-MSGID: =?utf-8?q?1750118211828401075?= W=1 build complains: drivers/irqchip/irq-gic-v3-its-msi-parent.c:110:12: warning: no previous prototype for function 'iort_pmsi_get_dev_id' [-Wmissing-prototypes] int __weak iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) Reported-by: Ammar Faizi Signed-off-by: Thomas Gleixner Cc: Robin Murphy Cc: Lorenzo Pieralisi --- include/linux/acpi_iort.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -26,13 +26,15 @@ int iort_register_domain_token(int trans struct fwnode_handle *fw_node); void iort_deregister_domain_token(int trans_id); struct fwnode_handle *iort_find_domain_token(int trans_id); + +int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id); + #ifdef CONFIG_ACPI_IORT void acpi_iort_init(void); u32 iort_msi_map_id(struct device *dev, u32 id); struct irq_domain *iort_get_device_domain(struct device *dev, u32 id, enum irq_domain_bus_token bus_token); void acpi_configure_pmsi_domain(struct device *dev); -int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id); void iort_get_rmr_sids(struct fwnode_handle *iommu_fwnode, struct list_head *head); void iort_put_rmr_sids(struct fwnode_handle *iommu_fwnode, From patchwork Mon Nov 21 14:39:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23857 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1642904wrr; Mon, 21 Nov 2022 07:06:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf7qqWk/UsmYREm6iTxHvS2QOD4OjLDpzNb50MJIOuD3X34LlnhaOgGSAWRSbHW4HysqmhSZ X-Received: by 2002:a17:906:361a:b0:7ae:129b:2ce7 with SMTP id q26-20020a170906361a00b007ae129b2ce7mr2867543ejb.92.1669043210121; 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Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier Acked-by: Marc Zyngier --- drivers/irqchip/irq-gic-v2m.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -263,7 +263,7 @@ static struct msi_domain_info gicv2m_pms .chip = &gicv2m_pmsi_irq_chip, }; -static void gicv2m_teardown(void) +static void __init gicv2m_teardown(void) { struct v2m_data *v2m, *tmp; @@ -278,7 +278,7 @@ static void gicv2m_teardown(void) } } -static int gicv2m_allocate_domains(struct irq_domain *parent) +static __init int gicv2m_allocate_domains(struct irq_domain *parent) { struct irq_domain *inner_domain, *pci_domain, *plat_domain; struct v2m_data *v2m; @@ -405,7 +405,7 @@ static int __init gicv2m_init_one(struct return ret; } -static const struct of_device_id gicv2m_device_id[] = { +static __initconst struct of_device_id gicv2m_device_id[] = { { .compatible = "arm,gic-v2m-frame", }, {}, }; @@ -455,7 +455,7 @@ static int __init gicv2m_of_init(struct #ifdef CONFIG_ACPI static int acpi_num_msi; -static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev) +static __init struct fwnode_handle *gicv2m_get_fwnode(struct device *dev) { struct v2m_data *data; @@ -470,7 +470,7 @@ static struct fwnode_handle *gicv2m_get_ return data->fwnode; } -static bool acpi_check_amazon_graviton_quirks(void) +static __init bool acpi_check_amazon_graviton_quirks(void) { static struct acpi_table_madt *madt; acpi_status status; From patchwork Mon Nov 21 14:39:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23847 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1637170wrr; Mon, 21 Nov 2022 06:59:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf7MHgjTLR93AnqTLC3oBrz0xHAW/VCjyPvsEKAD+zEVuHegMeYxvSlaHySS3fWHBkZ/mriS X-Received: by 2002:a63:711e:0:b0:477:5654:c37e with SMTP id m30-20020a63711e000000b004775654c37emr8164967pgc.206.1669042763082; Mon, 21 Nov 2022 06:59:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669042763; cv=none; d=google.com; s=arc-20160816; b=Ub+2T67B4fBKcogSAjbpzcBNObMyEi9LneN4rNOMT2TtTUrAtNMQ+ddKTGWqLuL7rM HaC+g1KK7UfeX9nqpAZxQOlaStI+1C6tBO14uBPHoLgdi4ZvF3qMGNxYn6sExbqDfhef UMyVZPdQNEziVJ9pC7fMf0kHudvg04G0gF9iMBtfFf/nMfx4q2j2+tyTs+UsxhGBV1bW 7yWH8ykyrmBYOk0wQ25v0/Rtw1R3UTduqqR98BM/1CVHqTtl+qd+Qtc6NWW0wk2xwmix /+FqvaDbOvEbipg05r7eXHr2QauFCSwjH98LXNSwRXAIYa+sm2W8uLaX03gFXgxpAm6j kibg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=XmeDaeqxxBY7nsoBMruO4Bn75n1RoKWKMjjDX37M0fs=; b=ZQ5B+9ZMM42j8ePbShC/G5CVhb3ykZg9dWtlHcg93hE2R7O8fIR6mhfnZA26q7d4Uc dNxyzp8r13p6LmY19IvO2Iir/lFOHT9CZizRyXSOy+HYmfoSa6KBBhIl46JDWQ3ND3Bm DtGKFeiG4YYw8lsBesCNc/RUOVb/6qaAITK4Eld5LILqvbPNkoamXDkowxhSc2ys9hiT zPbP0f2i9sVIw3q9XarWwtVj4vCXJ/+PhuIY8ht+7qwqHE1gA7dgJl8ncyXFuTE2H3+6 6deJUuoY23Y/xxGZbmLPFAozkijp7UlOBPRZj3xwITPYMtzcnOslB/ZPzcxmCoELoSfT 5FIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=hAIlLxN1; dkim=neutral (no key) header.i=@linutronix.de header.b=4TRSK3fT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XmeDaeqxxBY7nsoBMruO4Bn75n1RoKWKMjjDX37M0fs=; b=4TRSK3fTnqS9ah+MoAl2pZjh7JGD7zL3nf8/AlaZJEycpo5R4OnAVQ9KVGqzBJKDU/VQfh oWMLvyBEwF05AKAg== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 05/40] irqchip/ti-sci-inta: Fix kernel doc References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:34 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118184373223012?= X-GMAIL-MSGID: =?utf-8?q?1750118184373223012?= W=1 build complains: drivers/irqchip/irq-ti-sci-inta.c:177: warning: Function parameter or member 'vint_id' not described in 'ti_sci_inta_xlate_irq' drivers/irqchip/irq-ti-sci-inta.c:177: warning: Excess function parameter 'irq' description in 'ti_sci_inta_xlate_irq' Signed-off-by: Thomas Gleixner Cc: Nishanth Menon Cc: Tero Kristo Cc: Santosh Shilimkar Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Acked-by: Marc Zyngier --- drivers/irqchip/irq-ti-sci-inta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/irqchip/irq-ti-sci-inta.c +++ b/drivers/irqchip/irq-ti-sci-inta.c @@ -168,7 +168,7 @@ static void ti_sci_inta_irq_handler(stru /** * ti_sci_inta_xlate_irq() - Translate hwirq to parent's hwirq. * @inta: IRQ domain corresponding to Interrupt Aggregator - * @irq: Hardware irq corresponding to the above irq domain + * @vint_id: Hardware irq corresponding to the above irq domain * * Return parent irq number if translation is available else -ENOENT. */ From patchwork Mon Nov 21 14:39:36 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hq28-20020a1709073f1c00b007ae1e635ea3si10582886ejc.754.2022.11.21.06.58.53; Mon, 21 Nov 2022 06:59:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ztMtjC8C; dkim=neutral (no key) header.i=@linutronix.de header.b="B/8rXcQr"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231863AbiKUOql (ORCPT + 99 others); Mon, 21 Nov 2022 09:46:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231135AbiKUOqT (ORCPT ); Mon, 21 Nov 2022 09:46:19 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2269D2347; Mon, 21 Nov 2022 06:40:44 -0800 (PST) Message-ID: <20221121140048.659849460@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041576; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s+g/QPbklxPzM4FZ4SYWZR5FPe67LrDVUw7p5TgGo7M=; b=ztMtjC8CMfgn0ofL21t85GjPjHPmJj0DI3J8Wj1MfBlR/rPA9bWrNAj8tRTWNu+JZ4F+Rz Y6kYfSLLdpSwYVpuJp1Pnvt4t1kSSGDOheLoI98NvBg9myVGmqCGdHBLyq/fMYdeyfOfTM kEy3hloOeLgpVrxfdIRbR6F4oveg0ZdHqBfXPT5u96Bbr4eWrtGqJSP2tDKYN1oGAs+6TK 3DGkJ4NCruCBMMprw16iBMfMjAZCKI4HSW400IL3L/FKElF72mUKNWSm+eI/FTQsT24ZmF AyQiTWfrn4XFXV+0+RUbb6HJ6PAgCYbHDfwif+JU6rYW7oaG7gT4cpvJ/xThAQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041576; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=s+g/QPbklxPzM4FZ4SYWZR5FPe67LrDVUw7p5TgGo7M=; b=B/8rXcQr4Eb6KRVesJ4zp0ATD6W2MViFL5MUAP3df6qU9aw5XXOTz46aiq58JCAE1M2DQ1 I72PpkA6DPvOwmAQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 06/40] PCI/MSI: Provide static key for parent mask/unmask References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:36 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118179098079009?= X-GMAIL-MSGID: =?utf-8?q?1750118179098079009?= Most ARM(64) PCI/MSI domains mask and unmask in the parent domain after or before the PCI mask/unmask operation takes place. So there are more than a dozen of the same wrapper implementation all over the place. Don't make the same mistake with the new per device PCI/MSI domains and provide a static key which lets the domain implementation enable this sequence in the PCI/MSI code. Signed-off-by: Thomas Gleixner Cc: Bjorn Helgaas --- drivers/pci/msi/irqdomain.c | 30 ++++++++++++++++++++++++++++++ include/linux/msi.h | 2 ++ 2 files changed, 32 insertions(+) --- a/drivers/pci/msi/irqdomain.c +++ b/drivers/pci/msi/irqdomain.c @@ -148,17 +148,45 @@ static void pci_device_domain_set_desc(m arg->hwirq = desc->msi_index; } +static DEFINE_STATIC_KEY_FALSE(pci_msi_mask_unmask_parent); + +/** + * pci_device_msi_mask_unmask_parent_enable - Enable propagation of mask/unmask + * to the parent interrupt chip + * + * For MSI parent interrupt domains which want to mask at the parent interrupt + * chip too. + */ +void pci_device_msi_mask_unmask_parent_enable(void) +{ + static_branch_enable(&pci_msi_mask_unmask_parent); +} + +static __always_inline void cond_mask_parent(struct irq_data *data) +{ + if (static_branch_unlikely(&pci_msi_mask_unmask_parent)) + irq_chip_mask_parent(data); +} + +static __always_inline void cond_unmask_parent(struct irq_data *data) +{ + if (static_branch_unlikely(&pci_msi_mask_unmask_parent)) + irq_chip_unmask_parent(data); +} + static void pci_mask_msi(struct irq_data *data) { struct msi_desc *desc = irq_data_get_msi_desc(data); pci_msi_mask(desc, BIT(data->irq - desc->irq)); + cond_mask_parent(data); } static void pci_unmask_msi(struct irq_data *data) { struct msi_desc *desc = irq_data_get_msi_desc(data); + cond_unmask_parent(data); pci_msi_unmask(desc, BIT(data->irq - desc->irq)); } @@ -195,10 +223,12 @@ static struct msi_domain_template pci_ms static void pci_mask_msix(struct irq_data *data) { pci_msix_mask(irq_data_get_msi_desc(data)); + cond_mask_parent(data); } static void pci_unmask_msix(struct irq_data *data) { + cond_unmask_parent(data); pci_msix_unmask(irq_data_get_msi_desc(data)); } --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -653,12 +653,14 @@ struct irq_domain *pci_msi_create_irq_do struct irq_domain *parent); u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev); struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev); +void pci_device_msi_mask_unmask_parent_enable(void); #else /* CONFIG_PCI_MSI */ static inline struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev) { return NULL; } static inline void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg) { } +static inline void pci_device_msi_mask_unmask_parent_enable(void) { } #endif /* !CONFIG_PCI_MSI */ #endif /* LINUX_MSI_H */ From patchwork Mon Nov 21 14:39:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23850 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1640582wrr; Mon, 21 Nov 2022 07:03:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf7VAdTJy3JRdUqScNLUhNRw2XKw82YPLCpGKwhBL6YkT7XhJsvSSmN3mKXzhySOUjggjAJ/ X-Received: by 2002:a17:906:3ac1:b0:78d:36d8:1814 with SMTP id z1-20020a1709063ac100b0078d36d81814mr15363320ejd.99.1669043028861; Mon, 21 Nov 2022 07:03:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043028; cv=none; d=google.com; s=arc-20160816; b=QfdsESQ7Lmlo5w+QGHdyHZ9cu5KA84h45hSrS2+7pEC+ulvMI6hnUpIDqjk4qHIPlp nbVyGdtdUP5cn4k4h9X1mHmhU/DBj7o4uzzayzISToAgw1STRwoybbOdCJIqFdxBHaWC 9cVMxEesPGny5RapTS0ckuVinNcJU2eo2hBc9g8q4/SMu2uKBaUcGGm2VRPpHwEk94EL srPrpBjKKMhHXBeB2k717i5GYvSeYQRnzk+cvvTiurtVYrvyb25aio73W3jQ1WEYclPo 3VZl06cywZ4ayRtWGQQGijA1XJG18vMB6uxvNuaX9WA6m2qKna3iUegdb2garEwUt6Gs 3JZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=0uPKQvIE6eHWFWTzh0P31YZRE+J5P6MvaWi2wIg9qig=; b=WaYL8MePgvtdUqi3iuCSlS5QJaqVeTnomGZbbLu/a2jkzpD5C57u6KnqiFBSjkeUzz NVQl7MwBhqd3kjpNKpij1Tx8YeExbpiDE1pFqtS9D2L3Ht8wdadtKdfUVQQYPv9dZjaY rv608AlV5EPi4530sYi+cLK1mAAhqKD95TR6Cx2qNDoPeIa3iRJNThIHZcpf0C+z5MNX 8TJjavbpG66gON845Jsj+WzJFUtLRfnufZZAkAlfyfhBjib3Io9qsyF1WJ309rAtHzMI dP3EZKium9BURhXa1t+LE+vLoy6IvKygZE8rHMmzUPrGWR3rV+NcRy6R/9XKGPZUaja+ ULMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=2xxh3n8f; dkim=neutral (no key) header.i=@linutronix.de header.b=PCeo9bxF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id mp8-20020a1709071b0800b007add405cccdsi10292368ejc.444.2022.11.21.07.03.05; Mon, 21 Nov 2022 07:03:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=2xxh3n8f; dkim=neutral (no key) header.i=@linutronix.de header.b=PCeo9bxF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230377AbiKUOsj (ORCPT + 99 others); Mon, 21 Nov 2022 09:48:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231856AbiKUOqc (ORCPT ); Mon, 21 Nov 2022 09:46:32 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F368D236B; Mon, 21 Nov 2022 06:40:56 -0800 (PST) Message-ID: <20221121140048.722992910@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041577; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0uPKQvIE6eHWFWTzh0P31YZRE+J5P6MvaWi2wIg9qig=; b=2xxh3n8fCQKY1tupSQrL9RMghm2CJAVDhvY/Tjdbm5UyTrZ3617loyNvTvtgNhd1HURZCG Ex96BmehgLludH3jYNj5aEgGOs3VtfcvigHKrZKPcj+QOILkhwD1zWcorhR2EQI6SmQQ5n KukieQVmKgYlUtVMunHXe/xRbloR1Epl9yYeoaU26IAVI2n/oqnJCsqZfEUyIs0/ujwyPo pZrNPN0L6CDAvMrk6b/buOWEbQOjlyfd5MmgRoRi1qpQ16QV8lOeNG/friBcWTlSuxbbJC Hopj84F9VxpGLUoQSU3abw9iD9Rfjr2mF19toJL/p/AnaCzwIr5dX5AihkVlXg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041577; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=0uPKQvIE6eHWFWTzh0P31YZRE+J5P6MvaWi2wIg9qig=; b=PCeo9bxFppNV9qQQ6klCeD7Y79K1FfbS6EFwmhDWSSkQCY8I3v39UhssGnoodq7GVDpqqE ZkeJvgcIGuShZNDQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 07/40] irqchip/gic-v3: Make gic_irq_domain_select() robust for zero parameter count References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:37 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118462826710228?= X-GMAIL-MSGID: =?utf-8?q?1750118462826710228?= Currently the irqdomain select callback is only invoked when the parameter count of the fwspec arguments is not zero. That makes sense because then the match is on the firmware node and eventually on the bus_token, which is already handled in the core code. The upcoming support for per device MSI domains requires to do real bus token specific checks in the MSI parent domains with a zero parameter count. Make the gic-v3 select() callback handle that case. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1613,9 +1613,13 @@ static int gic_irq_domain_select(struct irq_hw_number_t hwirq; /* Not for us */ - if (fwspec->fwnode != d->fwnode) + if (fwspec->fwnode != d->fwnode) return 0; + /* Handle pure domain searches */ + if (!fwspec->param_count) + return d->bus_token == bus_token; + /* If this is not DT, then we have a single domain */ if (!is_of_node(fwspec->fwnode)) return 1; From patchwork Mon Nov 21 14:39:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23859 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1643106wrr; Mon, 21 Nov 2022 07:07:09 -0800 (PST) X-Google-Smtp-Source: AA0mqf6O+Kw9v18GGuQpj+DSrtHctyLDHjUT5BSGzkicfEl3xOp6B1xiFFcOBqu6lNAelY4jbi65 X-Received: by 2002:ac2:4104:0:b0:4ac:102e:5c93 with SMTP id b4-20020ac24104000000b004ac102e5c93mr394649lfi.352.1669043229392; Mon, 21 Nov 2022 07:07:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043229; cv=none; d=google.com; s=arc-20160816; b=IIOe2y289l9obrb65HmG0HZ5UEBlWz9tyKk/fW2CW6J3b1rGwMym6u/qXYHozwAGh6 MA7C1ep81Uay+i+1logOfG5rO9omwxrTeDFEcuvzLRwFVWKTX67TeCL8emmbZ3AltTkg mjZ6uTHtPTqHy0c2URdThfLyolFResPjgY2MdmDgfG4wJj/gnRrVnWFk/fYxXuJ9gplv 2k9hDCDSmI4a7sz6gpZzAu3b87pjzVo0wjaYj7FpwTIlCthzPIlIVg0b9mO99fG/FzwT 4AK0wbuUSJkMvOONrjCn34eNVpEMSwnkxHrOtL6kkb0zF3vfHMhA9Z+JoClc7eVzxTHU JmwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=lryKCdg7QeE0MhY5O2OfgLlItEx02Ny9/G/YzdpvlKM=; b=ugujGh8drz6PbRDbHC4ylYgu6VWoiKWKOWvp/XIZC+KN3oRub40bBkltWhen7x4/GJ Z/Oct2kT7OCK9Q8+DvEYPxNyhbbxPFug5JUHZ0noIzRQtbXERsFsEQeV0HKZ+NziOsWl N6oaY0d4QTQWhCQp/WLVvvhf3hUBh5Qvq6Yw4ptBGNeNLklPFGAuWsdHiuRh5ZSM3rbA A5k+zgpeTFu3QiTfKFGUvbqq2rX2vn5CQaOBZ6xemr5xMkmlRnpq3aLysmwJoE07PKaE T9errBLmXjJ7TXIq3jigPmZNgdnWDkbGmAQFGNVpF0GoFoT8qwkGp2BZ+70uhqtC001S xYgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EvfA4Chl; dkim=neutral (no key) header.i=@linutronix.de header.b=eKAUQqZW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id pj17-20020a170906d79100b007a45e4f4ff0si5196981ejb.885.2022.11.21.07.06.21; Mon, 21 Nov 2022 07:07:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EvfA4Chl; dkim=neutral (no key) header.i=@linutronix.de header.b=eKAUQqZW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231726AbiKUOss (ORCPT + 99 others); Mon, 21 Nov 2022 09:48:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232213AbiKUOre (ORCPT ); Mon, 21 Nov 2022 09:47:34 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D28B3D2987; Mon, 21 Nov 2022 06:41:40 -0800 (PST) Message-ID: <20221121140048.785620505@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041578; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lryKCdg7QeE0MhY5O2OfgLlItEx02Ny9/G/YzdpvlKM=; b=EvfA4ChliMdUWDqFwD48kq3Hg0yw0bqkMrO1I5BIckFvTPdega+p+b5VYOwVlM76jwFHLW adCBGVY5fe7qKOI6TX/hnojOb8TxywOTUDg2KFJhXFkRtxZTII+5r4mx5Ciip9wBI81VVG zy9EX16+9f55IyVJUjCOfcB+aK6H+7Nw/cM89SZ5K8p9r+kgk4PRC6HwFWq22aScexZWKh 6xT3b8avmlv/OraRbE5S/3bFXs1w8qx2z7bK03svjMgz7699ieamCuRwOo0lPHIiRWhhag qejNDCdn9UdihbEkhouzH5Vhtc7XjquHuIV2zbaaFqSBCxsaLHtSrog9RJZqGw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041578; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lryKCdg7QeE0MhY5O2OfgLlItEx02Ny9/G/YzdpvlKM=; b=eKAUQqZWCQ4VtNX8iVvvP7N4sbQ/Pq5wipjeK7yYD6tszP4D450UAP/9XSiZgzOVuUq9mE GiklmwXIgED4jwAw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 08/40] genirq/irqdomain: Remove the param count restriction from select() References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:38 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118673229051585?= X-GMAIL-MSGID: =?utf-8?q?1750118673229051585?= Now that the GIC-v3 callback can handle invocation with a fwspec parameter count of 0 lift the restriction in the core code and invoke select() unconditionally when the domain provides it. Preparatory change for per device MSI domains. Signed-off-by: Thomas Gleixner --- kernel/irq/irqdomain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -417,7 +417,7 @@ struct irq_domain *irq_find_matching_fws */ mutex_lock(&irq_domain_mutex); list_for_each_entry(h, &irq_domain_list, link) { - if (h->ops->select && fwspec->param_count) + if (h->ops->select) rc = h->ops->select(h, fwspec, bus_token); else if (h->ops->match) rc = h->ops->match(h, to_of_node(fwnode), bus_token); From patchwork Mon Nov 21 14:39:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23879 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646921wrr; Mon, 21 Nov 2022 07:12:39 -0800 (PST) X-Google-Smtp-Source: AA0mqf5zl0v4+AbLdqbpk8sAy97NvRZ0dQV5z+IUEGcBaNEgENW8jGJp0rxq7kKsdm8tB6SxXi1f X-Received: by 2002:a17:902:b20c:b0:189:1318:714 with SMTP id t12-20020a170902b20c00b0018913180714mr9581879plr.122.1669043559190; Mon, 21 Nov 2022 07:12:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043559; cv=none; d=google.com; s=arc-20160816; b=f4WMpoyuXmqJv+OEQT9CPEq0lgwtOz57RSWXBqISnEirLtqX/Ow2hlBViEz5dNt1dN 5dJSZ4xSJ7jbEaRNZeegjz2Ikw0qA6MPGQRMf/E3mjpXKoRTN54Fb/911uAVzDyIUMFh Bgz2br9oMpZ+EI/zKy0Uqfcs4LiWsl01iyLiEkNbnYB7k2GqGZDkSn+Bd6ez8M4YQhNb 1sDt+itB/2ski/1AfB8ECwBlV23rmyIh1nKp5Ljai5qw9QQFrJ5QAKSkuAy7gF0esI5i mU4Zb2J1j9FyO5qeonFlmmFQXkek8uterMt3IIW+zLPgPw/PgTQb0lbskPUcevhYzYUO 4Igw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=UZS11zTOR4JGS38C/7fpGOXRWJz4E7s7evBEbCg06U4=; b=gUDUl60hedCsj9wucIhq3L0PS66uQCJ5lNKGnQIuIla2j9n/FTVJkOnb0w5FOPJc/5 0aRlgx6gId1pleqD6D/LVqQU99fhMgou4CqnMJFeKcNY/P2lpDN42ob/p3q601j24udS nTjs0IrGTsnVvP8ocXuol3N0N+n3jEiaHKfIC+zdhTz5yXrOlZvhZBoXi6usgUgBIfWH jS9OwMFLMFr6hhy/VKGh/5yAZi2eN85M+m0DybaLUBb/vg+GH9ENVgS0/4pQb8treXh2 EAefkUsufkNLx+a6LnH9vnoEqbRxfrvKqeILLzKvkbKZU8CXb7gJ82Ca3LrQMASu8MWx D9Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=IWtyqOfa; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n36-20020a635924000000b0046f72960500si11193013pgb.379.2022.11.21.07.12.20; Mon, 21 Nov 2022 07:12:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=IWtyqOfa; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231266AbiKUOzt (ORCPT + 99 others); Mon, 21 Nov 2022 09:55:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229802AbiKUOze (ORCPT ); Mon, 21 Nov 2022 09:55:34 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52873CFBB1; Mon, 21 Nov 2022 06:45:16 -0800 (PST) Message-ID: <20221121140048.849246242@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041580; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UZS11zTOR4JGS38C/7fpGOXRWJz4E7s7evBEbCg06U4=; b=IWtyqOfanQvxMKLKPN7fGmW0o2xzn3gxDdqo42IMVg9Go9jVble5nrAW32WLYffMsexzIe 6xZqA8JwqEwxsd5s+n34HYkK4IQE/I7b5mubvR1xwecgbiLsWt+LqUXg+Nm6hAA2gZEW9l eYaVC9A321U0BFH4+X+7frVNI8v+mymmOD2j6yvTyjiMo/N9GSjfxTg2nkBR8tdcplOKXY V/FnCfBUHON7jcCpS0UpPjeSSog9cxOizd4H2nuU2F58W6IaOHoCccVypBg+JbuXx/Jbon c1qX/CWJeig/KNzt2AtIBaVjFMwfnCknfMtszTsI8iJeJCuRmA0fc3MdXtiEoQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041580; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UZS11zTOR4JGS38C/7fpGOXRWJz4E7s7evBEbCg06U4=; b=OrC9JZmx1rLqXQ93KbSuzak2wSNsDqJQEtHxMHymOfW7NHPiReiyEOeokmJ7IE84OTcH94 HsxU9DQJTVOibgDg== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 09/40] genirq/msi: Extend msi_parent_ops References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:39 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750119018989078402?= X-GMAIL-MSGID: =?utf-8?q?1750119018989078402?= Supporting per device MSI domains on ARM64 and the zoo of interrupt mechanisms needs a bit more information than what the initial x86 implementation provides. Add the following fields: - required_flags: The flags which a parent domain requires to be set - bus_select_token: The bus token of the parent domain for select() - bus_select_mask: A bitmask of supported child domain bus types This allows to provide library functions which can be shared between various interrupt chip implementations and avoids replicating mostly similar code all over the place. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 11 +++++++++++ 1 file changed, 11 insertions(+) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -556,6 +556,14 @@ enum { * struct msi_parent_ops - MSI parent domain callbacks and configuration info * * @supported_flags: Required: The supported MSI flags of the parent domain + * @required_flags: Optional: The required MSI flags of the parent MSI domain + * Mandatory for ARM_GIC_MSI_LIB users + * @bus_select_token: Optional: The bus token of the real parent domain for + * irq_domain::select() + * Mandatory for ARM_GIC_MSI_LIB users + * @bus_select_mask: Optional: A mask of supported BUS_DOMAINs for + * irq_domain::select() + * Mandatory for ARM_GIC_MSI_LIB users * @prefix: Optional: Prefix for the domain and chip name * @init_dev_msi_info: Required: Callback for MSI parent domains to setup parent * domain specific domain flags, domain ops and interrupt chip @@ -563,6 +571,9 @@ enum { */ struct msi_parent_ops { u32 supported_flags; + u32 required_flags; + u32 bus_select_token; + u32 bus_select_mask; const char *prefix; bool (*init_dev_msi_info)(struct device *dev, struct irq_domain *domain, struct irq_domain *msi_parent_domain, From patchwork Mon Nov 21 14:39:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1638909wrr; Mon, 21 Nov 2022 07:01:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf6ug4K4BFAFH3Gmss7mKWMLjBmT3uWSgC82TxeHlLTstk7UKLHIljEaO3Lj+SoJ7nVJwl4O X-Received: by 2002:a17:907:8b14:b0:7b5:addd:ea67 with SMTP id sz20-20020a1709078b1400b007b5adddea67mr5603169ejc.11.1669042918186; Mon, 21 Nov 2022 07:01:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669042918; cv=none; d=google.com; s=arc-20160816; b=qs5taNc+r44zYVlUKvOT0P1a3N76sewQaDIF4TeGjjWYq+RCbb555PVpcd6DiqiAwt IyR3z45c5nbNRMpdhQpFTkzQls8OuxbcCRqv/hCly++3FcaSsCLgP8CM9aOQURH0hnZk o9R0ZrPJPZEhJIyHX04uamOacjHlNFTot0GwaPhMmfmTNKHs2CgJYB0JKIILa6nblVko WQ04W2oem2K/V2ArhsugPYkzxGAgETdnwVWGzMjGyQ4JgX7lh732QwkBx4Wm9Errxnta gC1naoNUnYB6fvNnMhWaSl2xSTNaxbcDTnmYKBTKmavAfnfOxjlpKzSnjHUgt6VDwCDO IwKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=idBO2Jn3x7lJLQyPZWlY/n45k+pAZ7w1xLsTIR+PA4Q=; b=I1oYndwak9ao16kyXSNafUcNbLUTYrhy6sXDQxkKDD9pAXWsdIoe6Zc2EDB93CHQRU HvQAnoqd7O7z0vcD/r4al+gPSANrLQuTZhHgqng4gAFHk88PuWgUK/G5YFk3hOOfskCy PAxnPi3kb7ktVO2S3kyaveE5O6oonK5uFc+XKYezjEcqAxZoSW6LZohpFJcxe1mZRTIl bIF0WaVMgpKxBDRS1dNCfHGPXU8Q2gGsejGgG+yXdVE2Yfkh25AdMGvjL59n24RNlMMK Laj3OxAsf+3ddSHk+NZo0D/GlDM6CsfKI9yDQSbIFRMbllC/npPUo6bzHwYwyoMIfiLK 1j8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=vYJ3zwSV; dkim=neutral (no key) header.i=@linutronix.de header.b=fPTd3YlK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ji16-20020a170907981000b0078d9d67841fsi9749812ejc.400.2022.11.21.07.01.19; Mon, 21 Nov 2022 07:01:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=vYJ3zwSV; dkim=neutral (no key) header.i=@linutronix.de header.b=fPTd3YlK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231645AbiKUOsV (ORCPT + 99 others); Mon, 21 Nov 2022 09:48:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231681AbiKUOqo (ORCPT ); Mon, 21 Nov 2022 09:46:44 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3559DD2883; Mon, 21 Nov 2022 06:41:04 -0800 (PST) Message-ID: <20221121140048.913023922@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041581; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=idBO2Jn3x7lJLQyPZWlY/n45k+pAZ7w1xLsTIR+PA4Q=; b=vYJ3zwSV7ba7WJwns1j0+2RwIgwpv41OLCYeXbqcxPsKW7xxH3hu5JG8a5gekFdSnHDMwk vCEnkFzoW3KSLiz2b5rqXGHcwZbsJuj4WwPpOAOXpDpInmL/LTLAXsV3BFPyPAFDtGzZ6+ V+Z8xHB8vYIdUkG57DCiCeVOf+qFaZK3bKwva4LDpEV73Lvt8cocbRC0PjCtYRYDVdTS8T Rzb3AD2JkOBlqMS8IpMvRlkoI2SQ37mjUPFs5A54cLryF0XFkzumCTRPIHaT18DXI1UaYE nG3WJuzYkhsp9Zwzk9Yka/kC3JZmXzaJxwnZvfbTCdGiYYhK81qp0YTwiJoGbg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041581; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=idBO2Jn3x7lJLQyPZWlY/n45k+pAZ7w1xLsTIR+PA4Q=; b=fPTd3YlKMUbpX7p/xnzUnj3Y1k0ggMFVNh1oc6avPGlyM1NCHu7cEj3F77oxLPltSAxWwj HJodJOv7sk1eX8BQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 10/40] irqchip: Provide irq-gic-lib References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:41 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118347099349705?= X-GMAIL-MSGID: =?utf-8?q?1750118347099349705?= All irqdomains which provide MSI parent domain functionality for per device MSI domains need to provide a select() callback for the irqdomain and a function to initialize the child domain. Most of these functions would just be copy&pasta with minimal modifications, so provide a library function which implements the required functionality and is customizable via parent_domain::msi_parent_ops Signed-off-by: Thomas Gleixner --- V2: Export functions for modular irqchip drivers... --- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 drivers/irqchip/irq-gic-msi-lib.c | 112 ++++++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gic-msi-lib.h | 19 ++++++ 4 files changed, 135 insertions(+) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -30,6 +30,9 @@ config ARM_GIC_V2M config GIC_NON_BANKED bool +config ARM_GIC_MSI_LIB + bool + config ARM_GIC_V3 bool select IRQ_DOMAIN_HIERARCHY --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_SPEAR3XX) += spear-sh obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o +obj-$(CONFIG_ARM_GIC_MSI_LIB) += irq-gic-msi-lib.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o --- /dev/null +++ b/drivers/irqchip/irq-gic-msi-lib.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2022 Linutronix GmbH +// Copyright (C) 2022 Intel + +#include + +#include "irq-gic-msi-lib.h" + +/** + * gic_msi_lib_init_dev_msi_info - Domain info setup for MSI domains + * @dev: The device for which the domain is created for + * @domain: The domain providing this callback + * @real_parent: The real parent domain of the to initialize domain + * which might be a domain built on top of @domain + * or @domain itself + * @info: The domain info for the to initialize domain + * + * This function is to be used for all types of MSI domains above the root + * parent domain and any intermediates. The topmost parent domain specific + * functionality is determined via @real_parent. + * + * All intermediate domains between the root and the device domain must + * have either msi_parent_ops.init_dev_msi_info = msi_parent_init_dev_msi_info + * or invoke it down the line. + */ +bool gic_msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, + struct msi_domain_info *info) +{ + const struct msi_parent_ops *pops = real_parent->msi_parent_ops; + + /* + * MSI parent domain specific settings. For now there is only the + * root parent domain, e.g. NEXUS, acting as a MSI parent, but it is + * possible to stack MSI parents. See x86 vector -> irq remapping + */ + if (domain->bus_token == pops->bus_select_token) { + if (WARN_ON_ONCE(domain != real_parent)) + return false; + } else { + WARN_ON_ONCE(1); + return false; + } + + /* Parent ops available? */ + if (WARN_ON_ONCE(!pops)) + return false; + + /* Is the target domain bus token supported ? */ + switch(info->bus_token) { + default: + /* + * This should never be reached. See + * gic_msi_lib_irq_domain_select() + */ + WARN_ON_ONCE(1); + return false; + } + + /* + * Mask out the domain specific MSI feature flags which are not + * supported by the real parent. + */ + info->flags &= pops->supported_flags; + /* Enforce the required flags */ + info->flags |= pops->required_flags; + + /* Chip updates for all child bus types */ + if (!info->chip->irq_eoi) + info->chip->irq_eoi = irq_chip_eoi_parent; + + /* + * The device MSI domain can never have a set affinity callback it + * always has to rely on the parent domain to handle affinity + * settings. The device MSI domain just has to write the resulting + * MSI message into the hardware which is the whole purpose of the + * device MSI domain aside of mask/unmask which is provided e.g. by + * PCI/MSI device domains. + */ + info->chip->irq_set_affinity = msi_domain_set_affinity; + return true; +} +EXPORT_SYMBOL_GPL(gic_msi_lib_init_dev_msi_info); + +/** + * gic_msi_lib_irq_domain_select - Shared select function for NEXUS domains + * @d: Pointer to the irq domain on which select is invoked + * @fwspec: Firmware spec describing what is searched + * @bus_token: The bus token for which a matching irq domain is looked up + * + * Returns: %0 if @d is not what is being looked for + * + * %1 if @d is either the domain which is directly searched for or + * if @d is providing the parent MSI domain for the functionality + * requested with @bus_token. + */ +int gic_msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + const struct msi_parent_ops *ops = d->msi_parent_ops; + u32 busmask = BIT(bus_token); + + if (fwspec->fwnode != d->fwnode || fwspec->param_count != 0) + return 0; + + /* Handle pure domain searches */ + if (bus_token == ops->bus_select_token) + return 1; + + return ops && !!(ops->bus_select_mask & busmask); +} +EXPORT_SYMBOL_GPL(gic_msi_lib_irq_domain_select); --- /dev/null +++ b/drivers/irqchip/irq-gic-msi-lib.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2022 Linutronix GmbH +// Copyright (C) 2022 Intel + +#ifndef _DRIVERS_IRQCHIP_IRQ_GIC_MSI_LIB_H +#define _DRIVERS_IRQCHIP_IRQ_GIC_MSI_LIB_H + +#include +#include +#include + +int gic_msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token); + +bool gic_msi_lib_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, + struct msi_domain_info *info); + +#endif /* _DRIVERS_IRQCHIP_IRQ_GIC_MSI_LIB_H */ From patchwork Mon Nov 21 14:39:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23883 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1647811wrr; Mon, 21 Nov 2022 07:14:12 -0800 (PST) X-Google-Smtp-Source: AA0mqf5ZUoKkc2MdfbFjjSxl0x01zYIqVjTr0jdICOwLolduoa86vFZVP/2s5stGep7wDNiILSnM X-Received: by 2002:a63:5747:0:b0:46f:cbcb:761a with SMTP id h7-20020a635747000000b0046fcbcb761amr3508413pgm.82.1669043652224; Mon, 21 Nov 2022 07:14:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043652; cv=none; d=google.com; s=arc-20160816; b=XUDl4PZY60B7ACknm6M8Nqc4eBdKslTPohr1hAXxNIxQ4lMxxvA4WSHnOf1WKW+Gka wid/IqlWiRKPQ2AUl6pfjZbRk6JzLSt4Nk5jxFTBXHe4TcasfJ3HedhRYpK2sek9RLkg OPUknpMhv0hBfvyWWKx02VWQly+aDqA1dNi9zc8W0oP1vHc0QPivFhgaSPK646btvAT3 rOItxw4vKXCXBiwUCh9qZVauP+oXCoDV47WxmTQG8jQ4gLa5hx27oW/A8ewKsJ+C4/sh Am4GR2jx4pFW2ee78FIByczrfoHKQeePi8F7sdcftGMtxwiEP6Zr2gjALa/mX1xntgiV YPag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=J680i1QxtZBBm/698AYzrsmPCp2I4TQ8+mHi4G7lF8s=; b=aZ6z28PAMSZeU8isA7s3fZCiTJdix+NSo3hV8Jt0a5yBmj/cb3NJ+A5LwntHrwsQct e/yrRA1ZJhDNhNgBHria1YKRUw7M98vYOCPudQ5tsuCDbl5d8ZAsn4KDVd0oaA70TZC2 z3xG9gLhH9wDj+JkT3Wc+NaAw9wUOY7gzk/R+6jgWK+4x41Y/H+bO6/zjVv8mQRj38+A IdfbnOIYjf+sCWgR0FnKEH/+RdyyRRqrGnjNz10IwjarFvggVpaINw8vnB+fTLwa/2n2 JnFmLx32Q6qPk/2lFyGh4IpGJTtzT4wQNbUlxWHHInViBMH3hZ35oNZ+DCQOHuTzLlJf l6Vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YEAcDoKF; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s21-20020a056a00195500b0056ed0d35397si10629838pfk.184.2022.11.21.07.13.52; Mon, 21 Nov 2022 07:14:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YEAcDoKF; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbiKUO4Y (ORCPT + 99 others); Mon, 21 Nov 2022 09:56:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231233AbiKUOz6 (ORCPT ); Mon, 21 Nov 2022 09:55:58 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35730C845D; Mon, 21 Nov 2022 06:45:57 -0800 (PST) Message-ID: <20221121140048.974974729@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041582; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=J680i1QxtZBBm/698AYzrsmPCp2I4TQ8+mHi4G7lF8s=; b=YEAcDoKFN2i4HVtKWLa93Rn3Nps5WvYcJZWF3OQBX/wCxYsjmB3/W+naIybJwtc5JKRWMu UiDIX9UCYQAVjw5qQ3wTY1RKTVq1L3eSAF5jkp3pxvkByrs8Mw+MIwt92R/E9yxF8XEaYa gJJRkH6mQ/tDvHAcA99s1suZuo5qEGBJp7IbGLZNRmD3T9uK7Gtq9xyOynHKBwFkbAeisF xoyGgmi95Qk+/TpW8JTT5VqDyoul3M71V6SXNTkLj/avRKqqmt+j1Di39KiBLgt2R7Nq/R 0jeTEzL1ermxR4Z92SKpXbPimZTev/TvBiGMhTmZk+nLRQwcAq3HetmEAsO3gA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041582; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=J680i1QxtZBBm/698AYzrsmPCp2I4TQ8+mHi4G7lF8s=; b=CXynxs3icGJRX156kuitvZRrXMV4gIhHiX9TrvNmBx4NWbVOitTheb3WrmiC6M5iVzAKJ8 68QizqSKkXZAc4Cw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 11/40] irqchip/gic-v3-its: Provide MSI parent infrastructure References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:42 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750119116890404870?= X-GMAIL-MSGID: =?utf-8?q?1750119116890404870?= To support per device MSI domains the ITS must provide MSI parent domain functionality. Provide the basic skeleton for this: - msi_parent_ops - child domain init callback - the MSI parent flag set in irqdomain::flags This does not make ITS a functional parent domain as there is no bit set in the bus_select_mask yet, but it provides the base to implement PCI and platform MSI support gradualy on top. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/Kconfig | 1 drivers/irqchip/Makefile | 2 - drivers/irqchip/irq-gic-common.h | 3 ++ drivers/irqchip/irq-gic-v3-its-msi-parent.c | 30 ++++++++++++++++++++++++++++ drivers/irqchip/irq-gic-v3-its.c | 4 +++ 5 files changed, 39 insertions(+), 1 deletion(-) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -42,6 +42,7 @@ config ARM_GIC_V3 config ARM_GIC_V3_ITS bool select GENERIC_MSI_IRQ + select ARM_GIC_MSI_LIB default ARM_GIC_V3 config ARM_GIC_V3_ITS_PCI --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -33,7 +33,7 @@ obj-$(CONFIG_ARCH_REALVIEW) += irq-gic- obj-$(CONFIG_ARM_GIC_MSI_LIB) += irq-gic-msi-lib.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o -obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o +obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o irq-gic-v3-its-msi-parent.o obj-$(CONFIG_ARM_GIC_V3_ITS_PCI) += irq-gic-v3-its-pci-msi.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -8,6 +8,7 @@ #include #include +#include #include struct gic_quirk { @@ -28,4 +29,6 @@ void gic_enable_quirks(u32 iidr, const s void gic_enable_of_quirks(const struct device_node *np, const struct gic_quirk *quirks, void *data); +extern const struct msi_parent_ops gic_v3_its_msi_parent_ops; + #endif /* _IRQ_GIC_COMMON_H */ --- /dev/null +++ b/drivers/irqchip/irq-gic-v3-its-msi-parent.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2022 Linutronix GmbH +// Copyright (C) 2022 Intel + +#include "irq-gic-common.h" +#include "irq-gic-msi-lib.h" + +#define ITS_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define ITS_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_PCI_MSIX | \ + MSI_FLAG_MULTI_PCI_MSI) + +static bool its_init_dev_msi_info(struct device *dev, struct irq_domain *domain, + struct irq_domain *real_parent, struct msi_domain_info *info) +{ + if (!gic_msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) + return false; + + return true; +} + +const struct msi_parent_ops gic_v3_its_msi_parent_ops = { + .supported_flags = ITS_MSI_FLAGS_SUPPORTED, + .required_flags = ITS_MSI_FLAGS_REQUIRED, + .bus_select_token = DOMAIN_BUS_NEXUS, + .prefix = "ITS-", + .init_dev_msi_info = its_init_dev_msi_info, +}; --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -38,6 +38,7 @@ #include #include "irq-gic-common.h" +#include "irq-gic-msi-lib.h" #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) @@ -3656,6 +3657,7 @@ static void its_irq_domain_free(struct i } static const struct irq_domain_ops its_domain_ops = { + .select = gic_msi_lib_irq_domain_select, .alloc = its_irq_domain_alloc, .free = its_irq_domain_free, .activate = its_irq_domain_activate, @@ -4918,6 +4920,8 @@ static int its_init_domain(struct fwnode inner_domain->parent = its_parent; irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); inner_domain->flags |= its->msi_domain_flags; + inner_domain->msi_parent_ops = &gic_v3_its_msi_parent_ops; + inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; info->ops = &its_msi_domain_ops; info->data = its; inner_domain->host_data = info; From patchwork Mon Nov 21 14:39:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23880 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646950wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h21-20020a632115000000b0044fb27b64c7si11735422pgh.326.2022.11.21.07.12.23; Mon, 21 Nov 2022 07:12:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=sd7rSg2k; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=1LwGc7zM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230474AbiKUO4S (ORCPT + 99 others); Mon, 21 Nov 2022 09:56:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231145AbiKUOz6 (ORCPT ); Mon, 21 Nov 2022 09:55:58 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E135D0DCC; Mon, 21 Nov 2022 06:45:57 -0800 (PST) Message-ID: <20221121140049.038269899@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041583; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LWZzkLvZ5gHjlFpFBFxZZ1jfolwvE2BdWztZvI0p9OM=; b=sd7rSg2kigN5NlHza6Cga+tuw6V9g85Jshy3OJDjK1D5b+qUcdz91t0O3Qb7ZR3SW3lewI DfbjxwYyurnLIoogWDByWH0NlutYf0V9VkIgvV++7jY+zYa2EGu6EI+IFMEIRtc7la0rzE WH2IxOydVABXRQ06Sao4uSzlRihp9Tikofgzb6iL/mTFJaNuvRHqVrlxRDhFWQbqjxfnwK igW9I5XFFuEXC8Yb8YimZO73/2RCiXQFbZQ3E87PAo1mabN/cafe+5XcUS3S6syHFoA8dp uv6aXrfvYzLHbEOGm8lueongK4ZyUOIXhPaYWp2MYcMNNmNeyME8yfFFDVpvzQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041583; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LWZzkLvZ5gHjlFpFBFxZZ1jfolwvE2BdWztZvI0p9OM=; b=1LwGc7zMWirV3udF+2ZM+b/fwdVY8bzXmFqARcd7mOXQ0aeXbaK0OWc4jNKdf3PHPi8Z1H paC0VXkW6C9Kn5Aw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 12/40] irqchip/gic-msi-lib: Prepare for PCI MSI/MSIX References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:43 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750119021951106992?= X-GMAIL-MSGID: =?utf-8?q?1750119021951106992?= Add the bus tokens for DOMAIN_BUS_PCI_DEVICE_MSI and DOMAIN_BUS_PCI_DEVICE_MSIX to the common child init function and enable the parent mask/unmask static key in the PCI/MSI core. Provide the match mask which can be used by parent domain implementation so the bitmask based child bus token match works. Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-gic-msi-lib.c | 7 +++++++ drivers/irqchip/irq-gic-msi-lib.h | 6 ++++++ 2 files changed, 13 insertions(+) --- a/drivers/irqchip/irq-gic-msi-lib.c +++ b/drivers/irqchip/irq-gic-msi-lib.c @@ -48,6 +48,13 @@ bool gic_msi_lib_init_dev_msi_info(struc /* Is the target domain bus token supported ? */ switch(info->bus_token) { + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: + if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_PCI_MSI))) + return false; + + pci_device_msi_mask_unmask_parent_enable(); + break; default: /* * This should never be reached. See --- a/drivers/irqchip/irq-gic-msi-lib.h +++ b/drivers/irqchip/irq-gic-msi-lib.h @@ -9,6 +9,12 @@ #include #include +#ifdef CONFIG_PCI_MSI +#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) +#else +#define MATCH_PCI_MSI (0) +#endif + int gic_msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, enum irq_domain_bus_token bus_token); From patchwork Mon Nov 21 14:39:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23860 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1643136wrr; Mon, 21 Nov 2022 07:07:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf5fIBVVSBNyjqrpRwxUalGDwaZwStQ/WiTzlNdbDT6UxXeU3VDp6bEhobgooBUcO2liWPE3 X-Received: by 2002:a05:6402:4504:b0:463:71ef:b9ce with SMTP id ez4-20020a056402450400b0046371efb9cemr8222368edb.75.1669043231694; Mon, 21 Nov 2022 07:07:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043231; cv=none; d=google.com; s=arc-20160816; b=bG4Ox7BtUqNUo75p/rNXiscPiWHjpmb8lUppT+Pa4QFe8nu7tOqV/ikqBxgGuEn32e qGySshycuVaInZnf9gIvR4OtumrAXsJCN8HYRCb67GuaEP5zlepgqoW5FPRevpkERIN6 ahhxmj/DpOy7LnxVa4KI/FdGenlkpvG1afUO/pJ4hyKAgRm+RxPgavka772sPsUopewF UnQohYMThCMrK+3GNTBHBwFUJkeS7E22MeP5JR+11CejjpRaqURZwy6L5ixYbG6c5sQS uVv/qxlB1qNiZcgsLGVog5d7qVYr1NMmmcY4IJ16jXFzNYGHaezklcBQjFo2nP2/KVjR DUBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=jpf4uTDZSxvRjVAE3WgmDcW+YtGdj2bZVH5YpiSoOUo=; b=SVNU4/8U53i+HRd9vPScbkECHS4czSOMFlfe4XLjaeUxzQQKWxap/tKfndx0h/wvK9 8zbNm7XMUhhaoptp4yGryyjp5mHX7BgTAmsFwvh8XFnBX+dX27OgjH5PgLKJYo0gq2Ox wW/YdLQrVPck3LpnsUVI31ENnqEhAfNgXqFzBV9hiQ2ZtC4L51S17vgzFHT8RTfEz6bX LkJJ33v9OIt8XZ25Gz+1z++wYpW0o8yyPFZLd3k/hys2ZCP4Y9rCa4pioMLSQinvFPpc TJRxX9ajsucenDL5EOCjvwMsQMVhaGiRNnl8yVtjnSS/Fm/Se0Y6uFh5deJgZJrCzLnz HlwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=G9DBuITp; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ho18-20020a1709070e9200b0078d9b2facaesi9771271ejc.339.2022.11.21.07.06.24; Mon, 21 Nov 2022 07:07:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=G9DBuITp; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230233AbiKUOtx (ORCPT + 99 others); Mon, 21 Nov 2022 09:49:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230229AbiKUOsR (ORCPT ); Mon, 21 Nov 2022 09:48:17 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86E6AD39CC; Mon, 21 Nov 2022 06:42:12 -0800 (PST) Message-ID: <20221121140049.112451419@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=jpf4uTDZSxvRjVAE3WgmDcW+YtGdj2bZVH5YpiSoOUo=; b=G9DBuITpemF9kibAhhPqyHeoHh8ExTBDmwMhPjBZh0I0DnioHVrhMPH+wlUSSc+NbtZJKD EPf3WK33eJaIiCZuBpBye2OhETYwXEnMwwhJ8Uvr9V3vofViIbUQ79o+aKDHTh0b77ylQA nLazQ1U0hjaMoO9atHzYEgZZMtzXGNopdb+Dss2PvhGpd0lQnoyjz3tAgU1i+fJpITYrix NznzSqq3vZPseHhxG+gvNKLIg6GZZmZ42g41huXCtozTLWBBoEAKdwabp+Cw8yCpx9EqG0 gsYqjEc4SeVbdGRTU7ZKf2kMt+svMm+eBIFH0/pe02WQgPGOX/YgCvo2eIjAAw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=jpf4uTDZSxvRjVAE3WgmDcW+YtGdj2bZVH5YpiSoOUo=; b=YQ3dUE5uR8oBuOat+5zzb0nbJD4JBkAS060GpXpRCNgwgcZn8InxqEW06CNV5Mtrh8QUkf yMFJIAUMcLViWtDg== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 13/40] irqchip/gic-v3-its: Provide MSI parent for PCI/MSI[-X] References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:44 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118675440824462?= X-GMAIL-MSGID: =?utf-8?q?1750118675440824462?= Lift the its_pci_msi_prepare() function from the ITS-PCI/MSI code which provides the 'global' PCI/MSI domains and amend it to use the domain hardware size, which is the MSI[X] vector count, for allocating the ITS slots for the PCI device. Enable PCI matching in msi_parent_ops and provide the necessary update to the ITS specific child domain initialization function so that the prepare callback gets invoked on allocations. The latter might be optimized to do the allocation right at the point where the child domain is initialized, but keep it simple for now. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/Makefile | 1 drivers/irqchip/irq-gic-v3-its-msi-parent.c | 106 ++++++++++++++ drivers/irqchip/irq-gic-v3-its-pci-msi.c | 202 ---------------------------- 3 files changed, 106 insertions(+), 203 deletions(-) --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -34,7 +34,6 @@ obj-$(CONFIG_ARM_GIC_MSI_LIB) += irq-gi obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o irq-gic-v3-its-msi-parent.o -obj-$(CONFIG_ARM_GIC_V3_ITS_PCI) += irq-gic-v3-its-pci-msi.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o --- a/drivers/irqchip/irq-gic-v3-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-v3-its-msi-parent.c @@ -1,7 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only +// Copyright (C) 2013-2015 ARM Limited, All Rights Reserved. +// Author: Marc Zyngier // Copyright (C) 2022 Linutronix GmbH // Copyright (C) 2022 Intel +#include + #include "irq-gic-common.h" #include "irq-gic-msi-lib.h" @@ -12,12 +16,113 @@ MSI_FLAG_PCI_MSIX | \ MSI_FLAG_MULTI_PCI_MSI) +#ifdef CONFIG_PCI_MSI +static int its_pci_msi_vec_count(struct pci_dev *pdev, void *data) +{ + int msi, msix, *count = data; + + msi = max(pci_msi_vec_count(pdev), 0); + msix = max(pci_msix_vec_count(pdev), 0); + *count += max(msi, msix); + return 0; +} + +static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data) +{ + struct pci_dev **alias_dev = data; + + *alias_dev = pdev; + return 0; +} + +static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev, + int nvec, msi_alloc_info_t *info) +{ + struct pci_dev *pdev, *alias_dev; + struct msi_domain_info *msi_info; + int alias_count = 0, minnvec = 1; + + if (!dev_is_pci(dev)) + return -EINVAL; + + pdev = to_pci_dev(dev); + /* + * If pdev is downstream of any aliasing bridges, take an upper + * bound of how many other vectors could map to the same DevID. + * Also tell the ITS that the signalling will come from a proxy + * device, and that special allocation rules apply. + */ + pci_for_each_dma_alias(pdev, its_get_pci_alias, &alias_dev); + if (alias_dev != pdev) { + if (alias_dev->subordinate) + pci_walk_bus(alias_dev->subordinate, + its_pci_msi_vec_count, &alias_count); + info->flags |= MSI_ALLOC_FLAGS_PROXY_DEVICE; + } + + /* ITS specific DeviceID, as the core ITS ignores dev. */ + info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev); + + /* + * @domain->msi_domain_info->hwsize contains the size of the + * MSI[-X] domain, but vector allocation happens one by one. This + * needs some thought when IMS comes into play as the size of IMS + * might be unknown at domain creation time and therefore set to + * MSI_MAX_INDEX. + */ + msi_info = msi_get_domain_info(domain); + if (msi_info->hwsize > nvec) + nvec = msi_info->hwsize; + + /* + * Always allocate a power of 2, and special case device 0 for + * broken systems where the DevID is not wired (and all devices + * appear as DevID 0). For that reason, we generously allocate a + * minimum of 32 MSIs for DevID 0. If you want more because all + * your devices are aliasing to DevID 0, consider fixing your HW. + */ + nvec = max(nvec, alias_count); + if (!info->scratchpad[0].ul) + minnvec = 32; + nvec = max_t(int, minnvec, roundup_pow_of_two(nvec)); + + msi_info = msi_get_domain_info(domain->parent); + return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info); +} +#else /* CONFIG_PCI_MSI */ +#define its_pci_msi_prepare NULL +#endif /* !CONFIG_PCI_MSI */ + static bool its_init_dev_msi_info(struct device *dev, struct irq_domain *domain, struct irq_domain *real_parent, struct msi_domain_info *info) { if (!gic_msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) return false; + switch(info->bus_token) { + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: + /* + * FIXME: This probably should be done after a (not yet + * existing) post domain creation callback once to make + * support for dynamic post-enable MSI-X allocations + * work without having to reevaluate the domain size + * over and over. It is known already at allocation + * time via info->hwsize. + * + * That should work perfectly fine for MSI/MSI-X but needs + * some thoughts for purely software managed IMS domains + * where the index space is only limited artificially via + * %MSI_MAX_INDEX. + */ + info->ops->msi_prepare = its_pci_msi_prepare; + break; + default: + /* Confused. How did the lib return true? */ + WARN_ON_ONCE(1); + return false; + } + return true; } @@ -25,6 +130,7 @@ const struct msi_parent_ops gic_v3_its_m .supported_flags = ITS_MSI_FLAGS_SUPPORTED, .required_flags = ITS_MSI_FLAGS_REQUIRED, .bus_select_token = DOMAIN_BUS_NEXUS, + .bus_select_mask = MATCH_PCI_MSI, .prefix = "ITS-", .init_dev_msi_info = its_init_dev_msi_info, }; --- a/drivers/irqchip/irq-gic-v3-its-pci-msi.c +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved. - * Author: Marc Zyngier - */ - -#include -#include -#include -#include -#include -#include - -static void its_mask_msi_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void its_unmask_msi_irq(struct irq_data *d) -{ - pci_msi_unmask_irq(d); - irq_chip_unmask_parent(d); -} - -static struct irq_chip its_msi_irq_chip = { - .name = "ITS-MSI", - .irq_unmask = its_unmask_msi_irq, - .irq_mask = its_mask_msi_irq, - .irq_eoi = irq_chip_eoi_parent, -}; - -static int its_pci_msi_vec_count(struct pci_dev *pdev, void *data) -{ - int msi, msix, *count = data; - - msi = max(pci_msi_vec_count(pdev), 0); - msix = max(pci_msix_vec_count(pdev), 0); - *count += max(msi, msix); - - return 0; -} - -static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data) -{ - struct pci_dev **alias_dev = data; - - *alias_dev = pdev; - - return 0; -} - -static int its_pci_msi_prepare(struct irq_domain *domain, struct device *dev, - int nvec, msi_alloc_info_t *info) -{ - struct pci_dev *pdev, *alias_dev; - struct msi_domain_info *msi_info; - int alias_count = 0, minnvec = 1; - - if (!dev_is_pci(dev)) - return -EINVAL; - - msi_info = msi_get_domain_info(domain->parent); - - pdev = to_pci_dev(dev); - /* - * If pdev is downstream of any aliasing bridges, take an upper - * bound of how many other vectors could map to the same DevID. - * Also tell the ITS that the signalling will come from a proxy - * device, and that special allocation rules apply. - */ - pci_for_each_dma_alias(pdev, its_get_pci_alias, &alias_dev); - if (alias_dev != pdev) { - if (alias_dev->subordinate) - pci_walk_bus(alias_dev->subordinate, - its_pci_msi_vec_count, &alias_count); - info->flags |= MSI_ALLOC_FLAGS_PROXY_DEVICE; - } - - /* ITS specific DeviceID, as the core ITS ignores dev. */ - info->scratchpad[0].ul = pci_msi_domain_get_msi_rid(domain, pdev); - - /* - * Always allocate a power of 2, and special case device 0 for - * broken systems where the DevID is not wired (and all devices - * appear as DevID 0). For that reason, we generously allocate a - * minimum of 32 MSIs for DevID 0. If you want more because all - * your devices are aliasing to DevID 0, consider fixing your HW. - */ - nvec = max(nvec, alias_count); - if (!info->scratchpad[0].ul) - minnvec = 32; - nvec = max_t(int, minnvec, roundup_pow_of_two(nvec)); - return msi_info->ops->msi_prepare(domain->parent, dev, nvec, info); -} - -static struct msi_domain_ops its_pci_msi_ops = { - .msi_prepare = its_pci_msi_prepare, -}; - -static struct msi_domain_info its_pci_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX), - .ops = &its_pci_msi_ops, - .chip = &its_msi_irq_chip, -}; - -static struct of_device_id its_device_id[] = { - { .compatible = "arm,gic-v3-its", }, - {}, -}; - -static int __init its_pci_msi_init_one(struct fwnode_handle *handle, - const char *name) -{ - struct irq_domain *parent; - - parent = irq_find_matching_fwnode(handle, DOMAIN_BUS_NEXUS); - if (!parent || !msi_get_domain_info(parent)) { - pr_err("%s: Unable to locate ITS domain\n", name); - return -ENXIO; - } - - if (!pci_msi_create_irq_domain(handle, &its_pci_msi_domain_info, - parent)) { - pr_err("%s: Unable to create PCI domain\n", name); - return -ENOMEM; - } - - return 0; -} - -static int __init its_pci_of_msi_init(void) -{ - struct device_node *np; - - for (np = of_find_matching_node(NULL, its_device_id); np; - np = of_find_matching_node(np, its_device_id)) { - if (!of_device_is_available(np)) - continue; - if (!of_property_read_bool(np, "msi-controller")) - continue; - - if (its_pci_msi_init_one(of_node_to_fwnode(np), np->full_name)) - continue; - - pr_info("PCI/MSI: %pOF domain created\n", np); - } - - return 0; -} - -#ifdef CONFIG_ACPI - -static int __init -its_pci_msi_parse_madt(union acpi_subtable_headers *header, - const unsigned long end) -{ - struct acpi_madt_generic_translator *its_entry; - struct fwnode_handle *dom_handle; - const char *node_name; - int err = -ENXIO; - - its_entry = (struct acpi_madt_generic_translator *)header; - node_name = kasprintf(GFP_KERNEL, "ITS@0x%lx", - (long)its_entry->base_address); - dom_handle = iort_find_domain_token(its_entry->translation_id); - if (!dom_handle) { - pr_err("%s: Unable to locate ITS domain handle\n", node_name); - goto out; - } - - err = its_pci_msi_init_one(dom_handle, node_name); - if (!err) - pr_info("PCI/MSI: %s domain created\n", node_name); - -out: - kfree(node_name); - return err; -} - -static int __init its_pci_acpi_msi_init(void) -{ - acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, - its_pci_msi_parse_madt, 0); - return 0; -} -#else -static int __init its_pci_acpi_msi_init(void) -{ - return 0; -} -#endif - -static int __init its_pci_msi_init(void) -{ - its_pci_of_msi_init(); - its_pci_acpi_msi_init(); - - return 0; -} -early_initcall(its_pci_msi_init); From patchwork Mon Nov 21 14:39:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23851 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1641358wrr; Mon, 21 Nov 2022 07:04:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf5MuAD6DfyKdJqVoux3L/y+9U92N8pNNwNeaNeqHsci4we048eSKviBtMsGmrcqfCZyuQ1O X-Received: by 2002:a17:906:c1d0:b0:7b4:64d3:e6f4 with SMTP id bw16-20020a170906c1d000b007b464d3e6f4mr1278301ejb.594.1669043084599; Mon, 21 Nov 2022 07:04:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043084; cv=none; d=google.com; s=arc-20160816; b=P0W72iqCwoDhzCp/gzBPGpFoEVwX5f0ScZeYLa1SiqbGeQLHgEIKZAgSE93aTrnvu4 88R/bGvW8HHqLsiiw5xeCy2IFTx979TCyRrJrf1FHZHMlvLD/UQr1c+uVi58hFlXYxyZ 8EqBaw46YfJtDi9p8ALiI5aVhhUC3m3Acj40GJuImSrqpK+ucsgiF9ToXR0VMtVTLqWY FyVmjo/iep/wyfspuBkxLIVDSRHqbu9vmAb3rTKFCR69RA5d+Af4PjgiP4nQ7/qOehup 7eeYEStdd+JV/dkL7Eaq89HzDkl0zS6G8eidXm4HT9n9Ul9HhVJL1Fc8NJC8tb/eKhIt TURQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=wpFVnFupwg4o33fIjYqnuqldVKOyyxjOYBrih4TBtQU=; b=y72qcov7fUi2Lv9imE9Imcf9zLq2ATUCPBchn9H7kglzzoXvi/prY7xh4ET6R8coke ymM0W58X4TaF2KqYPZuLclM8zx9YzyxXED7+qL04qAUyqjf6lSIy7I0KDgK2/nob615N JLJ9OJj/WsAulENGg7r6EFRiOur2R4I7JfpG7l3k/WlgUw5nMTrqeHyx7hbW0jNqk8mn gU09QvRz+bS8qF5CtQuwJOQi6uFBerH23X2ory8JzEiKnBLFInbqzW0/kuMePQgDdJYa J0gn8iJ43srCzLYNvyJ+9SzQ9TKHVrHxvIN8/5DzgpASm6emdCceaWSy3B9gByO9tzqX 2J4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="SERGv/Fb"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=kgQKet4V; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner --- include/linux/irqdomain_defs.h | 1 + 1 file changed, 1 insertion(+) --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -26,6 +26,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_DMAR, DOMAIN_BUS_AMDVI, DOMAIN_BUS_PCI_DEVICE_IMS, + DOMAIN_BUS_DEVICE_IMS, }; #endif /* _LINUX_IRQDOMAIN_DEFS_H */ From patchwork Mon Nov 21 14:39:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23852 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1641789wrr; Mon, 21 Nov 2022 07:05:18 -0800 (PST) X-Google-Smtp-Source: AA0mqf7nfDYX1jFynF+mD7GzimxPsEc1MsxlK19L7JeVxylBZghQl8nbf0JH0Ye6TMCfyag3aPYV X-Received: by 2002:a05:6402:1399:b0:461:53b0:2ac0 with SMTP id b25-20020a056402139900b0046153b02ac0mr16388378edv.153.1669043118161; Mon, 21 Nov 2022 07:05:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043118; cv=none; d=google.com; s=arc-20160816; b=ihs0uvhNLhMFlfOSHiYnjbvb7hNGgKoSbNCDwq17RTtfi1zbXPjPWmledCvpYmKrPY OjanWaXHNOBvSyQe9P8vEH8POfUUm27cqMwoUyGqx6mB0l8YF+R+U/jOaA0m6kc3hzBz 5KJnRDjH6cv3qtJ5zHkWKAUcFcF2TWflTzioGDlca6cNYqyzD6fZ7CIV+Akdd1d1wZx8 4LrpUC8BueyeqDM13zebB5yeXdD7TAe+xqV8jKLaTwWJwycu++B6W1IxWJEnhRtYc4Qf Sj6p/Lr+HjcH2HVjqgTwLJWwtJpQCYro5Bp+MdC+XkMgxFtbwbipzcR8HsZ+3TaIT13+ yrHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=+qksWd2+ccMmqLte5f9aPSVt++7qKd9jnyVMQkZ0blc=; b=Y0Uz6XnImr3zjfMxBgyWNiBIYAM7RcjZlTvtdNvQYAVCUDBXIhFu76/FJcBxF6qCdY ILncB487FqG3+U6bNi13jd7hzeiHF9otSC2o4B0N5+ANHC0ONYACYgAgK+R2MwskLD2J frNtes3VEmFcRFk0pIp6Tzjl/fqhkwyDVcIU1g+c17eSnfbK7hOMT/1VMmdlFQUTtkME aw5XRc0vIJeXC537Ezw2sVuXkZy10OiXf/IYHCOCSp0HXV8dFrIOP23g7Op9KDFTyLvF q+rrGUXM6IFp/Yub3twueO0oC+CxNjVVKEspFVmVz8CvpOa+uePErQT8l0i/AN4WfLU/ b9qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=xNNxpN26; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Jxt9EtE5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jt24-20020a170906dfd800b007317274bb0dsi7687513ejc.979.2022.11.21.07.04.17; Mon, 21 Nov 2022 07:05:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=xNNxpN26; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Jxt9EtE5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230035AbiKUOtG (ORCPT + 99 others); Mon, 21 Nov 2022 09:49:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232322AbiKUOrp (ORCPT ); Mon, 21 Nov 2022 09:47:45 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED255D32A1; Mon, 21 Nov 2022 06:41:51 -0800 (PST) Message-ID: <20221121140049.237988384@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041587; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+qksWd2+ccMmqLte5f9aPSVt++7qKd9jnyVMQkZ0blc=; b=xNNxpN26XOiNIK1Emk3fcyWh3Vb/rxCZ0KWmilAmnOPvM3r3PacwAhHwcxWLgmtpZHhkQT jP1VcrkI+iuvdmrHbvA47gHQfzgsy4m8umj+7PyAzo2FmgcCP1HMMMgv7T/3b08eUmVJeO sR4nlMurDfJwTe8mCfL51Bbz59fDcgzICgAnIdBOhAwBJW4H1hiPqpuoq3/23ArbJn7eSY RmHg7NUPNAeDkSD9MWAknTB0EIJXw7l5hRclFHMCrvG7uYh7odHdOGPR+T8RR0BHTYfrm9 QKc+AlIq/03LfRAjYZg57tSNUnnCp+/OV3jYzxpxwrwPhpOZee4bgaYgzpUzOA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041587; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=+qksWd2+ccMmqLte5f9aPSVt++7qKd9jnyVMQkZ0blc=; b=Jxt9EtE53tlRD9+hwUci8tAYYQ/g44FiV1TIMRiPipyRbRpVhKUZI8JvvGxXeO5KPFtp22 POKx8P2tmAR7O3DQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 15/40] irqchip/gic-msi-lib: Prepare for DEVICE MSI to replace platform MSI References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:47 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118556860239428?= X-GMAIL-MSGID: =?utf-8?q?1750118556860239428?= Add the prerequisites for DEVICE MSI into the shared select() and child domain init function. These domains are really trivial and just provide a custom irq chip callback to write the MSI message. Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-gic-msi-lib.c | 13 +++++++++++++ drivers/irqchip/irq-gic-msi-lib.h | 2 ++ 2 files changed, 15 insertions(+) --- a/drivers/irqchip/irq-gic-msi-lib.c +++ b/drivers/irqchip/irq-gic-msi-lib.c @@ -55,6 +55,19 @@ bool gic_msi_lib_init_dev_msi_info(struc pci_device_msi_mask_unmask_parent_enable(); break; + case DOMAIN_BUS_DEVICE_IMS: + /* + * Per device IMS should never have any MSI feature bits + * set. It's sole purpose is to create a dumb interrupt + * chip which has a device specific irq_write_msi_msg() + * callback. + */ + if (WARN_ON_ONCE(info->flags)) + return false; + + /* Core managed MSI descriptors */ + info->flags = MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | MSI_FLAG_FREE_MSI_DESCS; + break; default: /* * This should never be reached. See --- a/drivers/irqchip/irq-gic-msi-lib.h +++ b/drivers/irqchip/irq-gic-msi-lib.h @@ -15,6 +15,8 @@ #define MATCH_PCI_MSI (0) #endif +#define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) + int gic_msi_lib_irq_domain_select(struct irq_domain *d, struct irq_fwspec *fwspec, enum irq_domain_bus_token bus_token); From patchwork Mon Nov 21 14:39:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23853 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1641797wrr; Mon, 21 Nov 2022 07:05:19 -0800 (PST) X-Google-Smtp-Source: AA0mqf4mOysVvW/avwcimaHxLM4GbYIY+6FjwGCE4S/+vUgxiBQYSQzyypbDsWi1g1kiyLS0r6Fi X-Received: by 2002:a17:90a:7a82:b0:211:55d8:4cdd with SMTP id q2-20020a17090a7a8200b0021155d84cddmr20536417pjf.133.1669043118900; Mon, 21 Nov 2022 07:05:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043118; cv=none; d=google.com; s=arc-20160816; b=EjpRexWOWfIG6LJhc5aWiB4TUVHZ7BvlbsApPF58DdyUx710xsVIhM82inQ69F03Vd jiBy5za+Z6UmquEoA3JWPxRdHUoX24AJR2etzNk63VOCE3wtsQHjN/f/fYY3PleqbQrw tvtgdLgb1AJvPtJo0qlmgu4fgOUihyBrt91iuI8sLsxUsT1t0NTKy6EB1Fu3Tn2Dq5ud 6W3dOWG+NPSDTjIV5AJmVFiPPp0NldG8wZxaJ6D0DocrKRQCIyz6aqCcjaiz4bol7vyN 8FIRMGp9iAjXwomN541fR84P83THEwS1x15ugjFtqeEQAzTpL8Bg8+SmsZNRuWO5eF9O 5G3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=kl5jEFmZ6mV3MxctqQhK0mI7GqDB/127fsAWZEDHGQ4=; b=hh9EX3428YmKBiuIFPK2HZPos15Xp167D/SW0Fq4cenq3I7tgdN/RldOjBHMsWBTIx ZDOf+9EWIBLnHyb5m8LVqiD0+ChvnHuKfwSEYvXuSnGHUH5jDhYXvKJ2JL2j65/CR8PU bzlls+ZfLj6JeNBH7ahaa6mc9RqDmNugZDuH4iQBFYxcs3iziTWUimERq4vfWOxrl89B Qpm3B6yr/q+kvgVcAlxmmpEeLYIXmt+1OXbnileT727U680WKD3SbsWpxLklTlbTbbVm Q0v5csKRHap/E3IJMnpU0NQYx4bb8Y2TG7Zyo6rrpP2cijc5xRKjwrak+FUm1vOUUiSt LApw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="t/MsyzEB"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e2-20020aa78242000000b005633766252asi10592428pfn.313.2022.11.21.07.04.38; Mon, 21 Nov 2022 07:05:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="t/MsyzEB"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231793AbiKUOtK (ORCPT + 99 others); Mon, 21 Nov 2022 09:49:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232329AbiKUOrq (ORCPT ); Mon, 21 Nov 2022 09:47:46 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D35F9D3283; Mon, 21 Nov 2022 06:41:51 -0800 (PST) Message-ID: <20221121140049.301480611@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041588; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kl5jEFmZ6mV3MxctqQhK0mI7GqDB/127fsAWZEDHGQ4=; b=t/MsyzEBwE5k1Edq3y3kvTBANZV0O2ddSvfhvolvR+zZnU9MzXt6cYGo40UzFSOUtcjjul wETGPWwc45KGUGmH9nSYmRif8veDZxXnaZRBAkmvsiw3Dtr9MC5PulBoZwF7kdIN0N9L2t s5C+05g5r9xI+DArNrW/7oe1j2XN1eAHPiCbdMoFqlH1by7TiktOQCinkeUpxF1tVXoCU3 r3kvi6b+P9koiJ6WPCEZQMNrBxDjaJbDuCyr4QJbVR/nDf6bZvDaj12j7oI5o4ZQSwlJfe wHNNpmLe8Ix1Q4VpnS+dLvUkKNZCHj8qr255HVOXxUL9HrYBMPCTx65Kj1RXMA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041588; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=kl5jEFmZ6mV3MxctqQhK0mI7GqDB/127fsAWZEDHGQ4=; b=/2nHaNj8gHb80Ft70cE0eTktfhiSxxG04atdWQJIAxt6nK2X8oncIsGOW1zVDPUxa5g/1W /rsCxDJNiGoYwvDw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 16/40] platform-msi: Prepare for real per device domains References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:48 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118557349626261?= X-GMAIL-MSGID: =?utf-8?q?1750118557349626261?= Provide functions to create and remove per device MSI domains which replace the platform-MSI domains. The new model is that each of the devices which utilize platform-MSI gets now its private MSI domain which is "customized" in size and with a device specific function to write the MSI message into the device. This is the same functionality as platform-MSI but it avoids all the down sides of platform MSI, i.e. the extra ID book keeping, the special data structure in the msi descriptor. Further the domains are only created when the devices are really in use, so the burden is on the usage and not on the infrastructure. Fill in the domain template and provide two functions to init/allocate and remove a per device MSI domain. Until all users and parent domain providers are converted, the init/alloc function invokes the original platform-MSI code when the irqdomain which is associated to the device does not provide MSI parent functionality yet. Signed-off-by: Thomas Gleixner --- drivers/base/platform-msi.c | 98 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/msi.h | 4 + 2 files changed, 102 insertions(+) --- a/drivers/base/platform-msi.c +++ b/drivers/base/platform-msi.c @@ -13,6 +13,8 @@ #include #include +/* Begin of removal area. Once everything is converted over. Cleanup the includes too! */ + #define DEV_ID_SHIFT 21 #define MAX_DEV_MSIS (1 << (32 - DEV_ID_SHIFT)) @@ -349,3 +351,99 @@ int platform_msi_device_domain_alloc(str return msi_domain_populate_irqs(domain->parent, dev, virq, nr_irqs, &data->arg); } + +/* End of removal area */ + +/* Real per device domain interfaces */ + +/* + * This indirection can go when platform_device_ims_init_and_alloc_irqs() + * is switched to a proper irq_chip::irq_write_msi_msg() callback. Keep it + * simple for now. + */ +static void platform_msi_write_msi_msg(struct irq_data *d, struct msi_msg *msg) +{ + irq_write_msi_msg_t cb = d->chip_data; + + cb(irq_data_get_msi_desc(d), msg); +} + +static void platform_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) +{ + arg->desc = desc; + arg->hwirq = desc->msi_index; +} + +static const struct msi_domain_template platform_msi_template = { + .chip = { + .name = "pMSI", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_write_msi_msg = platform_msi_write_msi_msg, + /* The rest is filled in by the platform MSI parent */ + }, + + .ops = { + .set_desc = platform_msi_set_desc, + }, + + .info = { + .bus_token = DOMAIN_BUS_DEVICE_IMS, + }, +}; + +/** + * platform_device_ims_init_and_alloc_irqs - Initialize platform device IMS + * and allocate interrupts for @dev + * @dev: The device for which to allocate interrupts + * @nvec: The number of interrupts to allocate + * @write_msi_msg: Callback to write an interrupt message for @dev + * + * Returns: + * Zero for success, or an error code in case of failure + * + * This creates a MSI domain on @dev which has @dev->msi.domain as + * parent. The parent domain sets up the new domain. The domain has + * a fixed size of @nvec. The domain is managed by devres and will + * be removed when the device is removed. + * + * Note: For migration purposes this falls back to the original platform_msi code + * up to the point where all platforms have been converted to the MSI + * parent model. + */ +int platform_device_ims_init_and_alloc_irqs(struct device *dev, unsigned int nvec, + irq_write_msi_msg_t write_msi_msg) +{ + struct irq_domain *domain = dev->msi.domain; + int ret; + + if (!domain || !write_msi_msg) + return -EINVAL; + + /* Migration support. Will go away once everything is converted */ + if (!irq_domain_is_msi_parent(domain)) + return platform_msi_domain_alloc_irqs(dev, nvec, write_msi_msg); + + /* + * @write_msi_msg is stored in the resulting msi_domain_info::data. + * The underlying domain creation mechanism will assign that + * callback to the resulting irq chip. + */ + if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, + &platform_msi_template, + nvec, NULL, write_msi_msg)) + return -ENODEV; + + return msi_domain_alloc_irqs_range(dev, MSI_DEFAULT_DOMAIN, 0, nvec - 1); +} +EXPORT_SYMBOL_GPL(platform_device_ims_init_and_alloc_irqs); + +/** + * platform_device_ims_free_irqs_all - Free all interrupts for @dev + * @dev: The device for which to free interrupts + */ +void platform_device_ims_free_irqs_all(struct device *dev) +{ + msi_domain_free_irqs_all(dev, MSI_DEFAULT_DOMAIN); +} +EXPORT_SYMBOL_GPL(platform_device_ims_free_irqs_all); --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -649,6 +649,10 @@ int platform_msi_device_domain_alloc(str void platform_msi_device_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nvec); void *platform_msi_get_host_data(struct irq_domain *domain); +/* Per device platform MSI */ +int platform_device_ims_init_and_alloc_irqs(struct device *dev, unsigned int nvec, + irq_write_msi_msg_t write_msi_msg); +void platform_device_ims_free_irqs_all(struct device *dev); #endif /* CONFIG_GENERIC_MSI_IRQ */ /* PCI specific interfaces */ From patchwork Mon Nov 21 14:39:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23861 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1643651wrr; Mon, 21 Nov 2022 07:07:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf78AMWxZGVelASyj+GeiXo1C9qGSDaaJOMCCuf9M9fcRcf9MOdYi0tJ7VD49gzZWxtjP9vL X-Received: by 2002:aa7:cb09:0:b0:463:ff10:4ff with SMTP id s9-20020aa7cb09000000b00463ff1004ffmr5627537edt.290.1669043278508; Mon, 21 Nov 2022 07:07:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043278; cv=none; d=google.com; s=arc-20160816; b=z18nwBr/ZX0WZApIsOy6WjuYsLZlqNgu9oIxfmdx19oVwU4Hol7D9trqzJX9rY9gzp XEzSa60HsovpxTY1+hMFUu4skDEOcIYcOLqRNGgkZr3WHhYF6oV/dmjvHMjGLRDj30tI TfUQI9zQ8GX3+kt01w/GIaKSqJYkjqu+hPPr18HzVYctsyhtkuM4PqnqPlz6k4Hd8Kv7 XH9BZpss5O41pZSE4ynPPgYaXyRnwSlAXNROQAHAVOmML3zrBFN97Og4XUJPEkkYO5Qz DlMaLDR5HJogcvyR4hoMsZPBSk5iPB8VxFDsDz3tBFgpj25sJckVpe2gz2ssmrpY4HUZ aygA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=WmdB2qfbbOZDzyPsz/NXt+XoJ1l6mf2vgeHiaNbEoMk=; b=E3u6JwyslyDCpAMsqaQb46dt93d4YLY7fmhbnDZHpcG8OsZg9+YBlKN/eWSmZDu8OJ fJ+2Txakf/wO5Z8Q9TWyatWp4ssa+pdHgBDN4E1Gj249RO0ZmO2gQIPG1QP+vonu1QEr fiEy1yPaD3D14LCdbXBjcSUAjAKBzOrXIQZ7F010v0v+tXUmg9nYH5ESMUOHu1bh+JU8 EP+NwYHPBQ9GZxE50iZD/dxCu8AbuJZGoMyfUXQztXikI+2mlg0eQXTSHq+li8BJ20vh n9wKgkctNY6nuGGOh8Nh8bT7OnXZ4fYg+ywYlor0jwJt3EbYTQlmRHdMzMmaAxLYDg0h OGbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3XdDjRAf; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4jBwfkJE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gs30-20020a1709072d1e00b00780def41dc4si10497086ejc.527.2022.11.21.07.07.16; Mon, 21 Nov 2022 07:07:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3XdDjRAf; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4jBwfkJE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229662AbiKUOuH (ORCPT + 99 others); Mon, 21 Nov 2022 09:50:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229832AbiKUOsa (ORCPT ); Mon, 21 Nov 2022 09:48:30 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2D35D39EF; Mon, 21 Nov 2022 06:42:16 -0800 (PST) Message-ID: <20221121140049.363858787@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041590; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WmdB2qfbbOZDzyPsz/NXt+XoJ1l6mf2vgeHiaNbEoMk=; b=3XdDjRAfvWJaoSFapB48hY3JPrLaN/Z7q4sEmU3KSFTXTFycWPRSkgiCbGNjPkuCqDf8Vn Z1AaTBpUaFzB4LKR8oIgRN20xnYFmsqV3kt2YF0VFNtPpZII5G/qYVnb1ioagvBSaYlzGP n389cx4FFDVw9vew4D6ur3DiIZi7y0fTvtNTxtdbAslCy+DFj9CcwtnsY8RcrfpLG00+6B vNQXlt+iLFj406UqJDWPuA5SMmN+W7xXOjTzF8cQ5rYVKpcnObLvPCbYolGRCWOYaq+YAs ufrdRiPyckN4LJddBGhbFnq8hy63WzypJX4hRk09L1q3ibFfNAjbUKWtPX3BVQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041590; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WmdB2qfbbOZDzyPsz/NXt+XoJ1l6mf2vgeHiaNbEoMk=; b=4jBwfkJEKdyQ2OzLVskrhNL1aNHEnG09AdIvyb8YAtM+9AjlGulHq05MxUQ4vI0hVPu6lG rR6+bZPDs+0smpDw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 17/40] irqchip: Convert all platform MSI users to the new API References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:49 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118724648438961?= X-GMAIL-MSGID: =?utf-8?q?1750118724648438961?= Switch all the users of the platform MSI domain over to invoke the new interfaces which branch to the original platform MSI functions when the irqdomain associated to the caller device does not yet provide MSI parent functionality. No functional change. Signed-off-by: Thomas Gleixner Cc: Vinod Koul Cc: Sinan Kaya Cc: Andy Gross Cc: Bjorn Andersson Cc: Mark Rutland --- drivers/dma/mv_xor_v2.c | 8 ++++---- drivers/dma/qcom/hidma.c | 6 +++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 5 +++-- drivers/mailbox/bcm-flexrm-mailbox.c | 8 ++++---- drivers/perf/arm_smmuv3_pmu.c | 4 ++-- 5 files changed, 16 insertions(+), 15 deletions(-) --- a/drivers/dma/mv_xor_v2.c +++ b/drivers/dma/mv_xor_v2.c @@ -764,8 +764,8 @@ static int mv_xor_v2_probe(struct platfo goto disable_reg_clk; } - ret = platform_msi_domain_alloc_irqs(&pdev->dev, 1, - mv_xor_v2_set_msi_msg); + ret = platform_device_ims_init_and_alloc_irqs(&pdev->dev, 1, + mv_xor_v2_set_msi_msg); if (ret) goto disable_clk; @@ -868,7 +868,7 @@ static int mv_xor_v2_probe(struct platfo xor_dev->desc_size * MV_XOR_V2_DESC_NUM, xor_dev->hw_desq_virt, xor_dev->hw_desq); free_msi_irqs: - platform_msi_domain_free_irqs(&pdev->dev); + platform_device_ims_free_irqs_all(&pdev->dev); disable_clk: clk_disable_unprepare(xor_dev->clk); disable_reg_clk: @@ -888,7 +888,7 @@ static int mv_xor_v2_remove(struct platf devm_free_irq(&pdev->dev, xor_dev->irq, xor_dev); - platform_msi_domain_free_irqs(&pdev->dev); + platform_device_ims_free_irqs_all(&pdev->dev); tasklet_kill(&xor_dev->irq_tasklet); --- a/drivers/dma/qcom/hidma.c +++ b/drivers/dma/qcom/hidma.c @@ -697,7 +697,7 @@ static void hidma_free_msis(struct hidma devm_free_irq(dev, virq, &dmadev->lldev); } - platform_msi_domain_free_irqs(dev); + platform_device_ims_free_irqs_all(dev); #endif } @@ -707,8 +707,8 @@ static int hidma_request_msi(struct hidm #ifdef CONFIG_GENERIC_MSI_IRQ int rc, i, virq; - rc = platform_msi_domain_alloc_irqs(&pdev->dev, HIDMA_MSI_INTS, - hidma_write_msi_msg); + rc = platform_device_ims_init_and_alloc_irqs(&pdev->dev, HIDMA_MSI_INTS, + hidma_write_msi_msg); if (rc) return rc; --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3122,7 +3122,8 @@ static int arm_smmu_update_gbpa(struct a static void arm_smmu_free_msis(void *data) { struct device *dev = data; - platform_msi_domain_free_irqs(dev); + + platform_device_ims_free_irqs_all(dev); } static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) @@ -3163,7 +3164,7 @@ static void arm_smmu_setup_msis(struct a } /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */ - ret = platform_msi_domain_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg); + ret = platform_device_ims_init_and_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg); if (ret) { dev_warn(dev, "failed to allocate MSIs - falling back to wired irqs\n"); return; --- a/drivers/mailbox/bcm-flexrm-mailbox.c +++ b/drivers/mailbox/bcm-flexrm-mailbox.c @@ -1591,8 +1591,8 @@ static int flexrm_mbox_probe(struct plat } /* Allocate platform MSIs for each ring */ - ret = platform_msi_domain_alloc_irqs(dev, mbox->num_rings, - flexrm_mbox_msi_write); + ret = platform_device_ims_init_and_alloc_irqs(dev, mbox->num_rings, + flexrm_mbox_msi_write); if (ret) goto fail_destroy_cmpl_pool; @@ -1645,7 +1645,7 @@ static int flexrm_mbox_probe(struct plat fail_free_debugfs_root: debugfs_remove_recursive(mbox->root); - platform_msi_domain_free_irqs(dev); + platform_device_ims_free_irqs_all(dev); fail_destroy_cmpl_pool: dma_pool_destroy(mbox->cmpl_pool); fail_destroy_bd_pool: @@ -1661,7 +1661,7 @@ static int flexrm_mbox_remove(struct pla debugfs_remove_recursive(mbox->root); - platform_msi_domain_free_irqs(dev); + platform_device_ims_free_irqs_all(dev); dma_pool_destroy(mbox->cmpl_pool); dma_pool_destroy(mbox->bd_pool); --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -685,7 +685,7 @@ static void smmu_pmu_free_msis(void *dat { struct device *dev = data; - platform_msi_domain_free_irqs(dev); + platform_device_ims_free_irqs_all(dev); } static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) @@ -715,7 +715,7 @@ static void smmu_pmu_setup_msi(struct sm if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI)) return; - ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); + ret = platform_device_ims_init_and_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg); if (ret) { dev_warn(dev, "failed to allocate MSIs\n"); return; From patchwork Mon Nov 21 14:39:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23865 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1644891wrr; Mon, 21 Nov 2022 07:09:41 -0800 (PST) X-Google-Smtp-Source: AA0mqf44zEillxJr47TkPHWIIVVu5d7+BMJIC3YYdQsfzqCEoYFTznIjHrhTpvsv/Dn0JV1EL0si X-Received: by 2002:a17:906:504:b0:7b5:2d9f:4019 with SMTP id j4-20020a170906050400b007b52d9f4019mr6619149eja.536.1669043381120; Mon, 21 Nov 2022 07:09:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043381; cv=none; d=google.com; s=arc-20160816; b=GqePzxwkx4SY79NLoQmpcYGl2XbkUPdFFfLWMZIqy9eHpMknaZerK0eQ4E3IrBB7KD AMKL1I7nhFBh+KchceHxlZ8BVUwa4DwsJyT5O8aPa/I+KFnyJ5qkfBqJpSgaCqPov+3/ /hHJaQjVbdupAcuL7NAnZpUAxE5KnW4Mp8nDwBcr8bHzbqE9aopfdZjUaaDcElmpOPJW 1ox3eAVFH6XEpjRqQCTr4H8QzA5a9PNrLuRoVZ5/mKIfECKxtDyHpgVFxm39SKtBCvsa +BTgp0YKcxeNEW9Yvg01WeElzLmVXAxocldQQ275I//9jGl7UIdxpJ5zvSRl6aCIijA5 +B1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ZjMS9WKZ8Nf7BBjmdJgqdh2U6M/tG1SOi5dk7E2nC6I=; b=OgZBXxQEb+t8PAYB+ct6uydAFK/damQgohHdrYTlpKc/YTrywLba+koc4IljQI4uIa H/pWch1pDY7B3lDyooStbG9u5KBR31o/zexZPGiw8/XTnBP4SPjw4myXseoGbpGAXfqR DxIu3rBQTO58NmeCULf3EomD6e/+WNQZ9Pe59GAMoOMkEv4eDi6gUlvmDBn30nIavyAe IVu4VS57ZghTu5sMoEzu9PQfYH+FK0sH/BtdL94XPT3SiTLSKhKwVasV/+iwqoheJZ6+ TdSippDUUPWM1MLkrTxErAvdSL2D72mExk1/Q66TB4D19lqbn2RCbiOrz+8YH5K044NK DFIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=MDIYKt3e; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=I1Ve0rVu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hz1-20020a1709072ce100b0078e0e866a4dsi9589302ejc.682.2022.11.21.07.09.14; Mon, 21 Nov 2022 07:09:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=MDIYKt3e; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=I1Ve0rVu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231526AbiKUOt6 (ORCPT + 99 others); Mon, 21 Nov 2022 09:49:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231583AbiKUOsU (ORCPT ); Mon, 21 Nov 2022 09:48:20 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8A34D39DF; Mon, 21 Nov 2022 06:42:15 -0800 (PST) Message-ID: <20221121140049.428236986@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041591; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZjMS9WKZ8Nf7BBjmdJgqdh2U6M/tG1SOi5dk7E2nC6I=; b=MDIYKt3etoFIKinLV4uhdFA14rWeIDqUD4/mRKjbmfM+4Iqd/Px6KJsQQe/7+IWoPySsgz 0qW5kLK27fgOaV4YCrwZGWOwvmYFgzCMWQHARLfw8HBTGj0IeFkVdsRSdvKZ5GaYTzUt2p yRG/oM9ROxMOQM+uTYbveTKZkpE0wBfhPEVssvJLcnG4yvFkDAcsdPyvPKT7s5EdfMuCLJ 7U57SCDUKTy03LNV3E5Xxr+wQDUNVdVCRznP6UPupga3oC2JHm/WbpdtgnbNhQTkvKhOrY Pp1q3SrH0gNVEYvtvpImy2evDpqQS5Q0VZGk1W42qZ/rLsTasvzO3gx68GQ1Fg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041591; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ZjMS9WKZ8Nf7BBjmdJgqdh2U6M/tG1SOi5dk7E2nC6I=; b=I1Ve0rVuhE8WJ3sP02XIi7u8xPj1s7abVf0jjZdXnWbmsX1S0FNA8HTfl0exqssq029R+O QJqtB3V/lbjVchDQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 18/40] genirq/msi: Provide optional translation op References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:51 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118832392240532?= X-GMAIL-MSGID: =?utf-8?q?1750118832392240532?= irq_create_fwspec_mapping() requires translation of the firmware spec to a hardware interrupt number and the trigger type information. Wired interrupts which are connected to a wire to MSI bridge, like MBIGEN are allocated that way. So far MBIGEN provides a regular irqdomain which then hooks backwards into the MSI infrastructure. That's an unholy mess and will be replaced with per device MSI domains which are regular MSI domains. Interrupts on MSI domains are not supported by irq_create_fwspec_mapping(), but for making the wire to MSI bridges sane it makes sense to provide a special allocation/free interface in the MSI infrastructure. That avoids the backdoors into the core MSI allocation code and just shares all the regular MSI infrastructure. Provide an optional translation callback in msi_domain_ops which can be utilized by these wire to MSI bridges. No other MSI domain should provide a translation callback. The default translation callback of the MSI irqdomains will warn when it is invoked on a non-prepared MSI domain. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 5 +++++ kernel/irq/msi.c | 15 +++++++++++++++ 2 files changed, 20 insertions(+) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -393,6 +393,7 @@ bool arch_restore_msi_irqs(struct pci_de struct irq_domain; struct irq_domain_ops; struct irq_chip; +struct irq_fwspec; struct device_node; struct fwnode_handle; struct msi_domain_info; @@ -412,6 +413,8 @@ struct msi_domain_info; * function. * @msi_post_free: Optional function which is invoked after freeing * all interrupts. + * @msi_translate: Optional translate callback to support the odd wire to + * MSI bridges, e.g. MBIGEN * * @get_hwirq, @msi_init and @msi_free are callbacks used by the underlying * irqdomain. @@ -449,6 +452,8 @@ struct msi_domain_ops { struct device *dev); void (*msi_post_free)(struct irq_domain *domain, struct device *dev); + int (*msi_translate)(struct irq_domain *domain, struct irq_fwspec *fwspec, + irq_hw_number_t *hwirq, unsigned int *type); }; /** --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -772,11 +772,26 @@ static void msi_domain_free(struct irq_d irq_domain_free_irqs_top(domain, virq, nr_irqs); } +static int msi_domain_translate(struct irq_domain *domain, struct irq_fwspec *fwspec, + irq_hw_number_t *hwirq, unsigned int *type) +{ + struct msi_domain_info *info = domain->host_data; + + /* + * This will catch allocations through the regular irqdomain path except + * for MSI domains which really support this, e.g. MBIGEN. + */ + if (!info->ops->msi_translate) + return -ENOTSUPP; + return info->ops->msi_translate(domain, fwspec, hwirq, type); +} + static const struct irq_domain_ops msi_domain_ops = { .alloc = msi_domain_alloc, .free = msi_domain_free, .activate = msi_domain_activate, .deactivate = msi_domain_deactivate, + .translate = msi_domain_translate, }; static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info, From patchwork Mon Nov 21 14:39:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23855 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1642696wrr; Mon, 21 Nov 2022 07:06:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf61LGVfCpGAJax9aw18LiwHWjS+wzWCtXePYCZljKhMK6X0m3Zqvfn2XQiHpqYFi2v2lsQk X-Received: by 2002:a17:906:4e4e:b0:7ae:e6ac:2427 with SMTP id g14-20020a1709064e4e00b007aee6ac2427mr15912553ejw.345.1669043188743; Mon, 21 Nov 2022 07:06:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043188; cv=none; d=google.com; s=arc-20160816; b=quASUyWNgK0+/251cY1mKN9O9hXcMXC0Rco4RGIeTSc9rsl0QeFAQUWU3JJATXdcUF xRZhH8A6ze99LeiRfaicEghCGUD7NfF4T0ubVbTKqa3nIFdPPuZ82+nyjKKDd/Nf3sZO HSm/djnu90Pk/5qR7fdNRi9Rt297zC76DnTZQlRIUbjoRjQ3DVIhHvY7ib1jYBw/RlxD 4BFfAiSCBiR06rnLWzh2RCfD6AKyeeXBstSNRNodaMSJdVu0iYeMG3jRUQYkv8p2TXGP zzI2uTI3yTUUodLJSWhEGRYBL7TinIzFrShD46BLQkO1ST8YZpCkl/m9wA7MIOGJuiHG zkZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=MqSNqTk6zSn2/CxqHu1Zk5vIICcROEec5cXqFROUsAQ=; b=jVXFsFtdzUE0SaO9YRG5ME6FQ4aaNDPp1T4qcXE+ZKh673X1OYsDi9OPsISTe3c4e8 TpJgjU7sfXCHBOLWAvTvvjNIXRPfOhnC+JwqXawh19dGxL3YcI6w7a0vXWACnsN5kai0 LvyI5tdfdg/g/dWpI6PhEviK014lk52zjKoW0+lA4k1Bn/1g68DsMn+XhBZxx+MxQbaN JfRd/ph3C5mbjGKrZlLvvTFjgquZFjV+oTHcth4WywlaHsSBpT/wIUAi6kCeNRuH5qeO 3/5fvQ+VmUYNerEDJqY4BIner8ORuoVIh384LQX/AvlAANw/LOuFRgiPd8M8Kb0TPVsA 3ERg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=MED9eLTL; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Anqh6ewU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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No functional change. Signed-off-by: Thomas Gleixner --- kernel/irq/msi.c | 76 +++++++++++++++++++++++++++++++------------------------ 1 file changed, 43 insertions(+), 33 deletions(-) --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1465,34 +1465,10 @@ int msi_domain_alloc_irqs_all_locked(str return msi_domain_alloc_locked(dev, &ctrl); } -/** - * msi_domain_alloc_irq_at - Allocate an interrupt from a MSI interrupt domain at - * a given index - or at the next free index - * - * @dev: Pointer to device struct of the device for which the interrupts - * are allocated - * @domid: Id of the interrupt domain to operate on - * @index: Index for allocation. If @index == %MSI_ANY_INDEX the allocation - * uses the next free index. - * @affdesc: Optional pointer to an interrupt affinity descriptor structure - * @icookie: Optional pointer to a domain specific per instance cookie. If - * non-NULL the content of the cookie is stored in msi_desc::data. - * Must be NULL for MSI-X allocations - * - * This requires a MSI interrupt domain which lets the core code manage the - * MSI descriptors. - * - * Return: struct msi_map - * - * On success msi_map::index contains the allocated index number and - * msi_map::virq the corresponding Linux interrupt number - * - * On failure msi_map::index contains the error code and msi_map::virq - * is %0. - */ -struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, unsigned int index, - const struct irq_affinity_desc *affdesc, - union msi_instance_cookie *icookie) +static struct msi_map __msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, + unsigned int index, + const struct irq_affinity_desc *affdesc, + union msi_instance_cookie *icookie) { struct msi_ctrl ctrl = { .domid = domid, .nirqs = 1, }; struct msi_domain_info *info; @@ -1501,17 +1477,16 @@ struct msi_map msi_domain_alloc_irq_at(s struct msi_desc *desc; int ret; - msi_lock_descs(dev); domain = msi_get_device_domain(dev, domid); if (!domain) { map.index = -ENODEV; - goto unlock; + return map; } desc = msi_alloc_desc(dev, 1, affdesc); if (!desc) { map.index = -ENOMEM; - goto unlock; + return map; } if (icookie) @@ -1520,7 +1495,7 @@ struct msi_map msi_domain_alloc_irq_at(s ret = msi_insert_desc(dev, desc, domid, index); if (ret) { map.index = ret; - goto unlock; + return map; } ctrl.first = ctrl.last = desc->msi_index; @@ -1534,7 +1509,42 @@ struct msi_map msi_domain_alloc_irq_at(s map.index = desc->msi_index; map.virq = desc->irq; } -unlock: + return map; +} + +/** + * msi_domain_alloc_irq_at - Allocate an interrupt from a MSI interrupt domain at + * a given index - or at the next free index + * + * @dev: Pointer to device struct of the device for which the interrupts + * are allocated + * @domid: Id of the interrupt domain to operate on + * @index: Index for allocation. If @index == %MSI_ANY_INDEX the allocation + * uses the next free index. + * @affdesc: Optional pointer to an interrupt affinity descriptor structure + * @icookie: Optional pointer to a domain specific per instance cookie. If + * non-NULL the content of the cookie is stored in msi_desc::data. + * Must be NULL for MSI-X allocations + * + * This requires a MSI interrupt domain which lets the core code manage the + * MSI descriptors. + * + * Return: struct msi_map + * + * On success msi_map::index contains the allocated index number and + * msi_map::virq the corresponding Linux interrupt number + * + * On failure msi_map::index contains the error code and msi_map::virq + * is %0. + */ +struct msi_map msi_domain_alloc_irq_at(struct device *dev, unsigned int domid, unsigned int index, + const struct irq_affinity_desc *affdesc, + union msi_instance_cookie *icookie) +{ + struct msi_map map; + + msi_lock_descs(dev); + map = __msi_domain_alloc_irq_at(dev, domid, index, affdesc, icookie); msi_unlock_descs(dev); return map; } From patchwork Mon Nov 21 14:39:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23854 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1642504wrr; Mon, 21 Nov 2022 07:06:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf4RQIpx1XvaXshWvuUCbf7pKYAwgcmtbCnNICmYvN33LbGrTxrt/eXUecGayDq2kDt2MwbK X-Received: by 2002:a17:906:814f:b0:7b2:86d6:292d with SMTP id z15-20020a170906814f00b007b286d6292dmr2476753ejw.714.1669043177694; Mon, 21 Nov 2022 07:06:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043177; cv=none; d=google.com; s=arc-20160816; b=PCNUxVAsUpALofJGDgDzu5UCTjgyJIToQ/H2bUWmJxw0df/Tz60p0fDSgXcf6isobZ 3gJ4YeE0EcnX78WddCeVyPtQ7JMfZbPh4oz8K1Tmp9XNa0XmmnLQYe6tLYbJc1z4p+Kx 2NUjTZHOp4tCyRGt39dv2OIrO+yeMBohEeIH8UnTW/mtEU49SKbrveeGZoLxMJBugYDD RkvtuolMceF3qQIYynf8hR9aKIIlVMbJt/yWUIVqoM/LBod4FWuLompjYzoTAirmuDZI /DiaKueuTJjnW7Q3x2K0Idf1s87F9SXU0s0Z14Nwr5MV1HZ3B6R9eUB0R0hFWqtwn0Zl Ba7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=NtvhSh2f4pTpvLMutbIVG+VUzt3UJNiGBzd/l7fMSPA=; b=ohdkVz71tyt79HW/HckeegsxxTIDBmylxHsTl7EnVcpxqEO3Zfw94y93XDlY5OoTER 0rbD6M/xVZ2iHrLUG+Jx+xiGJyKfMGnqqmCuffHWODptsm3MIiyckEYy7bcAnlXYlX1Q 7kGMzX0x0QOFUDkHXTCk2tiWKLvnHdihZy4G7NdeR/qkRsfCus6JwcoUEWgu3nMmijlZ Eom/h5wEPs4ElHoayAo3/rBh2L5uBkjOKdn88fhWPdr5OAeJfpylgS1aOcsQ/LmjUYjB n2QxoKzOSSNSyGk0oyLsLEvG/J+eji4GN1UTFlO4pwzreoQaFOr5UixJNWsxLG69dKz3 hyHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="Z5N/sHGs"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=1Yg4NpVz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner --- include/linux/irqdomain_defs.h | 1 + 1 file changed, 1 insertion(+) --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -27,6 +27,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_AMDVI, DOMAIN_BUS_PCI_DEVICE_IMS, DOMAIN_BUS_DEVICE_IMS, + DOMAIN_BUS_WIRED_TO_MSI, }; #endif /* _LINUX_IRQDOMAIN_DEFS_H */ From patchwork Mon Nov 21 14:39:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23858 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1643019wrr; Mon, 21 Nov 2022 07:07:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf5WW7NVUD4KHD6hLC4yZ2XqKY/EWOSYpqb1UxkcD7+GfIJp97ZvRRzO02ad0irWZs1ZxQRp X-Received: by 2002:a17:906:9c47:b0:78d:8fa5:c326 with SMTP id fg7-20020a1709069c4700b0078d8fa5c326mr4070384ejc.25.1669043220110; Mon, 21 Nov 2022 07:07:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043220; cv=none; d=google.com; s=arc-20160816; b=kHX1AJRHfQg+uX3fTxqdo4/W8kGxtfLU9ZSdca+wTgd3A2Iy9JBa7C/kKfd8x2xlOH PkLBKS6sf95uqMqwdAKsyy7zri96KBee5iInas0ZtOxZ2JjAhhmtnAXjGVifizh5ttWx w2t/KaX1vDFOCg+aJxU/kX28ooorX5RSXzKRgY5axEhjS4SjWqO16qVJPQoZqsdRrO9Y RWZhVbbor/p+vL+XUNgBrgSGtSCVYkgyyvox66RwxJjDO/+1scEd2/lfIFIQXa5nYCoa 01S70Iksa3SZovA6vUkS+ec1gG8j/2EjO7Pg+4xx2z5e9MWylvUlOS+6W3SQJnq2xtsu s76A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=JA4DJhkL/SLZbiCPUtuJ/m0vEuiHsTx0BFOI4LdR10Q=; b=Iln/zkQftHASvaHrisFXaw8VWin2T9OxiQG7BMIAZgoAZ0aobolH8up0aaJXm+t/un LemV7Wi6UbsaEcN5+YV+doJ+l/MvEnJasUvYGKa4+22Uxif0xYZyZJF4sHIgUHeVvzNa GWsBJ7DOKsjlwovEns32hYlknCSbbOTQRxsLx/5pbNwDG7CjhDiH9DrMkqYURFcY+LTo n1LXvgxPfNYpXkGx7JF1sYn/KPVk+FPNp5lWWA0mZ1bgVdWxp2hZBTeB4ECpX1oUsu4F dD1E+gD8kp4Xi5wl3WUYF/ug1Bx5fY0Bm07BprrgPN3aEKomg1IVAQCmpTeSGHJYv608 fk+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="ydxHf/DS"; dkim=neutral (no key) header.i=@linutronix.de header.b=tpDw1REh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t15-20020a056402524f00b0046714f73377si10202086edd.293.2022.11.21.07.06.11; Mon, 21 Nov 2022 07:07:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="ydxHf/DS"; dkim=neutral (no key) header.i=@linutronix.de header.b=tpDw1REh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231297AbiKUOtu (ORCPT + 99 others); Mon, 21 Nov 2022 09:49:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232539AbiKUOsO (ORCPT ); Mon, 21 Nov 2022 09:48:14 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86B15D33B9; Mon, 21 Nov 2022 06:42:10 -0800 (PST) Message-ID: <20221121140049.617825672@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041595; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JA4DJhkL/SLZbiCPUtuJ/m0vEuiHsTx0BFOI4LdR10Q=; b=ydxHf/DSO9NqBzlSdDCOGZV8yc29f1kRL496Hy5wKB99tucPeKGC07lk3cKpyK9+2COl8c hjpk4rku7hZme1xQb60Ze8od18AYw/U/L2FQTdDLhNWxF1q2REtqR5/VICsDuxiJDB+qC0 lePu9FthiNaXK0Rayd8iIfrfZy6hntLOUUWK3SvBG0wHXaB3rlJfUg+mmaV1yVMogOQ0qO iyNdELpqvPfrCQ2G9j99NQ/+0mbIKlUkx7U34Vo67IglWB5tvwZKq+IEfLuluvvIjHQSQs ovcOyuCpqFarEwyiIVojI+sCJBBvrZpvQMmJdRhtj7dFDiaAwRJeSDubKzD7Wg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041595; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JA4DJhkL/SLZbiCPUtuJ/m0vEuiHsTx0BFOI4LdR10Q=; b=tpDw1REhwrgyCWZKJtswkMSb0d8Ir1QxPnOwIaV2QLUMOPSg/Ophl8ZWx4MgtiwRW5aUTF J3CTK4CKHP0XrJCw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 21/40] genirq/msi: Optionally use dev->fwnode for device domain References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:54 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118663911727740?= X-GMAIL-MSGID: =?utf-8?q?1750118663911727740?= To support wire to MSI domains via the MSI infrastructure it is required to use the firmware node of the device which implements this for creating the MSI domain. Otherwise the existing firmware match mechanisms to find the correct irqdomain for a wired interrupt which is connected to a wire to MSI bridge would fail. This cannot be used for the general case because not all devices provide firmware nodes and all regular per device MSI domains are directly associated to the device and have not be searched for. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 2 ++ kernel/irq/msi.c | 20 ++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -536,6 +536,8 @@ enum { * handled in the core MSI code. */ MSI_FLAG_NOMASK_QUIRK = (1 << 7), + /* Use dev->fwnode for MSI device domain creation */ + MSI_FLAG_USE_DEV_FWNODE = (1 << 8), /* Mask for the generic functionality */ MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0), --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -998,9 +998,9 @@ bool msi_create_device_irq_domain(struct void *chip_data) { struct irq_domain *domain, *parent = dev->msi.domain; - const struct msi_parent_ops *pops; + struct fwnode_handle *fwnode, *fwnalloced = NULL; struct msi_domain_template *bundle; - struct fwnode_handle *fwnode; + const struct msi_parent_ops *pops; if (!irq_domain_is_msi_parent(parent)) return false; @@ -1023,7 +1023,19 @@ bool msi_create_device_irq_domain(struct pops->prefix ? : "", bundle->chip.name, dev_name(dev)); bundle->chip.name = bundle->name; - fwnode = irq_domain_alloc_named_fwnode(bundle->name); + /* + * Using the device firmware node is required for wire to MSI + * device domains so that the existing firmware results in a domain + * match. + * All other device domains like PCI/MSI use the named firmware + * node as they are not guaranteed to have a fwnode. They are never + * looked up and always handled in the context of the device. + */ + if (bundle->info.flags & MSI_FLAG_USE_DEV_FWNODE) + fwnode = dev->fwnode; + else + fwnode = fwnalloced = irq_domain_alloc_named_fwnode(bundle->name); + if (!fwnode) goto free_bundle; @@ -1050,7 +1062,7 @@ bool msi_create_device_irq_domain(struct fail: msi_unlock_descs(dev); free_fwnode: - kfree(fwnode); + kfree(fwnalloced); free_bundle: kfree(bundle); return false; From patchwork Mon Nov 21 14:39:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23856 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1642821wrr; Mon, 21 Nov 2022 07:06:43 -0800 (PST) X-Google-Smtp-Source: AA0mqf79WMecScsxNZQy0sNWrBJ0Ne+DBv5FAxd+JdxXentkFh9ECi2fLAmA/ST6No1bIV0Pb/Bo X-Received: by 2002:a2e:87ce:0:b0:277:ddf:f476 with SMTP id v14-20020a2e87ce000000b002770ddff476mr5993893ljj.432.1669043203450; Mon, 21 Nov 2022 07:06:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043203; cv=none; d=google.com; s=arc-20160816; b=VNxT1686SsxdB1DYXzslMUp8NstyKpqkZTwcQUh39SHaJo1giVXcTOd1/qtg/JyuF7 SCEzLv887epUNZUb5HJdHF8wvh1AqlONDm7XB6OAmDe+xQ+f96pZADU8Wcl0qucBrz+Z PgdI8uPPIYxcuz+kAnxKvny1PKrpjrQ6VuqtPwdFxsCEUeaYqFtUBBfRmi9EZIe3HKHR CuD1mjHh1NsvWbqPs9YI3O+6cuNZyaG4jtLcg/TjsrmYFqwCqx7GISgFUajEfXJiXUeL Q7P6WgAmYzNyRi1lRkvWDM0RvuzJ3AunUnR423zzzXdXLIYKLUCOzKybcyt7W6mL/eYk okMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=fNlJq7eUueydjyHA34mJBe9PSXy3iovJN7ArQPlOsWU=; b=nlst53KjbteZCwGz0qVsQkwJs51ft45EvQ16pDbnFAPIkgEp51+OI+hZ5d1HujILRh T/Ahm3qcr5L067aQmNa+SwpVj04Rwz29qt/7Y+uF2ozSzTh5ts9CX61Ia6CHvs0OrR+R 0LPvMUz2GxbrbgbZVCyCUGLXY0tAiKMbnjDddSPDBwDdWhCmGiOT4ZfX2IJ5F4VX/IoS 9jgwR75aIkXeJ667KecqcBkvOp9wEoWnqsGY3F2xhRovBR6Bqjl8hJ8gGfHzEdFVHe8L dar1DDySsqw8KBdNy4xqD2tBY/GkKTLJ85+oCJ0rr1wQR9hRjya045uAGJk55LMrSLhH cvCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=R66Bn3oM; dkim=neutral (no key) header.i=@linutronix.de header.b=8EZXOY4u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cs13-20020a170906dc8d00b007ae83c51922si10559394ejc.45.2022.11.21.07.05.58; Mon, 21 Nov 2022 07:06:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=R66Bn3oM; dkim=neutral (no key) header.i=@linutronix.de header.b=8EZXOY4u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231388AbiKUOtr (ORCPT + 99 others); Mon, 21 Nov 2022 09:49:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232533AbiKUOsO (ORCPT ); Mon, 21 Nov 2022 09:48:14 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95AE8D33B8; Mon, 21 Nov 2022 06:42:09 -0800 (PST) Message-ID: <20221121140049.679827689@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041596; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=fNlJq7eUueydjyHA34mJBe9PSXy3iovJN7ArQPlOsWU=; b=R66Bn3oMfKbAtRRfMMszVlBS+aGiqDqLdJzWQVM7YC9/DMBe6MNJKW7bMy8QT/0z0RCDdE oaju4mmWCHRGR/tiMvp5qEQCni0VBKIuXN4EjHphh9slImL/oWrNgH3kKOHlRZWe0SYNi0 13mPES8l9aOkXsyk88Uj8g4rm1aXrB8TikYqTgEZzpnjwDjjrYH6gydH4jj6Lcys5jDsUh ulXkLA5eyvAzwWDLYNIw59E12iqnwh9et+i8C0H83k4Qh+iN1x1Xa/r1ii8or9BoZA3XfI vRc7b7zghEEz9r37fw4mit2QEG0Z01Fj7DM13ie0CIZNJESChT0dT15oZPE/9Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041596; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=fNlJq7eUueydjyHA34mJBe9PSXy3iovJN7ArQPlOsWU=; b=8EZXOY4u5eB2hDqCFbU5zgotL72sPCtlKFZCE3GO3oA1y1NhwRQwlQSE32pIYk8sv8Wwx6 Z6WW4edgQ7gcI7CQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 22/40] genirq/msi: Provide allocation/free functions for "wired" MSI interrupts References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:56 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118646025785653?= X-GMAIL-MSGID: =?utf-8?q?1750118646025785653?= To support wire to MSI bridges proper in the MSI core infrastructure it is required to have separate allocation/free interfaces which can be invoked from the regular irqdomain allocaton/free functions. The mechanism for allocation is: - Allocate the next free MSI descriptor index in the domain - Store the hardware interrupt number and the trigger type which was extracted by the irqdomain core from the firmware spec in the MSI descriptor device cookie so it can be retrieved by the underlying interrupt domain and interrupt chip - Use the regular MSI allocation mechanism for the newly allocated index which returns a fully initialized Linux interrupt on succes This works because: - the domains have a fixed size - each hardware interrupt is only allocated once - the underlying domain does not care about the MSI index it only cares about the hardware interrupt number and the trigger type The free function looks up the MSI index in the MSI descriptor of the provided Linux interrupt number and uses the regular index based free functions of the MSI core. Signed-off-by: Thomas Gleixner --- include/linux/irqdomain.h | 17 +++++++++++ kernel/irq/msi.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -634,6 +634,23 @@ static inline bool irq_domain_is_msi_dev #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ +#ifdef CONFIG_GENERIC_MSI_IRQ +int msi_device_domain_alloc_wired(struct irq_domain *domain, unsigned int hwirq, + unsigned int type); +void msi_device_domain_free_wired(struct irq_domain *domain, unsigned int virq); +#else +static inline int msi_device_domain_alloc_wired(struct irq_domain *domain, unsigned int hwirq, + unsigned int type) +{ + WARN_ON_ONCE(1); + return -EINVAL; +} +static inline void msi_device_domain_free_wired(struct irq_domain *domain, unsigned int virq) +{ + WARN_ON_ONCE(1); +} +#endif + #else /* CONFIG_IRQ_DOMAIN */ static inline void irq_dispose_mapping(unsigned int virq) { } static inline struct irq_domain *irq_find_matching_fwnode( --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1561,6 +1561,50 @@ struct msi_map msi_domain_alloc_irq_at(s return map; } +/** + * msi_device_domain_alloc_wired - Allocate a "wired" interrupt on @domain + * @domain: The domain to allocate on + * @hwirq: The hardware interrupt number to allocate for + * @type: The interrupt type + * + * This weirdness supports wire to MSI controllers like MBIGEN. + * + * @hwirq is the hardware interrupt number which is handed in from + * irq_create_fwspec_mapping(). As the wire to MSI domain is sparse, but + * sized in firmware, the hardware interrupt number cannot be used as MSI + * index. For the underlying irq chip the MSI index is irrelevant and + * all it needs is the hardware interrupt number. + * + * To handle this the MSI index is allocated with MSI_ANY_INDEX and the + * hardware interrupt number is stored along with the type information in + * msi_desc::cookie so the underlying interrupt chip and domain code can + * retrieve it. + * + * Return: The Linux interrupt number (> 0) or an error code + */ +int msi_device_domain_alloc_wired(struct irq_domain *domain, unsigned int hwirq, + unsigned int type) +{ + unsigned int domid = MSI_DEFAULT_DOMAIN; + union msi_instance_cookie icookie = { }; + struct device *dev = domain->dev; + struct msi_map map = { }; + + if (WARN_ON_ONCE(!dev || domain->bus_token != DOMAIN_BUS_WIRED_TO_MSI)) + return -EINVAL; + + icookie.value = ((u64)type << 32) | hwirq; + + msi_lock_descs(dev); + if (WARN_ON_ONCE(msi_get_device_domain(dev, domid) != domain)) + map.index = -EINVAL; + else + map = __msi_domain_alloc_irq_at(dev, domid, MSI_ANY_INDEX, NULL, &icookie); + msi_unlock_descs(dev); + + return map.index >= 0 ? map.virq : map.index; +} + static void __msi_domain_free_irqs(struct device *dev, struct irq_domain *domain, struct msi_ctrl *ctrl) { @@ -1688,6 +1732,30 @@ void msi_domain_free_irqs_all(struct dev msi_unlock_descs(dev); } +/** + * msi_device_domain_free_wired - Free a wired interrupt in @domain + * @domain: The domain to free the interrupt on + * @virq: The Linux interrupt number to free + * + * This is the counterpart of msi_device_domain_alloc_wired() for the + * weird wired to MSI converting domains. + */ +void msi_device_domain_free_wired(struct irq_domain *domain, unsigned int virq) +{ + struct msi_desc *desc = irq_get_msi_desc(virq); + struct device *dev = domain->dev; + + if (WARN_ON_ONCE(!dev || !desc || domain->bus_token != DOMAIN_BUS_WIRED_TO_MSI)) + return; + + msi_lock_descs(dev); + if (!WARN_ON_ONCE(msi_get_device_domain(dev, MSI_DEFAULT_DOMAIN) != domain)) { + msi_domain_free_irqs_range_locked(dev, MSI_DEFAULT_DOMAIN, desc->msi_index, + desc->msi_index); + } + msi_unlock_descs(dev); +} + /** * msi_get_domain_info - Get the MSI interrupt domain info for @domain * @domain: The interrupt domain to retrieve data from From patchwork Mon Nov 21 14:39:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23863 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1644523wrr; Mon, 21 Nov 2022 07:09:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf465qnak3/t4UenSLkXQWKl+/c7QG6pxCk9wxlGUD0pVKjmUDOst5PdoG2FGxDCfTSHAcmA X-Received: by 2002:a17:907:c70a:b0:7ad:d6c6:eb7c with SMTP id ty10-20020a170907c70a00b007add6c6eb7cmr8582577ejc.249.1669043347341; Mon, 21 Nov 2022 07:09:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043347; cv=none; d=google.com; s=arc-20160816; b=VtFrpS1VKgf7MJygOTCHoM1InXLhkEctk2Ahp6YoOloZ9gi84QgDp6nn0+LYivytRW ftKWlxcZKytVNSXGd3OnCYWX3D3lBWJYrjEv8XftMkPH8etK1tiJG24cP6HZzgiYTRIb GAbJpZbSZKzx6ksK2Qw4GaReJHI6+aTMNl8+NmMAhML/roPeUTorsvAzem9jJEVJ6xXm g2sWCBuh77jUqjmj2alBO8lSUpMwZc0AxAiFCJQdfe9ItzhtZGBn5m79KqiolSRO8gFA tRZmNUuBz3snSAbtLQjGZL6Z9ZhAh/Y1X0pCjI8mrkg7+lctnUyxgzGs8A7D4t+IBElp KUeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=npOaMCiYsoks0F7mHssoAU+zRn6o9Ysh3VW0SdHACSU=; b=JG0vxkcS9iadYuJTTW8HGGSy2/cQaew/Aw2UnzJw/18TbH2rzNOAmRfVqDUKAKZjDg sRZs1uwA9LIavJ2zFnV1O/gAvrCG84LL29mP8Q7ahlCrwDwbKrs1qL7zy9Ar+2i0bpHi sYokIz+V0gohCYaocgp5EStlXJjdzjBpRm9J710h95B20APW2N1rKwgT8O3pWUCFVSlU 70uW9F4zOOjjZFKqjaWlCcKcugvJoCjnZmgkHXY1Sp8h5emDSb2bguojEioJBfWuu5E7 Yi9h4PZuiBbhc5SNnJnuCO13rr6asLPALgYop9wxAYyqOoNvgb9aS+x8eX0vy69TWP6k /cKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3TXaiHo6; dkim=neutral (no key) header.i=@linutronix.de header.b=AwJHQdeq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hb11-20020a170907160b00b007ae6fe0f286si10226897ejc.12.2022.11.21.07.08.07; Mon, 21 Nov 2022 07:09:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=3TXaiHo6; dkim=neutral (no key) header.i=@linutronix.de header.b=AwJHQdeq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229865AbiKUOug (ORCPT + 99 others); Mon, 21 Nov 2022 09:50:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231903AbiKUOtr (ORCPT ); Mon, 21 Nov 2022 09:49:47 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B13A0C847F; Mon, 21 Nov 2022 06:42:24 -0800 (PST) Message-ID: <20221121140049.743020502@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041597; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=npOaMCiYsoks0F7mHssoAU+zRn6o9Ysh3VW0SdHACSU=; b=3TXaiHo6uW/aaxhnn2KG2Uzs838Y0pUbjSbvGJnh1pBFM2qh0vmz1R1CYFhvBn/V+bBa+P qwqWNnGpZd1K7XNyAJNSF/r8d0eQhQKK2KrWIQcgxFdQV3gJ4j9EGNka2wfvb9+pEC2NWE pUT3CD6XMUO23n406SnSgCqYEEaLypzPm/EI8vzvarXHuJQSZM8qfFKN71TRhILFXcokWs 3m8TcmB+bIaUxk5/fU1lmgPgs9UYAq/aWa4Lrvw7upCGZKXiC6pcPn/vWdkMw+oPDE0qK3 mBY52Bdx0MYXhRgDTIQp8Pi2+l3VhW1IlOhtunxsXWhyA/QRkaBNRVESDO0VkQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041597; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=npOaMCiYsoks0F7mHssoAU+zRn6o9Ysh3VW0SdHACSU=; b=AwJHQdeqKACcGONTrz7Gd3yQY8ESpH15ZOH7wfsX2lcP4RybVMRkXhywwStrFS9S/RZXKw 5KwEx0d+A7/tCxDg== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 23/40] genirq/irqdomain: Reroute device MSI create_mapping References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:57 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118796717848788?= X-GMAIL-MSGID: =?utf-8?q?1750118796717848788?= Reroute interrupt allocation in irq_create_fwspec_mapping() if the domain is a MSI device domain. This is required to convert the support for wire to MSI bridges to per device MSI domains. Signed-off-by: Thomas Gleixner --- kernel/irq/irqdomain.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -26,6 +26,7 @@ static DEFINE_MUTEX(irq_domain_mutex); static struct irq_domain *irq_default_domain; static void irq_domain_check_hierarchy(struct irq_domain *domain); +static void irq_domain_free_one_irq(struct irq_domain *domain, unsigned int virq); struct irqchip_fwid { struct fwnode_handle fwnode; @@ -822,7 +823,10 @@ unsigned int irq_create_fwspec_mapping(s } if (irq_domain_is_hierarchy(domain)) { - virq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, fwspec); + if (irq_domain_is_msi_device(domain)) + virq = msi_device_domain_alloc_wired(domain, hwirq, type); + else + virq = irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, fwspec); if (virq <= 0) return 0; } else { @@ -835,7 +839,7 @@ unsigned int irq_create_fwspec_mapping(s irq_data = irq_get_irq_data(virq); if (!irq_data) { if (irq_domain_is_hierarchy(domain)) - irq_domain_free_irqs(virq, 1); + irq_domain_free_one_irq(domain, virq); else irq_dispose_mapping(virq); return 0; @@ -876,7 +880,7 @@ void irq_dispose_mapping(unsigned int vi return; if (irq_domain_is_hierarchy(domain)) { - irq_domain_free_irqs(virq, 1); + irq_domain_free_one_irq(domain, virq); } else { irq_domain_disassociate(domain, virq); irq_free_desc(virq); @@ -1706,6 +1710,14 @@ void irq_domain_free_irqs(unsigned int v irq_free_descs(virq, nr_irqs); } +static void irq_domain_free_one_irq(struct irq_domain *domain, unsigned int virq) +{ + if (irq_domain_is_msi_device(domain)) + msi_device_domain_free_wired(domain, virq); + else + irq_domain_free_irqs(virq, 1); +} + /** * irq_domain_alloc_irqs_parent - Allocate interrupts from parent domain * @domain: Domain below which interrupts must be allocated @@ -1865,9 +1877,9 @@ void irq_domain_set_info(struct irq_doma irq_set_handler_data(virq, handler_data); } -static void irq_domain_check_hierarchy(struct irq_domain *domain) -{ -} +static void irq_domain_check_hierarchy(struct irq_domain *domain) { } +static void irq_domain_free_one_irq(struct irq_domain *domain, unsigned int virq) { } + #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ #ifdef CONFIG_GENERIC_IRQ_DEBUGFS From patchwork Mon Nov 21 14:39:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23862 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1644324wrr; Mon, 21 Nov 2022 07:08:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf6t6JCz+YSfQ2bBAT2oOMQHDAm8NSDvLE281p02CPsho2+y4wJqV8O7niBRuNlNUGUZ9nNT X-Received: by 2002:a17:906:2e83:b0:78d:b3f0:b5c0 with SMTP id o3-20020a1709062e8300b0078db3f0b5c0mr16331287eji.141.1669043331675; Mon, 21 Nov 2022 07:08:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043331; cv=none; d=google.com; s=arc-20160816; b=rJR07E85XOXJq1uvh9LkGRRK2BTM/YYhSGO/RQa/2BqYFOzegXAlTPCsZtaIs0KpUp foDG3Y1pE3DfoU+ZQ9Fxg4a4dc2YBsf5nYsocPj9r058iZjhn9laq3jhZLnZ8GJd6zIl lQtNA2uCS45AgCU1LkEpGS3X5T2lr1XLJ6KElDGMfOxP+NjoYd6F2BMo0PfhaK6vyCsl 1pU/X0ao35BUqP9aaXMnl8xVyn5tME/hKUobwXr5pgXp1XMAKfvno/4HWbBHSU6mTbuz RxpTyQUZpngsmMpaXE3dXn6hiwI94Vmq8Ch4Jp0+ggXX3QAVrGSI3Stw9vQdLXH60aZZ NlFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=FKeWOHgG+aHIXBCujh1JES3kINokE+MytWoAnu2BWBo=; b=Uq2hpdaxmiqHNqR6Q3U8YUUKneMcan1fiC7wJslHLOA2v6GkzkMNhKL01q84lOX4mN HwhBlLpWM5W5HE0sajVyxf6qH/XZrGRjar0fB5M3lQVToySOdDBcyDmTNKeu1ZmxZKHB OUtcnxLxjz+ycmI32hcY4bU3TIvfPxfYZmQGe8LXpJoNiVDn/5XBDmHNSGfgz1Sz8mwy 7T1cViAsy3XZCim5qvPPEvTr54GUOwoZA9DooxEk910VfHMYv3Wo/uCu4RJAtMObIqjX aluTr1kJqdJkmV4r+TWINLOKkigTHcCKeeYvfWdma7uLOxQd4qIdTq4s/grBkvc8D7k8 5c0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=qpTzA5pD; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k26-20020aa7d8da000000b00448b88378f8si8833055eds.359.2022.11.21.07.08.09; Mon, 21 Nov 2022 07:08:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=qpTzA5pD; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229832AbiKUOul (ORCPT + 99 others); Mon, 21 Nov 2022 09:50:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230238AbiKUOtr (ORCPT ); Mon, 21 Nov 2022 09:49:47 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15FF3D48D3; Mon, 21 Nov 2022 06:42:24 -0800 (PST) Message-ID: <20221121140049.807060253@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041598; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FKeWOHgG+aHIXBCujh1JES3kINokE+MytWoAnu2BWBo=; b=qpTzA5pDWuxLVdyFMtO6/TMmtYgjp6g69hOtYoU5lf+erQvfYb2MGr190Z27zK3RW7ocW6 VaiUWDem6lQexzCwcH0nZQzaxrMB3W0WTeo5CVcwGev8yl6E9L4y8l8QxvkTU2RAl+MQcI /E9LialgECosISytwvcLi+99PhZr5/b4PENSoY9XYxA1CZtW6nhDqnmzZ54bPyCBrS3rVG SvFp+vhAAzOOEhgbXz0j6fNrUQ4RgyFP8nYV3x0J5iYJ6ZVVSUbNJHqG3n6DR/cjmWoqaV 8BgURHFsQK0AZ3LI1zc+zvndbm5pDyhedPBdonpY7Dlyigc9yWnloDwfI2zzVA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041598; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FKeWOHgG+aHIXBCujh1JES3kINokE+MytWoAnu2BWBo=; b=KHn7pDOVwpDBH1OyyefDBTTQc9TR/pjDnWNMzDLDTvr0sx9OEct6SJme9etfQBYaTQMhAo YhOnzZXa6BV/zFBg== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 24/40] irqchip/mbigen: Prepare for real per device MSI References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:39:58 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118780817447220?= X-GMAIL-MSGID: =?utf-8?q?1750118780817447220?= The core infrastructure has everything in place to switch MBIGEN to per device MSI domains and avoid the convoluted construct of the existing platform-MSI layering violation. The new infrastructure provides a wired interrupt specific interface in the MSI core which converts the 'hardware interrupt number + trigger type' allocation which is required for wired interrupts in the regular irqdomain code to a normal MSI allocation. The hardware interrupt number and the trigger type are stored in the MSI descriptor device cookie by the core code so the MBIGEN specific code can retrieve them. The new per device domain is only instantiated when the irqdomain which is associated to the MBIGEN device provides MSI parent functionality. Up to that point it invokes the existing code. Once the parent is converted the code for the current platform-MSI mechanism is removed. The new domain shares the interrupt chip callbacks and the translation function. The only new functionality aside of filling out the msi_domain_template is a domain specific set_desc() callback, which will go away once all platform-MSI code has been converted. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier Cc: Shameerali Kolothum Thodi Cc: Zenghui Yu --- drivers/irqchip/irq-mbigen.c | 100 ++++++++++++++++++++++++++++++------------- 1 file changed, 71 insertions(+), 29 deletions(-) --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -135,24 +135,14 @@ static int mbigen_set_type(struct irq_da return 0; } -static struct irq_chip mbigen_irq_chip = { - .name = "mbigen-v2", - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, - .irq_eoi = mbigen_eoi_irq, - .irq_set_type = mbigen_set_type, - .irq_set_affinity = irq_chip_set_affinity_parent, -}; - -static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) +static void mbigen_write_msi_msg(struct irq_data *d, struct msi_msg *msg) { - struct irq_data *d = irq_get_irq_data(desc->irq); void __iomem *base = d->chip_data; u32 val; if (!msg->address_lo && !msg->address_hi) return; - + base += get_mbigen_vec_reg(d->hwirq); val = readl_relaxed(base); @@ -165,10 +155,8 @@ static void mbigen_write_msg(struct msi_ writel_relaxed(val, base); } -static int mbigen_domain_translate(struct irq_domain *d, - struct irq_fwspec *fwspec, - unsigned long *hwirq, - unsigned int *type) +static int mbigen_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, + unsigned long *hwirq, unsigned int *type) { if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) { if (fwspec->param_count != 2) @@ -192,6 +180,17 @@ static int mbigen_domain_translate(struc return -EINVAL; } +/* The following section will go away once ITS provides a MSI parent */ + +static struct irq_chip mbigen_irq_chip = { + .name = "mbigen-v2", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = mbigen_eoi_irq, + .irq_set_type = mbigen_set_type, + .irq_set_affinity = irq_chip_set_affinity_parent, +}; + static int mbigen_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, @@ -232,13 +231,65 @@ static const struct irq_domain_ops mbige .free = mbigen_irq_domain_free, }; +static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + mbigen_write_msi_msg(irq_get_irq_data(desc->irq), msg); +} + +/* End of to be removed section */ + +static void mbigen_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) +{ + arg->desc = desc; + arg->hwirq = (u32)desc->data.icookie.value; +} + +static const struct msi_domain_template mbigen_msi_template = { + .chip = { + .name = "mbigen-v2", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = mbigen_eoi_irq, + .irq_set_type = mbigen_set_type, + .irq_write_msi_msg = mbigen_write_msi_msg, + }, + + .ops = { + .set_desc = mbigen_domain_set_desc, + .msi_translate = mbigen_domain_translate, + }, + + .info = { + .bus_token = DOMAIN_BUS_WIRED_TO_MSI, + .flags = MSI_FLAG_USE_DEV_FWNODE, + }, +}; + +static bool mbigen_create_device_domain(struct device *dev, unsigned int size, + struct mbigen_device *mgn_chip) +{ + struct irq_domain *domain = dev->msi.domain; + + if (WARN_ON_ONCE(!domain)) + return false; + + if (irq_domain_is_msi_parent(domain)) { + return msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, + &mbigen_msi_template, size, + NULL, mgn_chip->base); + } + + /* Remove once ITS provides MSI parent */ + return !!platform_msi_create_device_domain(dev, size, mbigen_write_msg, + &mbigen_domain_ops, mgn_chip); +} + static int mbigen_of_create_domain(struct platform_device *pdev, struct mbigen_device *mgn_chip) { - struct device *parent; struct platform_device *child; - struct irq_domain *domain; struct device_node *np; + struct device *parent; u32 num_pins; for_each_child_of_node(pdev->dev.of_node, np) { @@ -259,11 +310,7 @@ static int mbigen_of_create_domain(struc return -EINVAL; } - domain = platform_msi_create_device_domain(&child->dev, num_pins, - mbigen_write_msg, - &mbigen_domain_ops, - mgn_chip); - if (!domain) { + if (!mbigen_create_device_domain(&child->dev, num_pins, mgn_chip)) { of_node_put(np); return -ENOMEM; } @@ -282,7 +329,6 @@ MODULE_DEVICE_TABLE(acpi, mbigen_acpi_ma static int mbigen_acpi_create_domain(struct platform_device *pdev, struct mbigen_device *mgn_chip) { - struct irq_domain *domain; u32 num_pins = 0; int ret; @@ -313,11 +359,7 @@ static int mbigen_acpi_create_domain(str if (ret || num_pins == 0) return -EINVAL; - domain = platform_msi_create_device_domain(&pdev->dev, num_pins, - mbigen_write_msg, - &mbigen_domain_ops, - mgn_chip); - if (!domain) + if (!mbigen_create_device_domain(&pdev->dev, num_pins, mgn_chip)) return -ENOMEM; return 0; From patchwork Mon Nov 21 14:39:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23872 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646188wrr; Mon, 21 Nov 2022 07:11:37 -0800 (PST) X-Google-Smtp-Source: AA0mqf6z+jwiHT3DJZrhlMOOq5/hyLeYP4zbivk43XWMXfBARD3bqDEG/AEFeCQG25FPjTT1mIjY X-Received: by 2002:a17:902:868b:b0:186:8c19:d472 with SMTP id g11-20020a170902868b00b001868c19d472mr1065plo.12.1669043496651; Mon, 21 Nov 2022 07:11:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-gic-msi-lib.c | 2 ++ 1 file changed, 2 insertions(+) --- a/drivers/irqchip/irq-gic-msi-lib.c +++ b/drivers/irqchip/irq-gic-msi-lib.c @@ -68,6 +68,8 @@ bool gic_msi_lib_init_dev_msi_info(struc /* Core managed MSI descriptors */ info->flags = MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | MSI_FLAG_FREE_MSI_DESCS; break; + case DOMAIN_BUS_WIRED_TO_MSI: + break; default: /* * This should never be reached. See From patchwork Mon Nov 21 14:40:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23864 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1644714wrr; Mon, 21 Nov 2022 07:09:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf63B01OzRvCA9vX40hyw6K7GVkeq57lCNlhXA/IoBTgFW15lyMBeP5tRcIGqdiVsEPQmoTa X-Received: by 2002:a17:906:7b93:b0:7ae:c9ae:938d with SMTP id s19-20020a1709067b9300b007aec9ae938dmr7421973ejo.313.1669043362959; Mon, 21 Nov 2022 07:09:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043362; cv=none; d=google.com; s=arc-20160816; b=SRvEMC8iDlN4LK/Gq2avmpoel7dAoZg9QHD3NLc1jCTpCdloTJUvjxQZfL+Vfj5t8u B/7pbhxOAUUVGzZSatLShHnXFiw6BWU8gdhx3spRUOY1vNf3hHBfJEvR7BH4OJQMz2J0 kwlRw0cAzFxJ2NaQQ0xfqqcokCMgH2KgCCQXQiLmkwcSWdsTisFji+gXN9bXWj0ownQk 7QN/675oq7XtelVCfHLLTTTDh4sMlvLsSjUVv2vITtibDXg6gd83X45xq2j/WxwX41CC GVuSLiMkisGEEpUIfRbPpTYbvcU9KipfcJs/v1KS/jR0qRXAMSif3iZNfg0tnIkBM5XF uxzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=nbwC+lgSL6ozvNItgfyZXaBzbrAk8SyOeMtfmXA2KHc=; b=dkHuiv6Eo6R+HyeLliyJrbnBpC3DibrFa95TNjb6JUQid6EXeUotxCC8eL4NvfKQYN Y96xxa+p84yZ+JQDXWHGbdeRz2mSGpm7h1lFKbV39TeAYu91RFFnSzK5AeGcWxNT4wAN FDmNL7ygcYANHoZBjkQ2z7TR00+weY+8UzhEIMrsHQe3I3KQf3Kd+cjk3p/26GoPtEOX rqFjcZIiw4ufhj6g+ffad2WVM8GOIb9SV3B7h57IyHIKY0S6b+iE8i1BLt73KK1FDmFX 90gNNSXehanCyRENFLPe1V6oCpoh+XXjyEdY/CRtb/WEtqrf1ZpJfDBdBUXSn5Najsup 1p+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=aEgfAOyK; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Kk+3p8BY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e20-20020a1709067e1400b007269ef1872esi7656068ejr.897.2022.11.21.07.08.53; Mon, 21 Nov 2022 07:09:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=aEgfAOyK; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Kk+3p8BY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230114AbiKUOux (ORCPT + 99 others); Mon, 21 Nov 2022 09:50:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231345AbiKUOuZ (ORCPT ); Mon, 21 Nov 2022 09:50:25 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B74FE2DC5; Mon, 21 Nov 2022 06:42:32 -0800 (PST) Message-ID: <20221121140049.941784867@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041601; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nbwC+lgSL6ozvNItgfyZXaBzbrAk8SyOeMtfmXA2KHc=; b=aEgfAOyK0g42Cs3T2dxIWhy//sAG4P5ZapNnQgaQh9DuK8zQMyeI5zLD7Y7BfBMisRqTx0 0zl/4156RrkOu78eKsoGlTmCXTpSRdPA3tafW1ywAPTtarU3O/xrHNqUEEcSNxBYqtS3a6 aKI2sC/BTWzBjaTM7W7/q5NOm+ygGYVdLbqe2HgTTpj80rpk2En4wkxI1+qYoGtVwl8hVG z6qcNymeKvL2zxjXLOX/d4Jb4gUmdYf7D+3vaM9kAYbq1yKAPR/WqPet1dlACjXVMr11BR 9RWcap4yPMkAkpFtgHQ71WevieedMIdVyuvr61FvWKn4zv1rFDlxlRI2TdG7cg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041601; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nbwC+lgSL6ozvNItgfyZXaBzbrAk8SyOeMtfmXA2KHc=; b=Kk+3p8BYmhT8c6maSO8QdSKAeHmnWeAxMJKZR+aGs12evof84V8083yd4eHATRf8ebrrgy VaRf97lPkmQ3V7AQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 26/40] irqchip/gic-v3-its: Switch platform MSI to MSI parent References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:01 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118813290129211?= X-GMAIL-MSGID: =?utf-8?q?1750118813290129211?= Similar to the previous conversion of the PCI/MSI support lift the prepare() callback from the existing platform MSI code and enable platform MSI and the related device domain bus tokens in select and the child domain initialization code. All platform MSI users are automatically using the new per device MSI model now. Signed-off-by: Thomas Gleixner --- drivers/irqchip/Makefile | 2 drivers/irqchip/irq-gic-v3-its-msi-parent.c | 73 +++++++++++ drivers/irqchip/irq-gic-v3-its-platform-msi.c | 163 -------------------------- 3 files changed, 73 insertions(+), 165 deletions(-) --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -33,7 +33,7 @@ obj-$(CONFIG_ARCH_REALVIEW) += irq-gic- obj-$(CONFIG_ARM_GIC_MSI_LIB) += irq-gic-msi-lib.o obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o -obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o irq-gic-v3-its-msi-parent.o +obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v4.o irq-gic-v3-its-msi-parent.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o --- a/drivers/irqchip/irq-gic-v3-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-v3-its-msi-parent.c @@ -4,6 +4,7 @@ // Copyright (C) 2022 Linutronix GmbH // Copyright (C) 2022 Intel +#include #include #include "irq-gic-common.h" @@ -93,6 +94,68 @@ static int its_pci_msi_prepare(struct ir #define its_pci_msi_prepare NULL #endif /* !CONFIG_PCI_MSI */ +static int of_pmsi_get_dev_id(struct irq_domain *domain, struct device *dev, + u32 *dev_id) +{ + int ret, index = 0; + + /* Suck the DeviceID out of the msi-parent property */ + do { + struct of_phandle_args args; + + ret = of_parse_phandle_with_args(dev->of_node, + "msi-parent", "#msi-cells", + index, &args); + if (args.np == irq_domain_get_of_node(domain)) { + if (WARN_ON(args.args_count != 1)) + return -EINVAL; + *dev_id = args.args[0]; + break; + } + index++; + } while (!ret); + + return ret; +} + +int __weak iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) +{ + return -1; +} + +static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, + int nvec, msi_alloc_info_t *info) +{ + struct msi_domain_info *msi_info; + u32 dev_id; + int ret; + + if (dev->of_node) + ret = of_pmsi_get_dev_id(domain, dev, &dev_id); + else + ret = iort_pmsi_get_dev_id(dev, &dev_id); + if (ret) + return ret; + + /* ITS specific DeviceID, as the core ITS ignores dev. */ + info->scratchpad[0].ul = dev_id; + + /* + * @domain->msi_domain_info->hwsize contains the size of the device + * domain, but vector allocation happens one by one. + */ + msi_info = msi_get_domain_info(domain); + if (msi_info->hwsize > nvec) + nvec = msi_info->hwsize; + + /* Allocate at least 32 MSIs, and always as a power of 2 */ + nvec = max_t(int, 32, roundup_pow_of_two(nvec)); + + msi_info = msi_get_domain_info(domain->parent); + return msi_info->ops->msi_prepare(domain->parent, + dev, nvec, info); +} + static bool its_init_dev_msi_info(struct device *dev, struct irq_domain *domain, struct irq_domain *real_parent, struct msi_domain_info *info) { @@ -117,6 +180,14 @@ static bool its_init_dev_msi_info(struct */ info->ops->msi_prepare = its_pci_msi_prepare; break; + case DOMAIN_BUS_DEVICE_IMS: + case DOMAIN_BUS_WIRED_TO_MSI: + /* + * FIXME: See the above PCI prepare comment. The domain + * size is also known at domain creation time. + */ + info->ops->msi_prepare = its_pmsi_prepare; + break; default: /* Confused. How did the lib return true? */ WARN_ON_ONCE(1); @@ -130,7 +201,7 @@ const struct msi_parent_ops gic_v3_its_m .supported_flags = ITS_MSI_FLAGS_SUPPORTED, .required_flags = ITS_MSI_FLAGS_REQUIRED, .bus_select_token = DOMAIN_BUS_NEXUS, - .bus_select_mask = MATCH_PCI_MSI, + .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, .prefix = "ITS-", .init_dev_msi_info = its_init_dev_msi_info, }; --- a/drivers/irqchip/irq-gic-v3-its-platform-msi.c +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved. - * Author: Marc Zyngier - */ - -#include -#include -#include -#include -#include - -static struct irq_chip its_pmsi_irq_chip = { - .name = "ITS-pMSI", -}; - -static int of_pmsi_get_dev_id(struct irq_domain *domain, struct device *dev, - u32 *dev_id) -{ - int ret, index = 0; - - /* Suck the DeviceID out of the msi-parent property */ - do { - struct of_phandle_args args; - - ret = of_parse_phandle_with_args(dev->of_node, - "msi-parent", "#msi-cells", - index, &args); - if (args.np == irq_domain_get_of_node(domain)) { - if (WARN_ON(args.args_count != 1)) - return -EINVAL; - *dev_id = args.args[0]; - break; - } - index++; - } while (!ret); - - return ret; -} - -int __weak iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id) -{ - return -1; -} - -static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev, - int nvec, msi_alloc_info_t *info) -{ - struct msi_domain_info *msi_info; - u32 dev_id; - int ret; - - msi_info = msi_get_domain_info(domain->parent); - - if (dev->of_node) - ret = of_pmsi_get_dev_id(domain, dev, &dev_id); - else - ret = iort_pmsi_get_dev_id(dev, &dev_id); - if (ret) - return ret; - - /* ITS specific DeviceID, as the core ITS ignores dev. */ - info->scratchpad[0].ul = dev_id; - - /* Allocate at least 32 MSIs, and always as a power of 2 */ - nvec = max_t(int, 32, roundup_pow_of_two(nvec)); - return msi_info->ops->msi_prepare(domain->parent, - dev, nvec, info); -} - -static struct msi_domain_ops its_pmsi_ops = { - .msi_prepare = its_pmsi_prepare, -}; - -static struct msi_domain_info its_pmsi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), - .ops = &its_pmsi_ops, - .chip = &its_pmsi_irq_chip, -}; - -static const struct of_device_id its_device_id[] = { - { .compatible = "arm,gic-v3-its", }, - {}, -}; - -static int __init its_pmsi_init_one(struct fwnode_handle *fwnode, - const char *name) -{ - struct irq_domain *parent; - - parent = irq_find_matching_fwnode(fwnode, DOMAIN_BUS_NEXUS); - if (!parent || !msi_get_domain_info(parent)) { - pr_err("%s: unable to locate ITS domain\n", name); - return -ENXIO; - } - - if (!platform_msi_create_irq_domain(fwnode, &its_pmsi_domain_info, - parent)) { - pr_err("%s: unable to create platform domain\n", name); - return -ENXIO; - } - - pr_info("Platform MSI: %s domain created\n", name); - return 0; -} - -#ifdef CONFIG_ACPI -static int __init -its_pmsi_parse_madt(union acpi_subtable_headers *header, - const unsigned long end) -{ - struct acpi_madt_generic_translator *its_entry; - struct fwnode_handle *domain_handle; - const char *node_name; - int err = -ENXIO; - - its_entry = (struct acpi_madt_generic_translator *)header; - node_name = kasprintf(GFP_KERNEL, "ITS@0x%lx", - (long)its_entry->base_address); - domain_handle = iort_find_domain_token(its_entry->translation_id); - if (!domain_handle) { - pr_err("%s: Unable to locate ITS domain handle\n", node_name); - goto out; - } - - err = its_pmsi_init_one(domain_handle, node_name); - -out: - kfree(node_name); - return err; -} - -static void __init its_pmsi_acpi_init(void) -{ - acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR, - its_pmsi_parse_madt, 0); -} -#else -static inline void its_pmsi_acpi_init(void) { } -#endif - -static void __init its_pmsi_of_init(void) -{ - struct device_node *np; - - for (np = of_find_matching_node(NULL, its_device_id); np; - np = of_find_matching_node(np, its_device_id)) { - if (!of_device_is_available(np)) - continue; - if (!of_property_read_bool(np, "msi-controller")) - continue; - - its_pmsi_init_one(of_node_to_fwnode(np), np->full_name); - } -} - -static int __init its_pmsi_init(void) -{ - its_pmsi_of_init(); - its_pmsi_acpi_init(); - return 0; -} -early_initcall(its_pmsi_init); From patchwork Mon Nov 21 14:40:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23869 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1645556wrr; Mon, 21 Nov 2022 07:10:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf5TTOeZ9EQSaZB6Y+RRzTemj/lRobo5p689+XLgvWZusb2AFdercnWTWEvCvrd7RGUbBGyW X-Received: by 2002:a17:906:ce35:b0:7ae:215:2dd5 with SMTP id sd21-20020a170906ce3500b007ae02152dd5mr148510ejb.208.1669043438283; Mon, 21 Nov 2022 07:10:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043438; cv=none; d=google.com; s=arc-20160816; b=SWreOyV73RA5JAlUkL1CBkmyGSQPe3MRRlejv0PrXWOuSFVjFGU79nmdXgVtpRyhmj p99Y3JarbijG8ufKpnwlDvCit/V8hEvA26Xh4wIzPBN5qDkqDvAQz9t0EejIgzJCmcKM emXKTHW3vG4RhYMXRh/gaIFTPR1sO9ywnHvMEIkrpdmr8ln19GEw4nuVewvVc6yoPwbq 8+3T8nuUR0QCMYn/Z4OBSFwKhL1aNKtuCD6+ZjJIyRZ72clsy9xMBNu3MMiIzycfWAtN 1WF+tQut/XmzyO6XlTAtUWc4d7RrvW07xiCVtjBI1x9o9sFWiTe3vo6Wm8sxJgZKgInx G7tg== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u2-20020a50eac2000000b00463d1e2639fsi6990912edp.363.2022.11.21.07.10.07; Mon, 21 Nov 2022 07:10:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=H2+nRsG8; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4fQWxlxT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230438AbiKUOvP (ORCPT + 99 others); Mon, 21 Nov 2022 09:51:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231881AbiKUOud (ORCPT ); Mon, 21 Nov 2022 09:50:33 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF6A49E963; Mon, 21 Nov 2022 06:42:43 -0800 (PST) Message-ID: <20221121140050.005249847@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041602; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1qf1CpiGQuxTaBaQJziws0lBHcg/Bs5K2Mj5ASL27jM=; b=H2+nRsG8r586jKjGAlvKt02BDjMI4po3O2a4W8Od2X4bXuZeT3lW2rJMe4phHNkAI99TLm Ka0mmJns6BM2nQzY4k/oZdqezW6fbHT07Gq9Yqosps2wnx6f/GsDWIFRfzXQ+EVzGwH2XC 3ZiuYMZfQcPU0gzvHqnVKJELBhO4Dos+B3LYDCQCnJXhJmVCGeLeFogvREJUykOt7BzENw IeJCETfKmzXN+TiU/ptwiBFZCbBacy0bubqfW9Lt7AafjiqqA+HN8F8s7bUtHJM7u5NZlK QJ4G8NZkIT0HnjXlu39mW1YzF3KNzBzWd5nqR5xM+p4rnSYxyPLZGlYVq6Ex/Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041602; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1qf1CpiGQuxTaBaQJziws0lBHcg/Bs5K2Mj5ASL27jM=; b=4fQWxlxTHf6bVWds80rgtZQcBfZVZmudrfS4kGvp2hUUm7KhRFgD5PA2u0Cj9RqTYoasWR TpHZF16CQUFoO8Ag== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 27/40] irqchip/mbigen: Remove platform_msi_create_device_domain() fallback References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:02 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118892498159235?= X-GMAIL-MSGID: =?utf-8?q?1750118892498159235?= Now that ITS provides the MSI parent domain, remove the unused fallback code. Signed-off-by: Thomas Gleixner --- drivers/irqchip/irq-mbigen.c | 74 ++----------------------------------------- 1 file changed, 4 insertions(+), 70 deletions(-) --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -180,64 +180,6 @@ static int mbigen_domain_translate(struc return -EINVAL; } -/* The following section will go away once ITS provides a MSI parent */ - -static struct irq_chip mbigen_irq_chip = { - .name = "mbigen-v2", - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, - .irq_eoi = mbigen_eoi_irq, - .irq_set_type = mbigen_set_type, - .irq_set_affinity = irq_chip_set_affinity_parent, -}; - -static int mbigen_irq_domain_alloc(struct irq_domain *domain, - unsigned int virq, - unsigned int nr_irqs, - void *args) -{ - struct irq_fwspec *fwspec = args; - irq_hw_number_t hwirq; - unsigned int type; - struct mbigen_device *mgn_chip; - int i, err; - - err = mbigen_domain_translate(domain, fwspec, &hwirq, &type); - if (err) - return err; - - err = platform_msi_device_domain_alloc(domain, virq, nr_irqs); - if (err) - return err; - - mgn_chip = platform_msi_get_host_data(domain); - - for (i = 0; i < nr_irqs; i++) - irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, - &mbigen_irq_chip, mgn_chip->base); - - return 0; -} - -static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) -{ - platform_msi_device_domain_free(domain, virq, nr_irqs); -} - -static const struct irq_domain_ops mbigen_domain_ops = { - .translate = mbigen_domain_translate, - .alloc = mbigen_irq_domain_alloc, - .free = mbigen_irq_domain_free, -}; - -static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) -{ - mbigen_write_msi_msg(irq_get_irq_data(desc->irq), msg); -} - -/* End of to be removed section */ - static void mbigen_domain_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) { arg->desc = desc; @@ -268,20 +210,12 @@ static const struct msi_domain_template static bool mbigen_create_device_domain(struct device *dev, unsigned int size, struct mbigen_device *mgn_chip) { - struct irq_domain *domain = dev->msi.domain; - - if (WARN_ON_ONCE(!domain)) + if (WARN_ON_ONCE(!dev->msi.domain)) return false; - if (irq_domain_is_msi_parent(domain)) { - return msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, - &mbigen_msi_template, size, - NULL, mgn_chip->base); - } - - /* Remove once ITS provides MSI parent */ - return !!platform_msi_create_device_domain(dev, size, mbigen_write_msg, - &mbigen_domain_ops, mgn_chip); + return msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, + &mbigen_msi_template, size, + NULL, mgn_chip->base); } static int mbigen_of_create_domain(struct platform_device *pdev, From patchwork Mon Nov 21 14:40:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23867 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1645407wrr; Mon, 21 Nov 2022 07:10:24 -0800 (PST) X-Google-Smtp-Source: AA0mqf525BbUo0NPYh3MKZwT5zTupXVuikoMOthyJiDY7vec/f4yWO5/kzsh6AGEa6Kl6iSoI85g X-Received: by 2002:aa7:d156:0:b0:468:51b0:295 with SMTP id r22-20020aa7d156000000b0046851b00295mr16908203edo.319.1669043424410; Mon, 21 Nov 2022 07:10:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043424; cv=none; d=google.com; s=arc-20160816; b=lZuUKDR88fb7brlIHvhj4b/7zSu/WlmxkOnuDZUoFcQkIg/4gnqk+BkO/I9ipSh0ug /jovioKMGsa9tqZkSwec72aB5stewTJKESOFnE2l1E3Tl7hsxJ1hHSZiMtc6GmH/jIeS F1u8w09rdq32CXUglFtQ8UK+i15xYjDRJ3YxJ3gAAuYtSX8XzKdh0Nlx6knDMbFZ4xi/ jSyE0Z7tN+iAKItMVC2Dsx6kPH18jeoOtgWeaNYQoOtue5WQZxy/PbDNRxbpv1bn+YDH MxYVtPp/hEA3sWgUAlHqpOD7bInjMEN2W18byD+1wX3o71aX61nSJBm8oT5hQXesDX3X ND0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=rOGH2uTdH3rpdejv2KcowoAdUUfZ4dmd83F9d2EYah8=; b=FOa5S/wLMXV6TcF6Al1EWZ/S2CUlj+Uybsg5yA41t5zTAMRwkz5U2/OVvRjoIqSnjS Wha81eWT2DpUwelv0qGdZuR2tpFQl/5FhZdTuXpeX3OZhzZc/+0v91qk8UAzudyf0mwV 4V2ugEOHDF96BtbjVqqtmnDznNWgMZiE7TxXXpob6OWylRrt/5/T1smnM/ruNZ+O0B+s bpz3EKFNsBVuabyWsCDW5FGRwY8mcxVuzjhF2bfHh3pS8GnRGZCiFq26lgwT+odZ6L7l +lg85MtvXsZcq7UnKf+dCG/ewwbt/tM5tGfIpJRNTbi/bmrWPUXAE92rz4ex8so7KuPI x/Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=kp4D3GKb; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="e/+tc2Ub"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 2 -- 1 file changed, 2 deletions(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -646,8 +646,6 @@ struct irq_domain * const struct irq_domain_ops *ops, void *host_data); -#define platform_msi_create_device_domain(dev, nvec, write, ops, data) \ - __platform_msi_create_device_domain(dev, nvec, false, write, ops, data) #define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \ __platform_msi_create_device_domain(dev, nvec, true, write, ops, data) From patchwork Mon Nov 21 14:40:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23876 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646335wrr; Mon, 21 Nov 2022 07:11:50 -0800 (PST) X-Google-Smtp-Source: AA0mqf7Z8XGHJlulSxBW0lFa2IPGVy8r93CjiRW7pEynfDnp68OHuvgb3xrY5B1bc/yVtscGSIln X-Received: by 2002:a17:906:1412:b0:7a0:3313:a775 with SMTP id p18-20020a170906141200b007a03313a775mr5259302ejc.474.1669043510049; Mon, 21 Nov 2022 07:11:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043510; cv=none; d=google.com; s=arc-20160816; b=U0d+WrHIlyxpYM2kud1Re8VkcPMKx8VqDSUazeZrFDkjbShdj+a69VTpztkZueQuWQ HG6f8YPiNB1BO4A+hjFtanNP/cMRwk1FbWQdXsBYGSBD8fs4OzDTrhgteUGXPkmmymcW KdrZPRujxANnaoAQjQa/GnM8UyjEM8FDYZW/+N8nfuuDgAJy324p2CbA0dj4QML+b6H3 UvTQ+RgX7CQuKKZNf18YSueqQ4nsyAGiJdS1Io7kkwU9v692mJXOit/OVh7wB1EeverG 62y/xxNPUIA9kJW/cJB+zrj1mCIJri4vtkFNPfYXZCM/cAoQuuQxmxjk6yF6f64xSUeV V6xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=qmJiB7lB+dvr1o+yo/genv3gkUodKqwbvfDSuvcwh7M=; b=qcPMv07YrX6vWu6Osa5Lv2K3Bg4VJIqdEw3arwWgUUEEW0FGUwHLGD6nUP3GcVbqgW IEoIndv+k63J/pRlidzeLXbehhkaAaHK9C7uewS4zFY2yGiOVkWki0LwBcKWfis5HRR4 6LDxdVAUHSURsGSxCTkppUkQVkPFkYfV0uwubMbf29b/J0ykxkzyfYVDtZGoBCYMObL0 apTuJDO7L4hXc28WMB422Q/B/tYAC1XnIbJlQQ6WgzW78XUEPhs5xBbkmbn78qvaeTG4 PBAyymKZxIv56RsK+7Cv9rkM3UJXeVPxRtzfYmY09VttslEsjyAeYoh7dlf5jqEZaqKd kO0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=SewWDnqo; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b12-20020a056402138c00b00461c314f79fsi5782447edv.284.2022.11.21.07.11.22; Mon, 21 Nov 2022 07:11:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=SewWDnqo; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231376AbiKUOwe (ORCPT + 99 others); Mon, 21 Nov 2022 09:52:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231261AbiKUOvx (ORCPT ); Mon, 21 Nov 2022 09:51:53 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8267D53B8; Mon, 21 Nov 2022 06:43:15 -0800 (PST) Message-ID: <20221121140050.133104126@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041605; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qmJiB7lB+dvr1o+yo/genv3gkUodKqwbvfDSuvcwh7M=; b=SewWDnqoysUZwY2PAvCoRCcC1OPvN+pqfOVStFETafSX77gkq09/4wDnr9H9cDKGCHfBrl /Sji0uokjKN8s8bpnt1/I2cbg/Xs6pYcvCSZudNEstb4J6E//K4Jwnin9Hpbuczfjcod3T rIoZgZOrTROfoy+FioxNT5MpzPjafM3ZuR4h7IzC0tKFk59/u1xX1T2/zvMNgEpwtCDiE9 ZSBaokGfsXo7SJu8yjfQ6n2coE4m9y6fKcHazxADAvHXEnF/mvq3b+M7EQoXkPw503DFol 4BAF47XsCSGFmAl2V6PvLRYqNeZQ9px82wxNpZzz4aSyQA+k84pX/pNV3Yledg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041605; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qmJiB7lB+dvr1o+yo/genv3gkUodKqwbvfDSuvcwh7M=; b=kstALqzR6emQvai0k5knVo/BHPAWBt3K2qykTwvCvy+d5gAK1yJ7IgMLcRd2xQ9R5qVKFq UsktR2VG8sf4XuBg== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 29/40] genirq/gic-v3-mbi: Remove unused wired MSI mechanics References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:04 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118967409079457?= X-GMAIL-MSGID: =?utf-8?q?1750118967409079457?= Nothing builds a platform_device MSI domain for wire to MSI on top of this. The "regular" users of the platform MSI domain just provide their own irq_write_msi_msg() callback. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3-mbi.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -199,31 +199,16 @@ static int mbi_allocate_pci_domain(struc } #endif -static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg) -{ - mbi_compose_msi_msg(data, msg); - - msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); - msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR); - msg[1].data = data->parent_data->hwirq; - - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]); -} - /* Platform-MSI specific irqchip */ static struct irq_chip mbi_pmsi_irq_chip = { .name = "pMSI", - .irq_set_type = irq_chip_set_type_parent, - .irq_compose_msi_msg = mbi_compose_mbi_msg, - .flags = IRQCHIP_SUPPORTS_LEVEL_MSI, }; static struct msi_domain_ops mbi_pmsi_ops = { }; static struct msi_domain_info mbi_pmsi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_LEVEL_CAPABLE), + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), .ops = &mbi_pmsi_ops, .chip = &mbi_pmsi_irq_chip, }; From patchwork Mon Nov 21 14:40:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23866 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1645330wrr; Mon, 21 Nov 2022 07:10:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf6pX1dopTsROjQhQGR0FW5tbFn8hAzyyf2lIBU4p+OX4pHTHSFq0W55oUabxPAMnE9ETbJX X-Received: by 2002:a17:906:19d7:b0:7b2:b782:e1df with SMTP id h23-20020a17090619d700b007b2b782e1dfmr11891344ejd.308.1669043417403; Mon, 21 Nov 2022 07:10:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043417; cv=none; d=google.com; s=arc-20160816; b=Wru9BzfM4nCXTqQJXZEKMaOX9lE9eS2v9aEQzj5r2b9vo0hggmdDygPTx28xLn6PsW isiaBFQqBnm6DZ0Z4g2XnkBfc143S2qPYwhzEHQvkqiyP/DyRuL1dQkRfOm9Qo3qK28O 14KLKfZtSuzPKlSAR9xzl3KXaHKarAAQRSOzdi058UEVgwsXxoJGdr+fWot5Eb3hjjHA aRhpIO2wnqPvJEQ7s56Orgna8FOpborzMDV2YGQOzH+YzxswqlJF1XEDdNWGzPyM3vBl K3eVY+qhbDh36gh/mETh19uusEC7TN8PUPawlp0JORuHLmsk2+I2PjZC0bcIdDmnt/4O k9+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=G8YuXi8Rg+vVdoNzuTDwjeofGOju3zeDQbEjL5nZHEE=; b=n4MQlBqrx7J/25zT+Qw1yCNYvxdaovnvT077496CsPbbU6iqWroY0+xskky2JkrCnV L2aPsGWhlhOGYB6cQ6EhQgH2JHFKkkaVPi7jU1PMbooLoRwmTrMYhaCwzNwVMl694IHa LahUmaJ+8OHvRAv37jln1E9/Kb9JwvOQY14Rjt4osFVnsQywy9yKnm9GPDvwLeeMbv3E wtLltHyLFIRwwVsOQxZqoaG3xXturjiucViMKnAkJb12qcn+EZ1qtZnDBeFeC3nFBV2J c9TES5GcExZtRHj9D0Bccihqx9km6jwRB9oOa6LNSHGyeYKxG+vZ4X7sMWLe66puQcM6 0Ocw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YOQKK2nn; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j6-20020a05640211c600b00461f285ce57si10686127edw.211.2022.11.21.07.09.40; Mon, 21 Nov 2022 07:10:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YOQKK2nn; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231544AbiKUOvD (ORCPT + 99 others); Mon, 21 Nov 2022 09:51:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231936AbiKUOu3 (ORCPT ); Mon, 21 Nov 2022 09:50:29 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4349AE52; Mon, 21 Nov 2022 06:42:38 -0800 (PST) Message-ID: <20221121140050.197229661@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041606; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=G8YuXi8Rg+vVdoNzuTDwjeofGOju3zeDQbEjL5nZHEE=; b=YOQKK2nnOQ1IXPk9vH/EagvBlX6G4xVHr8a6G+uky088c975d+5Hndkbp3K6I2MGh4Ee8b 0uKnQjJ1smsvhKfyxTDlLRXTwZ3TnX+wkwM+ORJuD/yAwRdqu2krdi6HIf5rbsWT5RpicW ksb0oojIrgGmL1d8toGHW2jgevHFFPzGBnbCUolDZDrgxk13tixqJwZwORrJ1RECz0XRwk +CbRdACwFYv3ff5yXBONXQSqsBrEWl/nM/e2jzg5oBVczrRNKm6ffwZH1s5dkPuhny7vmm SGoffbJIgjO9ksJiBftVQFLyhMZKxLD8PF6yZRTERgxt5bNwzx7XMyTH4WRWKg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041606; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=G8YuXi8Rg+vVdoNzuTDwjeofGOju3zeDQbEjL5nZHEE=; b=1lmfc7siUnz/pvs8AAkAZagUcCbTHY8LDY3w77W70/CxajfzItxvOszV2S0J4L8f6hyx28 7gqM6d8r3MA7+zDw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 30/40] genirq/gic-v3-mbi: Switch to MSI parent References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:06 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118870125037429?= X-GMAIL-MSGID: =?utf-8?q?1750118870125037429?= All platform MSI users and the PCI/MSI code handle per device MSI domains when the irqdomain associated to the device provides MSI parent functionality. Remove the "global" PCI/MSI and platform domain related code and provide the MSI parent functionality by filling in msi_parent_ops. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/irq-gic-v3-mbi.c | 122 ++++++++++----------------------------- 1 file changed, 32 insertions(+), 90 deletions(-) --- a/drivers/irqchip/irq-gic-v3-mbi.c +++ b/drivers/irqchip/irq-gic-v3-mbi.c @@ -18,6 +18,8 @@ #include +#include "irq-gic-msi-lib.h" + struct mbi_range { u32 spi_start; u32 nr_spis; @@ -29,6 +31,15 @@ static phys_addr_t mbi_phys_base; static struct mbi_range *mbi_ranges; static unsigned int mbi_range_nr; +static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR); + msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); + msg[0].data = data->hwirq; + + iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); +} + static struct irq_chip mbi_irq_chip = { .name = "MBI", .irq_mask = irq_chip_mask_parent, @@ -36,11 +47,11 @@ static struct irq_chip mbi_irq_chip = { .irq_eoi = irq_chip_eoi_parent, .irq_set_type = irq_chip_set_type_parent, .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_compose_msi_msg = mbi_compose_msi_msg, }; -static int mbi_irq_gic_domain_alloc(struct irq_domain *domain, - unsigned int virq, - irq_hw_number_t hwirq) +static int mbi_irq_gic_domain_alloc(struct irq_domain *domain, unsigned int virq, + irq_hw_number_t hwirq) { struct irq_fwspec fwspec; struct irq_data *d; @@ -138,85 +149,30 @@ static void mbi_irq_domain_free(struct i } static const struct irq_domain_ops mbi_domain_ops = { + .select = gic_msi_lib_irq_domain_select, .alloc = mbi_irq_domain_alloc, .free = mbi_irq_domain_free, }; -static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) -{ - msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR); - msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR); - msg[0].data = data->parent_data->hwirq; - - iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); -} - -#ifdef CONFIG_PCI_MSI -/* PCI-specific irqchip */ -static void mbi_mask_msi_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} +#define MBI_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) -static void mbi_unmask_msi_irq(struct irq_data *d) -{ - pci_msi_unmask_irq(d); - irq_chip_unmask_parent(d); -} +#define MBI_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_PCI_MSIX | \ + MSI_FLAG_MULTI_PCI_MSI) -static struct irq_chip mbi_msi_irq_chip = { - .name = "MSI", - .irq_mask = mbi_mask_msi_irq, - .irq_unmask = mbi_unmask_msi_irq, - .irq_eoi = irq_chip_eoi_parent, - .irq_compose_msi_msg = mbi_compose_msi_msg, +static const struct msi_parent_ops gic_v3_mbi_msi_parent_ops = { + .supported_flags = MBI_MSI_FLAGS_SUPPORTED, + .required_flags = MBI_MSI_FLAGS_REQUIRED, + .bus_select_token = DOMAIN_BUS_NEXUS, + .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, + .prefix = "MBI-", + .init_dev_msi_info = gic_msi_lib_init_dev_msi_info, }; -static struct msi_domain_info mbi_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), - .chip = &mbi_msi_irq_chip, -}; - -static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain, - struct irq_domain **pci_domain) -{ - *pci_domain = pci_msi_create_irq_domain(nexus_domain->parent->fwnode, - &mbi_msi_domain_info, - nexus_domain); - if (!*pci_domain) - return -ENOMEM; - - return 0; -} -#else -static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain, - struct irq_domain **pci_domain) +static int mbi_allocate_domain(struct irq_domain *parent) { - *pci_domain = NULL; - return 0; -} -#endif - -/* Platform-MSI specific irqchip */ -static struct irq_chip mbi_pmsi_irq_chip = { - .name = "pMSI", -}; - -static struct msi_domain_ops mbi_pmsi_ops = { -}; - -static struct msi_domain_info mbi_pmsi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), - .ops = &mbi_pmsi_ops, - .chip = &mbi_pmsi_irq_chip, -}; - -static int mbi_allocate_domains(struct irq_domain *parent) -{ - struct irq_domain *nexus_domain, *pci_domain, *plat_domain; - int err; + struct irq_domain *nexus_domain; nexus_domain = irq_domain_create_tree(parent->fwnode, &mbi_domain_ops, NULL); @@ -225,22 +181,8 @@ static int mbi_allocate_domains(struct i irq_domain_update_bus_token(nexus_domain, DOMAIN_BUS_NEXUS); nexus_domain->parent = parent; - - err = mbi_allocate_pci_domain(nexus_domain, &pci_domain); - - plat_domain = platform_msi_create_irq_domain(parent->fwnode, - &mbi_pmsi_domain_info, - nexus_domain); - - if (err || !plat_domain) { - if (plat_domain) - irq_domain_remove(plat_domain); - if (pci_domain) - irq_domain_remove(pci_domain); - irq_domain_remove(nexus_domain); - return -ENOMEM; - } - + nexus_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + nexus_domain->msi_parent_ops = &gic_v3_mbi_msi_parent_ops; return 0; } @@ -303,7 +245,7 @@ int __init mbi_init(struct fwnode_handle pr_info("Using MBI frame %pa\n", &mbi_phys_base); - ret = mbi_allocate_domains(parent); + ret = mbi_allocate_domain(parent); if (ret) goto err_free_mbi; From patchwork Mon Nov 21 14:40:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23870 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1645804wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id nb17-20020a1709071c9100b007a858ead52dsi10733738ejc.732.2022.11.21.07.10.32; Mon, 21 Nov 2022 07:10:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="XMY0/akl"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4tDuoDhU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231915AbiKUOvl (ORCPT + 99 others); Mon, 21 Nov 2022 09:51:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230218AbiKUOvB (ORCPT ); Mon, 21 Nov 2022 09:51:01 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F16D5C847B; Mon, 21 Nov 2022 06:42:55 -0800 (PST) Message-ID: <20221121140050.259338252@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041607; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LVm6nNGwtgSWM//zSE7+IPj0DIZ/wlOjErT0DctjfGc=; b=XMY0/aklG+0k/tRYaPhi5x90nI4mKx0Ql4nnjWc3HnN51vG9bxj8tKRyrjPGICq0Kx+JXj ejhE8rAsnVIcPxDJM4Lfp0m6UkRjAqh1QmZMH8JGzeUNb5i4NXbAEt+XZOVMQWZ6KecqV7 bOg9RSyqozz2tJQps+SNw5KRe7GlGCmdA2U5o5YjUxfYDi/Lznho1QRke6RxbnJpa18jP0 WvhDA/oTGuSbhd568PqYOwelQifrT7UgkT5p1qlZBJ8Y/oF9nV7/7NAJIVknw7Em2Ek9SH 1yzAiO3Y5VjV2NCghkU4A5j85MNWCEpJkx94r4omrJOHlz6eRfhCmwRTB8MQUg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041607; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=LVm6nNGwtgSWM//zSE7+IPj0DIZ/wlOjErT0DctjfGc=; b=4tDuoDhUQ8Gc4et3llk3JdGY/T8p2yInJQLbvxnH91jqoTvRhbM+Uyj9miSI0uImQC2Guu XuL2dT19oPmENYCQ== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 31/40] irqchip/gic-v2m: Switch to device MSI References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:07 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118913502620344?= X-GMAIL-MSGID: =?utf-8?q?1750118913502620344?= All platform MSI users and the PCI/MSI code handle per device MSI domains when the irqdomain associated to the device provides MSI parent functionality. Remove the "global" PCI/MSI and platform domain related code and provide the MSI parent functionality by filling in msi_parent_ops. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/Kconfig | 1 drivers/irqchip/irq-gic-v2m.c | 82 ++++++++++++------------------------------ 2 files changed, 25 insertions(+), 58 deletions(-) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -25,6 +25,7 @@ config ARM_GIC_V2M bool depends on PCI select ARM_GIC + select ARM_GIC_MSI_LIB select PCI_MSI config GIC_NON_BANKED --- a/drivers/irqchip/irq-gic-v2m.c +++ b/drivers/irqchip/irq-gic-v2m.c @@ -26,6 +26,8 @@ #include #include +#include "irq-gic-msi-lib.h" + /* * MSI_TYPER: * [31:26] Reserved @@ -72,31 +74,6 @@ struct v2m_data { u32 flags; /* v2m flags for specific implementation */ }; -static void gicv2m_mask_msi_irq(struct irq_data *d) -{ - pci_msi_mask_irq(d); - irq_chip_mask_parent(d); -} - -static void gicv2m_unmask_msi_irq(struct irq_data *d) -{ - pci_msi_unmask_irq(d); - irq_chip_unmask_parent(d); -} - -static struct irq_chip gicv2m_msi_irq_chip = { - .name = "MSI", - .irq_mask = gicv2m_mask_msi_irq, - .irq_unmask = gicv2m_unmask_msi_irq, - .irq_eoi = irq_chip_eoi_parent, -}; - -static struct msi_domain_info gicv2m_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), - .chip = &gicv2m_msi_irq_chip, -}; - static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq) { if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) @@ -230,6 +207,7 @@ static void gicv2m_irq_domain_free(struc } static const struct irq_domain_ops gicv2m_domain_ops = { + .select = gic_msi_lib_irq_domain_select, .alloc = gicv2m_irq_domain_alloc, .free = gicv2m_irq_domain_free, }; @@ -250,19 +228,6 @@ static bool is_msi_spi_valid(u32 base, u return true; } -static struct irq_chip gicv2m_pmsi_irq_chip = { - .name = "pMSI", -}; - -static struct msi_domain_ops gicv2m_pmsi_ops = { -}; - -static struct msi_domain_info gicv2m_pmsi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), - .ops = &gicv2m_pmsi_ops, - .chip = &gicv2m_pmsi_irq_chip, -}; - static void __init gicv2m_teardown(void) { struct v2m_data *v2m, *tmp; @@ -278,17 +243,32 @@ static void __init gicv2m_teardown(void) } } +#define GICV2M_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define GICV2M_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_PCI_MSIX | \ + MSI_FLAG_MULTI_PCI_MSI) + +static struct msi_parent_ops gicv2m_msi_parent_ops = { + .supported_flags = GICV2M_MSI_FLAGS_SUPPORTED, + .required_flags = GICV2M_MSI_FLAGS_REQUIRED, + .bus_select_token = DOMAIN_BUS_NEXUS, + .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, + .prefix = "GICv2m-", + .init_dev_msi_info = gic_msi_lib_init_dev_msi_info, +}; + static __init int gicv2m_allocate_domains(struct irq_domain *parent) { - struct irq_domain *inner_domain, *pci_domain, *plat_domain; + struct irq_domain *inner_domain; struct v2m_data *v2m; v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry); if (!v2m) return 0; - inner_domain = irq_domain_create_tree(v2m->fwnode, - &gicv2m_domain_ops, v2m); + inner_domain = irq_domain_create_tree(v2m->fwnode, &gicv2m_domain_ops, v2m); if (!inner_domain) { pr_err("Failed to create GICv2m domain\n"); return -ENOMEM; @@ -296,22 +276,8 @@ static __init int gicv2m_allocate_domain irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); inner_domain->parent = parent; - pci_domain = pci_msi_create_irq_domain(v2m->fwnode, - &gicv2m_msi_domain_info, - inner_domain); - plat_domain = platform_msi_create_irq_domain(v2m->fwnode, - &gicv2m_pmsi_domain_info, - inner_domain); - if (!pci_domain || !plat_domain) { - pr_err("Failed to create MSI domains\n"); - if (plat_domain) - irq_domain_remove(plat_domain); - if (pci_domain) - irq_domain_remove(pci_domain); - irq_domain_remove(inner_domain); - return -ENOMEM; - } - + inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + inner_domain->msi_parent_ops = &gicv2m_msi_parent_ops; return 0; } @@ -512,7 +478,7 @@ acpi_parse_madt_msi(union acpi_subtable_ pr_info("applying Amazon Graviton quirk\n"); res.end = res.start + SZ_8K - 1; flags |= GICV2M_GRAVITON_ADDRESS_ONLY; - gicv2m_msi_domain_info.flags &= ~MSI_FLAG_MULTI_PCI_MSI; + gicv2m_msi_parent_ops.supported_flags &= ~MSI_FLAG_MULTI_PCI_MSI; } if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) { From patchwork Mon Nov 21 14:40:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23868 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1645533wrr; Mon, 21 Nov 2022 07:10:36 -0800 (PST) X-Google-Smtp-Source: AA0mqf42WnZ7eZfWlDfdQ8EDL9rsTVcA49AIPsSnk9ERg6WB1p+BW0ZpCSNwD6CQAIAqaq1UL/Fk X-Received: by 2002:a17:907:8b93:b0:7b4:f258:6196 with SMTP id tb19-20020a1709078b9300b007b4f2586196mr2841678ejc.524.1669043436011; Mon, 21 Nov 2022 07:10:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043436; cv=none; d=google.com; s=arc-20160816; b=qyzu4bG1SjVi+kgfvuIlYnaPt+q5+PAPdiMKt11tPppl6ulRRVlURcWPDswvyINZRY 7gD47Zsfwtt0IAjieFnzwEYKoKOY3jonNwHT9Z6gaYU3W7ZR6Y7luul9NlfAy+9F/DTY me33n8XCUWY//8vcyUfWvkO/4fPCrlLMxPi8pLj2R3UJwYtDH71TvQMpBXOIFxqZfokb fERUfeZRhlaowKS9svwpLg7KWHkNnLa6y+SKmjOA7bCVFV3On2Y2Afugx/3ZF+cTwDbA sr8lRLJuMiVp1ssEwU9RaccVbEOHHSMw5PFX5hFYlB0cLT2ezOcGBSQyTWOV3nNDFNAv EAnQ== ARC-Message-Signature: i=1; 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To make this work with per device MSI domains provide a new feature flag and let the core code handle the setup of dev->pm_dev when set during device MSI domain creation. Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 2 ++ kernel/irq/msi.c | 2 ++ 2 files changed, 4 insertions(+) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -538,6 +538,8 @@ enum { MSI_FLAG_NOMASK_QUIRK = (1 << 7), /* Use dev->fwnode for MSI device domain creation */ MSI_FLAG_USE_DEV_FWNODE = (1 << 8), + /* Set parent->dev into domain->pm_dev on device domain creation */ + MSI_FLAG_PARENT_PM_DEV = (1 << 9), /* Mask for the generic functionality */ MSI_GENERIC_FLAGS_MASK = GENMASK(15, 0), --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -884,6 +884,8 @@ static struct irq_domain *__msi_create_i if (!domain->name && info->chip) domain->name = info->chip->name; irq_domain_update_bus_token(domain, info->bus_token); + if (info->flags & MSI_FLAG_PARENT_PM_DEV) + domain->pm_dev = parent->pm_dev; } return domain; From patchwork Mon Nov 21 14:40:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23871 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646111wrr; Mon, 21 Nov 2022 07:11:29 -0800 (PST) X-Google-Smtp-Source: AA0mqf4mxQjXawx5wU2Y3pvwD9/ckUQROhj9TfCy4WwTkFitr+p+/K6tP+2oV8eht7v9tkOompLk X-Received: by 2002:a05:6402:12d5:b0:469:885b:fcfd with SMTP id k21-20020a05640212d500b00469885bfcfdmr2147161edx.177.1669043488889; Mon, 21 Nov 2022 07:11:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043488; cv=none; d=google.com; s=arc-20160816; b=CVrtgaATyOY0Fv75sg2MJ41G+9CBcO9M7/W9tE0oz/PZImwqYHW1jWkC6zWz1qjIDB RJMw8oRbxdOApyspMu6ShYbYqHArMz7ZZ87laoxkDCWrEkvMnThFxtAEBS8TEeNCSQdQ aZZWhK6cfthITG8SRyKm7n5S38WBRbx6awP+Cg0fKv9eSmBsmUnMs6i098Y/JHkE1YOf xLS/o804lZ0bfzH+OewbKnDYhgccJE6lji7zAWvFpHJX9fpmKx3QGI3TaES5aK9hS3O1 6x+Em0gAxf+RSGiLMHSCHPR13D4ptADYXO/T1trqHigf745ByIL094VsGLZUb7kvfhUX C1zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=nXitai8NNW5ZoGV4iB4WLsBQcUEV2ql1w841y8zrkC4=; b=h4MYZjPvg5fmKO+A4DBi5oaIkfqYvOJejoPbepw7Kpa+HQPi+oReC7fB4yy5SDuPxG EGhguBxyccmhspzXfScos2grVu7goUaWRh6ffEBl66x60NED5Qp/tfN5T1REzwW645+j ZKCPG77cL5B3nmjXI34T6yjc1V43ppHRtKgCpU40Ej44gFBVReH0Omqcf4ZxQ6C5vN8e ldRk5gIrQj8eSU7P8H7rY5CXLUFyh105IKkpiXar+vgtu6hzljvF19dYpD57fIvD33m9 SMwPvGRVTxWhpUv6daO6P+DkxdYZdSUePeGzijoSihpQfFejBIQLah14MskMS2ilaCl1 hORQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZYjAx1f+; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g12-20020a1709065d0c00b0078315844537si10693076ejt.378.2022.11.21.07.10.29; Mon, 21 Nov 2022 07:11:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZYjAx1f+; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbiKUOvf (ORCPT + 99 others); Mon, 21 Nov 2022 09:51:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231847AbiKUOuz (ORCPT ); Mon, 21 Nov 2022 09:50:55 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1F05D5388; Mon, 21 Nov 2022 06:42:53 -0800 (PST) Message-ID: <20221121140050.386216606@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041610; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nXitai8NNW5ZoGV4iB4WLsBQcUEV2ql1w841y8zrkC4=; b=ZYjAx1f+bZbDKdv0NCiPkFN8hoq6CJWlh96007mt0tRK0Ub323b+2n517CIn0+NrKI0snq 4m32CtJ6w+66nzOz7nnHU2Ae6NJGZaq/QDWLulrNXg1KVZAK37sdI9NKZgxLg9pllh4TJc pBM3J8f8kHcz4v+5tRqEJElXW2LacXj8w8Pv2ljOuhIkAmBFMCQefIOgu8W/JSnUGhH/5A nnWC60NaYZZf8pdR82dGpLivH139/emTx4OQg0Q0OnvobUm02Qds0CsU/Z0zdK5KQiT6Xd Dhp+Dm1uI0MjfoRze8bR2A0PhBwyoZqa1cFlCEXqpZrP7pMDI8FLJPHAPHbp4A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041610; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=nXitai8NNW5ZoGV4iB4WLsBQcUEV2ql1w841y8zrkC4=; b=hVEfbaTkojXgD9cFeu7P71Xwu6mIMOCS255HaFo1vemiQOefBL/PBPbky/jxxsmaJJ7YQr MTYUcEIZIv9lIgBA== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 33/40] irqchip/imx-mu-msi: Switch to MSI parent References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:09 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118945749345966?= X-GMAIL-MSGID: =?utf-8?q?1750118945749345966?= All platform MSI users and the PCI/MSI code handle per device MSI domains when the irqdomain associated to the device provides MSI parent functionality. Remove the "global" platform domain related code and provide the MSI parent functionality by filling in msi_parent_ops. Signed-off-by: Thomas Gleixner Cc: Thomas Gleixner Cc: Marc Zyngier Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam --- drivers/irqchip/Kconfig | 1 drivers/irqchip/irq-gic-msi-lib.c | 2 + drivers/irqchip/irq-imx-mu-msi.c | 53 +++++++++++++++----------------------- 3 files changed, 25 insertions(+), 31 deletions(-) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -494,6 +494,7 @@ config IMX_MU_MSI select IRQ_DOMAIN select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ + select ARM_GIC_MSI_LIB help Provide a driver for the i.MX Messaging Unit block used as a CPU-to-CPU MSI controller. This requires a specially crafted DT --- a/drivers/irqchip/irq-gic-msi-lib.c +++ b/drivers/irqchip/irq-gic-msi-lib.c @@ -90,6 +90,8 @@ bool gic_msi_lib_init_dev_msi_info(struc /* Chip updates for all child bus types */ if (!info->chip->irq_eoi) info->chip->irq_eoi = irq_chip_eoi_parent; + if (!info->chip->irq_ack) + info->chip->irq_ack = irq_chip_ack_parent; /* * The device MSI domain can never have a set affinity callback it --- a/drivers/irqchip/irq-imx-mu-msi.c +++ b/drivers/irqchip/irq-imx-mu-msi.c @@ -24,6 +24,8 @@ #include #include +#include "irq-gic-msi-lib.h" + #define IMX_MU_CHANS 4 enum imx_mu_xcr { @@ -114,20 +116,6 @@ static void imx_mu_msi_parent_ack_irq(st imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4); } -static struct irq_chip imx_mu_msi_irq_chip = { - .name = "MU-MSI", - .irq_ack = irq_chip_ack_parent, -}; - -static struct msi_domain_ops imx_mu_msi_irq_ops = { -}; - -static struct msi_domain_info imx_mu_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), - .ops = &imx_mu_msi_irq_ops, - .chip = &imx_mu_msi_irq_chip, -}; - static void imx_mu_msi_parent_compose_msg(struct irq_data *data, struct msi_msg *msg) { @@ -195,6 +183,7 @@ static void imx_mu_msi_domain_irq_free(s } static const struct irq_domain_ops imx_mu_msi_domain_ops = { + .select = gic_msi_lib_irq_domain_select, .alloc = imx_mu_msi_domain_irq_alloc, .free = imx_mu_msi_domain_irq_free, }; @@ -216,35 +205,37 @@ static void imx_mu_msi_irq_handler(struc chained_irq_exit(chip, desc); } +#define IMX_MU_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS | \ + MSI_FLAG_PARENT_PM_DEV) + +#define IMX_MU_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK) + +static const struct msi_parent_ops imx_mu_msi_parent_ops = { + .supported_flags = IMX_MU_MSI_FLAGS_SUPPORTED, + .required_flags = IMX_MU_MSI_FLAGS_REQUIRED, + .bus_select_token = DOMAIN_BUS_NEXUS, + .bus_select_mask = MATCH_PLATFORM_MSI, + .prefix = "MU-MSI-", + .init_dev_msi_info = gic_msi_lib_init_dev_msi_info, +}; + static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev) { struct fwnode_handle *fwnodes = dev_fwnode(dev); struct irq_domain *parent; /* Initialize MSI domain parent */ - parent = irq_domain_create_linear(fwnodes, - IMX_MU_CHANS, - &imx_mu_msi_domain_ops, - msi_data); + parent = irq_domain_create_linear(fwnodes, IMX_MU_CHANS, &imx_mu_msi_domain_ops, msi_data); if (!parent) { dev_err(dev, "failed to create IRQ domain\n"); return -ENOMEM; } irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); - - msi_data->msi_domain = platform_msi_create_irq_domain(fwnodes, - &imx_mu_msi_domain_info, - parent); - - if (!msi_data->msi_domain) { - dev_err(dev, "failed to create MSI domain\n"); - irq_domain_remove(parent); - return -ENOMEM; - } - - irq_domain_set_pm_device(msi_data->msi_domain, dev); - + parent->dev = parent->pm_dev = dev; + parent->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + parent->msi_parent_ops = &imx_mu_msi_parent_ops; return 0; } From patchwork Mon Nov 21 14:40:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23878 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646456wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w8-20020aa79548000000b0056d8f42a69csi10499083pfq.145.2022.11.21.07.11.40; Mon, 21 Nov 2022 07:11:59 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=WZM46VMu; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231534AbiKUOwo (ORCPT + 99 others); Mon, 21 Nov 2022 09:52:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231888AbiKUOvz (ORCPT ); Mon, 21 Nov 2022 09:51:55 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B50CD9043; Mon, 21 Nov 2022 06:43:16 -0800 (PST) Message-ID: <20221121140050.450294627@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041611; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JQNj2efQHu5+rY5wiZgLPG62/dR4d8wZTuePfy6MX5I=; b=WZM46VMuDWnGQidFfKDaLidgydx5WjMuaj/EUzPtBp9YBqrfO+ggWmqc8anMf9ig2Dnf/V lINuXizBV6HNAWenzAyXHCy8dItHQypiIA+YXlrf16JVw6xmRTw4uyq82ezqgkDl0H4zUY W/WLPugXnzvJ7IV+FHAoHGJpUYHuegd+hOoVnTj0g3AnJN5QDapxVtgt0NiuSBijXs+Uae oDq/sgIAt9CQ3j9fgciKsn0Zyy4Bv4XE7D6365dPgvKXla5QsHIoFgFnnIGwSuvPFAgRcJ N+BXmyRasREkPPlbj6rHYOd6VBvMZJBxnlRsQeRXyIdqOOhdmlmuU+cDMAv0aw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041611; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JQNj2efQHu5+rY5wiZgLPG62/dR4d8wZTuePfy6MX5I=; b=iY7zODOzabGxCsVgoG+R9UwXFnScPwXafGEgTeqKfmDpgQ57lm9bGVKu0PfY2vgcNExo5m 80X4X+Oktzl/IQBw== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 34/40] irqchip/irq-mvebu-icu: Prepare for real per device MSI References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:11 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118977974749578?= X-GMAIL-MSGID: =?utf-8?q?1750118977974749578?= The core infrastructure has everything in place to switch ICU to per device MSI domains and avoid the convoluted construct of the existing platform-MSI layering violation. The new infrastructure provides a wired interrupt specific interface in the MSI core which converts the 'hardware interrupt number + trigger type' allocation which is required for wired interrupts in the regular irqdomain code to a normal MSI allocation. The hardware interrupt number and the trigger type are stored in the MSI descriptor device cookie by the core code so the ICU specific code can retrieve them. The new per device domain is only instantiated when the irqdomain which is associated to the ICU device provides MSI parent functionality. Up to that point it invokes the existing code. Once the parent is converted the code for the current platform-MSI mechanism is removed. The new domain shares the interrupt chip callbacks and the translation function. The only new functionality aside of filling out the msi_domain_templates is a domain specific set_desc() callback, which will go away once all platform-MSI code has been converted. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth --- drivers/irqchip/irq-mvebu-icu.c | 181 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 170 insertions(+), 11 deletions(-) --- a/drivers/irqchip/irq-mvebu-icu.c +++ b/drivers/irqchip/irq-mvebu-icu.c @@ -20,6 +20,8 @@ #include #include +#include "irq-gic-msi-lib.h" + #include /* ICU registers */ @@ -60,14 +62,52 @@ struct mvebu_icu_msi_data { const struct mvebu_icu_subset_data *subset_data; }; -struct mvebu_icu_irq_data { - struct mvebu_icu *icu; - unsigned int icu_group; - unsigned int type; -}; - static DEFINE_STATIC_KEY_FALSE(legacy_bindings); +static int mvebu_icu_translate(struct irq_domain *d, struct irq_fwspec *fwspec, + unsigned long *hwirq, unsigned int *type) +{ + unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2; + struct mvebu_icu_msi_data *msi_data = d->host_data; + struct mvebu_icu *icu = msi_data->icu; + + /* Check the count of the parameters in dt */ + if (WARN_ON(fwspec->param_count != param_count)) { + dev_err(icu->dev, "wrong ICU parameter count %d\n", + fwspec->param_count); + return -EINVAL; + } + + if (static_branch_unlikely(&legacy_bindings)) { + *hwirq = fwspec->param[1]; + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + if (fwspec->param[0] != ICU_GRP_NSR) { + dev_err(icu->dev, "wrong ICU group type %x\n", + fwspec->param[0]); + return -EINVAL; + } + } else { + *hwirq = fwspec->param[0]; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + /* + * The ICU receives level interrupts. While the NSR are also + * level interrupts, SEI are edge interrupts. Force the type + * here in this case. Please note that this makes the interrupt + * handling unreliable. + */ + if (msi_data->subset_data->icu_group == ICU_GRP_SEI) + *type = IRQ_TYPE_EDGE_RISING; + } + + if (*hwirq >= ICU_MAX_IRQS) { + dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq); + return -EINVAL; + } + + return 0; +} + static void mvebu_icu_init(struct mvebu_icu *icu, struct mvebu_icu_msi_data *msi_data, struct msi_msg *msg) @@ -89,6 +129,14 @@ static void mvebu_icu_init(struct mvebu_ writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al); } +/* Start of area to be removed once all parent chips provide MSI parent */ + +struct mvebu_icu_irq_data { + struct mvebu_icu *icu; + unsigned int icu_group; + unsigned int type; +}; + static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) { struct irq_data *d = irq_get_irq_data(desc->irq); @@ -269,6 +317,109 @@ static const struct irq_domain_ops mvebu .free = mvebu_icu_irq_domain_free, }; +/* End of removal area */ + +static int mvebu_icu_msi_init(struct irq_domain *domain, struct msi_domain_info *info, + unsigned int virq, irq_hw_number_t hwirq, msi_alloc_info_t *arg) +{ + irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip, info->chip_data); + return irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false); +} + +static void mvebu_icu_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) +{ + arg->desc = desc; + arg->hwirq = (u32)desc->data.icookie.value; +} + +static void mvebu_icu_write_msi_msg(struct irq_data *d, struct msi_msg *msg) +{ + struct mvebu_icu_msi_data *msi_data = d->chip_data; + unsigned int icu_group = msi_data->subset_data->icu_group; + struct msi_desc *desc = irq_data_get_msi_desc(d); + struct mvebu_icu *icu = msi_data->icu; + unsigned int type; + u32 icu_int; + + if (msg->address_lo || msg->address_hi) { + /* One off initialization per domain */ + mvebu_icu_init(icu, msi_data, msg); + /* Configure the ICU with irq number & type */ + icu_int = msg->data | ICU_INT_ENABLE; + type = (unsigned int)(desc->data.icookie.value >> 32); + if (type & IRQ_TYPE_EDGE_RISING) + icu_int |= ICU_IS_EDGE; + icu_int |= icu_group << ICU_GROUP_SHIFT; + } else { + /* De-configure the ICU */ + icu_int = 0; + } + + writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); + + /* + * The SATA unit has 2 ports, and a dedicated ICU entry per + * port. The ahci sata driver supports only one irq interrupt + * per SATA unit. To solve this conflict, we configure the 2 + * SATA wired interrupts in the south bridge into 1 GIC + * interrupt in the north bridge. Even if only a single port + * is enabled, if sata node is enabled, both interrupts are + * configured (regardless of which port is actually in use). + */ + if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) { + writel_relaxed(icu_int, icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); + writel_relaxed(icu_int, icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); + } +} + +static const struct msi_domain_template mvebu_icu_nsr_msi_template = { + .chip = { + .name = "ICU-NSR", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_type = irq_chip_set_type_parent, + .irq_write_msi_msg = mvebu_icu_write_msi_msg, + .flags = IRQCHIP_SUPPORTS_LEVEL_MSI, + }, + + .ops = { + .msi_translate = mvebu_icu_translate, + .msi_init = mvebu_icu_msi_init, + .set_desc = mvebu_icu_set_desc, + }, + + .info = { + .bus_token = DOMAIN_BUS_WIRED_TO_MSI, + .flags = MSI_FLAG_LEVEL_CAPABLE | + MSI_FLAG_USE_DEV_FWNODE, + }, +}; + +static const struct msi_domain_template mvebu_icu_sei_msi_template = { + .chip = { + .name = "ICU-SEI", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_ack = irq_chip_ack_parent, + .irq_set_type = irq_chip_set_type_parent, + .irq_write_msi_msg = mvebu_icu_write_msi_msg, + .flags = IRQCHIP_SUPPORTS_LEVEL_MSI, + }, + + .ops = { + .msi_translate = mvebu_icu_translate, + .msi_init = mvebu_icu_msi_init, + .set_desc = mvebu_icu_set_desc, + }, + + .info = { + .bus_token = DOMAIN_BUS_WIRED_TO_MSI, + .flags = MSI_FLAG_LEVEL_CAPABLE | + MSI_FLAG_USE_DEV_FWNODE, + }, +}; + static const struct mvebu_icu_subset_data mvebu_icu_nsr_subset_data = { .icu_group = ICU_GRP_NSR, .offset_set_ah = ICU_SETSPI_NSR_AH, @@ -298,7 +449,6 @@ static const struct of_device_id mvebu_i static int mvebu_icu_subset_probe(struct platform_device *pdev) { struct mvebu_icu_msi_data *msi_data; - struct device_node *msi_parent_dn; struct device *dev = &pdev->dev; struct irq_domain *irq_domain; @@ -314,15 +464,24 @@ static int mvebu_icu_subset_probe(struct msi_data->subset_data = of_device_get_match_data(dev); } - dev->msi.domain = of_msi_get_domain(dev, dev->of_node, - DOMAIN_BUS_PLATFORM_MSI); + dev->msi.domain = of_msi_get_domain(dev, dev->of_node, DOMAIN_BUS_PLATFORM_MSI); if (!dev->msi.domain) return -EPROBE_DEFER; - msi_parent_dn = irq_domain_get_of_node(dev->msi.domain); - if (!msi_parent_dn) + if (!irq_domain_get_of_node(dev->msi.domain)) return -ENODEV; + if (irq_domain_is_msi_parent(dev->msi.domain)) { + bool sei = msi_data->subset_data->icu_group == ICU_GRP_SEI; + const struct msi_domain_template *tmpl; + + tmpl = sei ? &mvebu_icu_sei_msi_template : &mvebu_icu_nsr_msi_template; + + if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, tmpl, + ICU_MAX_IRQS, NULL, msi_data)) + return -ENOMEM; + } + irq_domain = platform_msi_create_device_tree_domain(dev, ICU_MAX_IRQS, mvebu_icu_write_msg, &mvebu_icu_domain_ops, From patchwork Mon Nov 21 14:40:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23881 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1647459wrr; Mon, 21 Nov 2022 07:13:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf7jr1ln4lVHyl0byUJOxrmgQWWRk0O+oSUILv96viTcpF/PuBVhzLDrWwUX2EcB8TyAyfZe X-Received: by 2002:a63:145e:0:b0:473:c377:b82 with SMTP id 30-20020a63145e000000b00473c3770b82mr18873949pgu.113.1669043613131; Mon, 21 Nov 2022 07:13:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043613; cv=none; d=google.com; s=arc-20160816; b=ccF2bdfQbsc15m6pbZCR52EwvgKOyMKlTqxbff5YIEVVaEL/6zYL/SnngYcmga4yoB DsodeheZqExCihi2yOp+/a9iVWYnhtlAq/+aWHur3X7yBMVksmrh0s/2WfrYqQoZllaC FrKOM+IkhJ3iiUTsyDF9VlrUAgQCD6JIhi7eayMXtLuUdDsl7/XyFTmh4NoSU+lkHteF fJ4Gg2f3v2uidAIqmICVCluJUrTqpeZOqoUqcha5fYNjYVfmbw6GDizCYNThkHFVd1Yq Su1mjgjFILgFhbGu9wjYZt9FNhtgiGNrUTPK6nIII1As5cePGxD68iHGB5DN+CRGq9D9 koEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=MWbome5dgm/wPYmMLcr+2vFNZotgfJG19zwD6ENHzgY=; b=Dsy6bVwIgzsHuKHfVnDUFI8bEiLdGa2+IU6b/oj2Hdyp1YeDbbss4VfhCw3tp8tTze e/DiERSFjSSXZ8FjSumvrSP0KvIej5ZXTavl0rtIhYDPg+mt7kFZ5IInJ+A6GUu7xac+ k7XSWyKQrIQjYr1Im9T/CHlOG9GLdF+k+Yy5MZgAjlBRP67oPHh0kM9ux9lWTygX3WrE pPeXLWD2095pKETBug0izgk+RjBt9gB/1U0TO60BfdeV0pChvYBYJMPEgpOxMl0F2MhE mVwMLVKqVWNzN4w+x1AjKQaZgwBjLVMuS9+Mv+MSgptHw800MBBid/eGHwozAgt+yt5O 4Kew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=HWoN44Km; dkim=neutral (no key) header.i=@linutronix.de header.b=aS68KBaR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Remove the "global" platform domain related code and provide the MSI parent functionality by filling in msi_parent_ops. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth --- drivers/irqchip/Kconfig | 1 drivers/irqchip/irq-mvebu-gicp.c | 44 ++++++++++++++++----------------------- 2 files changed, 20 insertions(+), 25 deletions(-) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -373,6 +373,7 @@ config MSCC_OCELOT_IRQ select GENERIC_IRQ_CHIP config MVEBU_GICP + select ARM_GIC_MSI_LIB bool config MVEBU_ICU --- a/drivers/irqchip/irq-mvebu-gicp.c +++ b/drivers/irqchip/irq-mvebu-gicp.c @@ -17,6 +17,8 @@ #include #include +#include "irq-gic-msi-lib.h" + #include #define GICP_SETSPI_NSR_OFFSET 0x0 @@ -145,32 +147,32 @@ static void gicp_irq_domain_free(struct } static const struct irq_domain_ops gicp_domain_ops = { + .select = gic_msi_lib_irq_domain_select, .alloc = gicp_irq_domain_alloc, .free = gicp_irq_domain_free, }; -static struct irq_chip gicp_msi_irq_chip = { - .name = "GICP", - .irq_set_type = irq_chip_set_type_parent, - .flags = IRQCHIP_SUPPORTS_LEVEL_MSI, -}; +#define GICP_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) -static struct msi_domain_ops gicp_msi_ops = { -}; +#define GICP_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_LEVEL_CAPABLE) -static struct msi_domain_info gicp_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | - MSI_FLAG_LEVEL_CAPABLE), - .ops = &gicp_msi_ops, - .chip = &gicp_msi_irq_chip, +static const struct msi_parent_ops gicp_msi_parent_ops = { + .supported_flags = GICP_MSI_FLAGS_SUPPORTED, + .required_flags = GICP_MSI_FLAGS_REQUIRED, + .bus_select_token = DOMAIN_BUS_GENERIC_MSI, + .bus_select_mask = MATCH_PLATFORM_MSI, + .prefix = "GICP-", + .init_dev_msi_info = gic_msi_lib_init_dev_msi_info, }; static int mvebu_gicp_probe(struct platform_device *pdev) { - struct mvebu_gicp *gicp; - struct irq_domain *inner_domain, *plat_domain, *parent_domain; + struct irq_domain *inner_domain, *parent_domain; struct device_node *node = pdev->dev.of_node; struct device_node *irq_parent_dn; + struct mvebu_gicp *gicp; int ret, i; gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL); @@ -233,17 +235,9 @@ static int mvebu_gicp_probe(struct platf if (!inner_domain) return -ENOMEM; - - plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node), - &gicp_msi_domain_info, - inner_domain); - if (!plat_domain) { - irq_domain_remove(inner_domain); - return -ENOMEM; - } - - platform_set_drvdata(pdev, gicp); - + irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_GENERIC_MSI); + inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + inner_domain->msi_parent_ops = &gicp_msi_parent_ops; return 0; } From patchwork Mon Nov 21 14:40:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23874 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646220wrr; Mon, 21 Nov 2022 07:11:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf5SZvPgmv/YVW8Jn/dSa9caGtiTpew3Q0Up6RpURG1DHejgutY9oX2vN/vl+zPP0s2JKY6c X-Received: by 2002:a17:906:4c4f:b0:7ad:a8c3:588f with SMTP id d15-20020a1709064c4f00b007ada8c3588fmr15043735ejw.687.1669043500152; Mon, 21 Nov 2022 07:11:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043500; cv=none; d=google.com; s=arc-20160816; b=Vg1WHnTC0Bno6j21dsoZHuaB54kYqlOxkb5eA6ekdfEY1IsOEQ6wbkBepT4zuvI3SU VRa5DSyofCz/g0VTkrUqdJ/vUTpSMwvDP5RHsS4yhBb39RJtcQQPjfLMZU0tmTTXfbkC m3oVX+S5RgkQsUggY2qF36APrY3RFJq0ronzey9WSducgdWecj/q3cMtNjBtyWl6AcVQ jdjR63PBUbVcGAOmvBMyz0jqaQoLmLN9D/10fBpnYjb97mzdwfnIntn+r9T7+b/TiHfk yWTQLJRJGUjT50+wrMSpeWg9P+FamwyC9t7rYq0sKLZ+BGT+bN2U4f4jaQLfkXM6MTE2 5Q3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=iMSiO35Q4nvqZnp/wnDAlFhYvzI37wmUM9mH/DHSckY=; b=NEo0WuWp+J9m3bCYpIPo+dg07jqB6lxiYu/QSiYfxgAyZX5UIlkcC8TTsCQvfrgY98 1XSfJrR4Fq6GxwZleZWHO7LquHNKLxr0W1D6m4FDKv8nJXgt0BoJARefREakgn2cDv7U iB6iFrGTbvlxKXR08/do3Zk8IzXkb2iH7uA51MIGc8/jU6R+cb+85Y8YPbL1pgyXYhVF HENOH9MNEE2KiRX2WPj8n+54kYZ2e8GCDUzjKBp200EiWUy21zWXqDJivo/XveBIFdrL feIQmEuZshIFNdAHBLukJtqyh7FHEnaX1ShceRPrOuAsxeSW/aZKs70ZYZHi7AiZVOEK PGTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KSocjNeR; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=TvgWE26I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hq6-20020a1709073f0600b007adf3ed5d20si11764806ejc.376.2022.11.21.07.11.10; Mon, 21 Nov 2022 07:11:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KSocjNeR; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=TvgWE26I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231939AbiKUOv5 (ORCPT + 99 others); Mon, 21 Nov 2022 09:51:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231860AbiKUOvV (ORCPT ); Mon, 21 Nov 2022 09:51:21 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3920D5A16; Mon, 21 Nov 2022 06:43:01 -0800 (PST) Message-ID: <20221121140050.577105827@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041613; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=iMSiO35Q4nvqZnp/wnDAlFhYvzI37wmUM9mH/DHSckY=; b=KSocjNeRJrC3ExVVlFIpdGXfkPZikicdmxhwqpVLEvE02aVnHCgmWUiumDo5550RX0DqfP 3AXLtn4ahhEdl/FmzyKSDljzwyCNLfmCVI9BhE2UOC391CLPc8plNzamAQll3Dvy8lUcJh Vm7/9jRpBiVvHQLy+5DICLjH7pOnd+sC8lXGTq1mSWfwfKcm8dUnNG940HupgIW2+tp5jx 5XeC3gmMnG3E0T+13QDLA17qT7ZZ+CMIRaSDZTekgJcAR3jv+dHDPmKUY0mHdxr/OcMhCk E5XtyDzG7dKgXEo6nZZuc3ciYBUlV4ion9s9CG1JLIhA6T6wyBPItw8VgM10zQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041613; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=iMSiO35Q4nvqZnp/wnDAlFhYvzI37wmUM9mH/DHSckY=; b=TvgWE26In1d44LFP7SA1WqKMrQFhhbqs7Wl4wsrLhksZY8jBfZXbJ9kHiv9CSa9ubjdwf6 WJFNOnZVQsFwdZBg== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 36/40] irqchip/mvebu-odmi: Switch to parent MSI References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:13 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750118957200985101?= X-GMAIL-MSGID: =?utf-8?q?1750118957200985101?= All platform MSI users and the PCI/MSI code handle per device MSI domains when the irqdomain associated to the device provides MSI parent functionality. Remove the "global" platform domain related code and provide the MSI parent functionality by filling in msi_parent_ops. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-mvebu-odmi.c | 39 ++++++++++++++++++--------------------- 2 files changed, 19 insertions(+), 21 deletions(-) --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -381,6 +381,7 @@ config MVEBU_ICU config MVEBU_ODMI bool + select ARM_GIC_MSI_LIB select GENERIC_MSI_IRQ config MVEBU_PIC --- a/drivers/irqchip/irq-mvebu-odmi.c +++ b/drivers/irqchip/irq-mvebu-odmi.c @@ -17,6 +17,9 @@ #include #include #include + +#include "irq-gic-msi-lib.h" + #include #define GICP_ODMIN_SET 0x40 @@ -141,27 +144,29 @@ static void odmi_irq_domain_free(struct } static const struct irq_domain_ops odmi_domain_ops = { + .select = gic_msi_lib_irq_domain_select, .alloc = odmi_irq_domain_alloc, .free = odmi_irq_domain_free, }; -static struct irq_chip odmi_msi_irq_chip = { - .name = "ODMI", -}; +#define ODMI_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) -static struct msi_domain_ops odmi_msi_ops = { -}; +#define ODMI_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK) -static struct msi_domain_info odmi_msi_domain_info = { - .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), - .ops = &odmi_msi_ops, - .chip = &odmi_msi_irq_chip, +static const struct msi_parent_ops odmi_msi_parent_ops = { + .supported_flags = ODMI_MSI_FLAGS_SUPPORTED, + .required_flags = ODMI_MSI_FLAGS_REQUIRED, + .bus_select_token = DOMAIN_BUS_GENERIC_MSI, + .bus_select_mask = MATCH_PLATFORM_MSI, + .prefix = "ODMI-", + .init_dev_msi_info = gic_msi_lib_init_dev_msi_info, }; static int __init mvebu_odmi_init(struct device_node *node, struct device_node *parent) { - struct irq_domain *inner_domain, *plat_domain; + struct irq_domain *inner_domain; int ret, i; if (of_property_read_u32(node, "marvell,odmi-frames", &odmis_count)) @@ -206,19 +211,11 @@ static int __init mvebu_odmi_init(struct } inner_domain->parent = irq_find_host(parent); - - plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node), - &odmi_msi_domain_info, - inner_domain); - if (!plat_domain) { - ret = -ENOMEM; - goto err_remove_inner; - } - + irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_GENERIC_MSI); + inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + inner_domain->msi_parent_ops = &odmi_msi_parent_ops; return 0; -err_remove_inner: - irq_domain_remove(inner_domain); err_unmap: for (i = 0; i < odmis_count; i++) { struct odmi_data *odmi = &odmis[i]; From patchwork Mon Nov 21 14:40:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23875 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646252wrr; Mon, 21 Nov 2022 07:11:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf75x+AzYreC7MXF1CgaW0YSKAKTfLf+JfkZVTR0Sd90CK95g+ToAPwKulfBGOmRnvzcbty2 X-Received: by 2002:a50:ff08:0:b0:461:dbcc:5176 with SMTP id a8-20020a50ff08000000b00461dbcc5176mr4611421edu.53.1669043502808; Mon, 21 Nov 2022 07:11:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043502; cv=none; d=google.com; s=arc-20160816; b=YBFJdyzOjFkV4Q9s/V301RMOuwDP5Iu7EUye49kzgEs1jN1AtjRC1ALm332AHFVZ9O y/nLwq5DpMtl6ZLW8WBTQrf6cwtzDuqL3zi5i76AXa9O15d9dYYjTjnJIZ5FhoZgZe21 d6gmJ2AlRPk090k4I6rRpG6aWmCv2InLEQZwfA5g52NdRoBWQGL448k9ribSYDsAkTrJ xpjo7homUUAQyfXDjGO8/i/1tA3bU/fn2+VgRmoRVX/+yOyKAlb6bvid4a12V82HHJVR Im1tdqtZ/n6mXvFHFjCdIXtqQV6OULErKRZuB5y9ghrj53KbYT56RoVB+xoPFrlWB/CB OV6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=KSViuYfTgwiHqkPMr1cUO/yCmI9Us9ItW7WKAB/O6sg=; b=mF2PcXkbfTfWLnL+nUT2jR1Yf+gAh/y+Yy4aPoZNSoOeMl2CsdlrgR9Mhlbi8MdYKz nwiDEvoPeBBWg3hqYscEVGtQhQnRcVtJmwJOh7MNHPvF2Z+o+Rkz9Is5odf0zme71agO wUqLF16hU0DtOW55+CZ/ESh/RCFIPhqxrx9UM/7mL2k329fFWb1s7kqR1laxmIs+Qpf7 IfDeWpiuRF08xMrysWY2Bzg9dwuiaoW3hd8h2LVJ0EMvsLkX0EgtHUje8QYWxpvtwCAD wddy8QRHJBsV7QAw/qpexigcrBGXGMZZ/r2jzXQZ5NyBp4kpZL7/szNE0vChzIa1GvSs W7+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="TF/TaBfw"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Remove the "global" platform domain related code and provide the MSI parent functionality by filling in msi_parent_ops. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth --- drivers/irqchip/irq-mvebu-sei.c | 52 +++++++++++++++------------------------- 1 file changed, 20 insertions(+), 32 deletions(-) --- a/drivers/irqchip/irq-mvebu-sei.c +++ b/drivers/irqchip/irq-mvebu-sei.c @@ -14,6 +14,8 @@ #include #include +#include "irq-gic-msi-lib.h" + /* Cause register */ #define GICP_SECR(idx) (0x0 + ((idx) * 0x4)) /* Mask register */ @@ -190,6 +192,7 @@ static void mvebu_sei_domain_free(struct } static const struct irq_domain_ops mvebu_sei_domain_ops = { + .select = gic_msi_lib_irq_domain_select, .alloc = mvebu_sei_domain_alloc, .free = mvebu_sei_domain_free, }; @@ -307,21 +310,6 @@ static const struct irq_domain_ops mvebu .free = mvebu_sei_cp_domain_free, }; -static struct irq_chip mvebu_sei_msi_irq_chip = { - .name = "SEI pMSI", - .irq_ack = irq_chip_ack_parent, - .irq_set_type = irq_chip_set_type_parent, -}; - -static struct msi_domain_ops mvebu_sei_msi_ops = { -}; - -static struct msi_domain_info mvebu_sei_msi_domain_info = { - .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS, - .ops = &mvebu_sei_msi_ops, - .chip = &mvebu_sei_msi_irq_chip, -}; - static void mvebu_sei_handle_cascade_irq(struct irq_desc *desc) { struct mvebu_sei *sei = irq_desc_get_handler_data(desc); @@ -360,10 +348,23 @@ static void mvebu_sei_reset(struct mvebu } } +#define SEI_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define SEI_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK) + +static const struct msi_parent_ops sei_msi_parent_ops = { + .supported_flags = SEI_MSI_FLAGS_SUPPORTED, + .required_flags = SEI_MSI_FLAGS_REQUIRED, + .bus_select_mask = MATCH_PLATFORM_MSI, + .bus_select_token = DOMAIN_BUS_GENERIC_MSI, + .prefix = "SEI-", + .init_dev_msi_info = gic_msi_lib_init_dev_msi_info, +}; + static int mvebu_sei_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - struct irq_domain *plat_domain; struct mvebu_sei *sei; u32 parent_irq; int ret; @@ -441,33 +442,20 @@ static int mvebu_sei_probe(struct platfo } irq_domain_update_bus_token(sei->cp_domain, DOMAIN_BUS_GENERIC_MSI); - - plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node), - &mvebu_sei_msi_domain_info, - sei->cp_domain); - if (!plat_domain) { - pr_err("Failed to create CPs MSI domain\n"); - ret = -ENOMEM; - goto remove_cp_domain; - } + sei->cp_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + sei->cp_domain->msi_parent_ops = &sei_msi_parent_ops; mvebu_sei_reset(sei); - irq_set_chained_handler_and_data(parent_irq, - mvebu_sei_handle_cascade_irq, - sei); - + irq_set_chained_handler_and_data(parent_irq, mvebu_sei_handle_cascade_irq, sei); return 0; -remove_cp_domain: - irq_domain_remove(sei->cp_domain); remove_ap_domain: irq_domain_remove(sei->ap_domain); remove_sei_domain: irq_domain_remove(sei->sei_domain); dispose_irq: irq_dispose_mapping(parent_irq); - return ret; } From patchwork Mon Nov 21 14:40:15 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id jf6-20020a170903268600b00186c3af9680si10247032plb.98.2022.11.21.07.15.06; Mon, 21 Nov 2022 07:15:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=vwn1NtVa; dkim=neutral (no key) header.i=@linutronix.de header.b=JzHCyAnu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231911AbiKUPKH (ORCPT + 99 others); Mon, 21 Nov 2022 10:10:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232076AbiKUPJr (ORCPT ); Mon, 21 Nov 2022 10:09:47 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 540DBD3395; Mon, 21 Nov 2022 07:00:16 -0800 (PST) Message-ID: <20221121140050.705171344@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1669041616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xVC5XhbyhuC0nBwKYdli0UkkPUi3eZn9huiS4dLgbno=; b=vwn1NtVaeWpzWR0KY98QBhWK1aS0jtYIfpHEqHGKLVMaKSd8dCf1wXkLuu6Do7FS+xpHRr 1bciPbQgGX83ut5KEzwdp3OkAsaHoKupl/THeC12qFTh5wWFF7gYmjMtEQMKtvJJ3T8RSY bQ2cs5o2HMkUcMcfsCLh0NRWvOcOxC6zFJPw2qi6HPO4P8aIEZzjT9nzt57xV+XYRtarwL Ur3LzSeSuoS3hzSQHWW3m8GwuXTZis6nkLGYuCOyw5u7F8lhZmgnYgFZBYLcIJ3KxKqYCD qeykij+aRKm4zK78AVpIE9DzuNd8H7016kLNM6UjlivMlTRtPF7hHeWngSK70Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1669041616; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xVC5XhbyhuC0nBwKYdli0UkkPUi3eZn9huiS4dLgbno=; b=JzHCyAnuDTPU5GhvQhVEJpvVEt48zMqZWiaEwdeeThy07eCD8lvkRskVRtDbI6tP15CtT3 iAESw3oGSii/tcDA== From: Thomas Gleixner To: LKML Cc: Will Deacon , linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Marc Zyngier , Greg Kroah-Hartman , Jason Gunthorpe , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Ammar Faizi , Robin Murphy , Lorenzo Pieralisi , Nishanth Menon , Tero Kristo , Santosh Shilimkar , linux-arm-kernel@lists.infradead.org, Vinod Koul , Sinan Kaya , Andy Gross , Bjorn Andersson , Mark Rutland , Shameerali Kolothum Thodi , Zenghui Yu , Shawn Guo , Sascha Hauer , Fabio Estevam Subject: [patch V2 38/40] irqchip/irq-mvebu-icu: Remove platform MSI leftovers References: <20221121135653.208611233@linutronix.de> MIME-Version: 1.0 Date: Mon, 21 Nov 2022 15:40:15 +0100 (CET) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750119201213727267?= X-GMAIL-MSGID: =?utf-8?q?1750119201213727267?= All related domains provide MSI parent functionality, so the fallback code to the original platform MSI implementation is not longer required. Signed-off-by: Thomas Gleixner Cc: Andrew Lunn Cc: Gregory Clement Cc: Sebastian Hesselbarth --- drivers/irqchip/irq-mvebu-icu.c | 213 +--------------------------------------- 1 file changed, 6 insertions(+), 207 deletions(-) --- a/drivers/irqchip/irq-mvebu-icu.c +++ b/drivers/irqchip/irq-mvebu-icu.c @@ -129,196 +129,6 @@ static void mvebu_icu_init(struct mvebu_ writel_relaxed(msg[1].address_lo, icu->base + subset->offset_clr_al); } -/* Start of area to be removed once all parent chips provide MSI parent */ - -struct mvebu_icu_irq_data { - struct mvebu_icu *icu; - unsigned int icu_group; - unsigned int type; -}; - -static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg) -{ - struct irq_data *d = irq_get_irq_data(desc->irq); - struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d->domain); - struct mvebu_icu_irq_data *icu_irqd = d->chip_data; - struct mvebu_icu *icu = icu_irqd->icu; - unsigned int icu_int; - - if (msg->address_lo || msg->address_hi) { - /* One off initialization per domain */ - mvebu_icu_init(icu, msi_data, msg); - /* Configure the ICU with irq number & type */ - icu_int = msg->data | ICU_INT_ENABLE; - if (icu_irqd->type & IRQ_TYPE_EDGE_RISING) - icu_int |= ICU_IS_EDGE; - icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT; - } else { - /* De-configure the ICU */ - icu_int = 0; - } - - writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq)); - - /* - * The SATA unit has 2 ports, and a dedicated ICU entry per - * port. The ahci sata driver supports only one irq interrupt - * per SATA unit. To solve this conflict, we configure the 2 - * SATA wired interrupts in the south bridge into 1 GIC - * interrupt in the north bridge. Even if only a single port - * is enabled, if sata node is enabled, both interrupts are - * configured (regardless of which port is actually in use). - */ - if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) { - writel_relaxed(icu_int, - icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID)); - writel_relaxed(icu_int, - icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID)); - } -} - -static struct irq_chip mvebu_icu_nsr_chip = { - .name = "ICU-NSR", - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, - .irq_eoi = irq_chip_eoi_parent, - .irq_set_type = irq_chip_set_type_parent, - .irq_set_affinity = irq_chip_set_affinity_parent, -}; - -static struct irq_chip mvebu_icu_sei_chip = { - .name = "ICU-SEI", - .irq_ack = irq_chip_ack_parent, - .irq_mask = irq_chip_mask_parent, - .irq_unmask = irq_chip_unmask_parent, - .irq_set_type = irq_chip_set_type_parent, - .irq_set_affinity = irq_chip_set_affinity_parent, -}; - -static int -mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, - unsigned long *hwirq, unsigned int *type) -{ - unsigned int param_count = static_branch_unlikely(&legacy_bindings) ? 3 : 2; - struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(d); - struct mvebu_icu *icu = msi_data->icu; - - /* Check the count of the parameters in dt */ - if (WARN_ON(fwspec->param_count != param_count)) { - dev_err(icu->dev, "wrong ICU parameter count %d\n", - fwspec->param_count); - return -EINVAL; - } - - if (static_branch_unlikely(&legacy_bindings)) { - *hwirq = fwspec->param[1]; - *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; - if (fwspec->param[0] != ICU_GRP_NSR) { - dev_err(icu->dev, "wrong ICU group type %x\n", - fwspec->param[0]); - return -EINVAL; - } - } else { - *hwirq = fwspec->param[0]; - *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; - - /* - * The ICU receives level interrupts. While the NSR are also - * level interrupts, SEI are edge interrupts. Force the type - * here in this case. Please note that this makes the interrupt - * handling unreliable. - */ - if (msi_data->subset_data->icu_group == ICU_GRP_SEI) - *type = IRQ_TYPE_EDGE_RISING; - } - - if (*hwirq >= ICU_MAX_IRQS) { - dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq); - return -EINVAL; - } - - return 0; -} - -static int -mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs, void *args) -{ - int err; - unsigned long hwirq; - struct irq_fwspec *fwspec = args; - struct mvebu_icu_msi_data *msi_data = platform_msi_get_host_data(domain); - struct mvebu_icu *icu = msi_data->icu; - struct mvebu_icu_irq_data *icu_irqd; - struct irq_chip *chip = &mvebu_icu_nsr_chip; - - icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL); - if (!icu_irqd) - return -ENOMEM; - - err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq, - &icu_irqd->type); - if (err) { - dev_err(icu->dev, "failed to translate ICU parameters\n"); - goto free_irqd; - } - - if (static_branch_unlikely(&legacy_bindings)) - icu_irqd->icu_group = fwspec->param[0]; - else - icu_irqd->icu_group = msi_data->subset_data->icu_group; - icu_irqd->icu = icu; - - err = platform_msi_device_domain_alloc(domain, virq, nr_irqs); - if (err) { - dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n"); - goto free_irqd; - } - - /* Make sure there is no interrupt left pending by the firmware */ - err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false); - if (err) - goto free_msi; - - if (icu_irqd->icu_group == ICU_GRP_SEI) - chip = &mvebu_icu_sei_chip; - - err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, - chip, icu_irqd); - if (err) { - dev_err(icu->dev, "failed to set the data to IRQ domain\n"); - goto free_msi; - } - - return 0; - -free_msi: - platform_msi_device_domain_free(domain, virq, nr_irqs); -free_irqd: - kfree(icu_irqd); - return err; -} - -static void -mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) -{ - struct irq_data *d = irq_get_irq_data(virq); - struct mvebu_icu_irq_data *icu_irqd = d->chip_data; - - kfree(icu_irqd); - - platform_msi_device_domain_free(domain, virq, nr_irqs); -} - -static const struct irq_domain_ops mvebu_icu_domain_ops = { - .translate = mvebu_icu_irq_domain_translate, - .alloc = mvebu_icu_irq_domain_alloc, - .free = mvebu_icu_irq_domain_free, -}; - -/* End of removal area */ - static int mvebu_icu_msi_init(struct irq_domain *domain, struct msi_domain_info *info, unsigned int virq, irq_hw_number_t hwirq, msi_alloc_info_t *arg) { @@ -448,9 +258,10 @@ static const struct of_device_id mvebu_i static int mvebu_icu_subset_probe(struct platform_device *pdev) { + const struct msi_domain_template *tmpl; struct mvebu_icu_msi_data *msi_data; struct device *dev = &pdev->dev; - struct irq_domain *irq_domain; + bool sei; msi_data = devm_kzalloc(dev, sizeof(*msi_data), GFP_KERNEL); if (!msi_data) @@ -471,26 +282,14 @@ static int mvebu_icu_subset_probe(struct if (!irq_domain_get_of_node(dev->msi.domain)) return -ENODEV; - if (irq_domain_is_msi_parent(dev->msi.domain)) { - bool sei = msi_data->subset_data->icu_group == ICU_GRP_SEI; - const struct msi_domain_template *tmpl; - - tmpl = sei ? &mvebu_icu_sei_msi_template : &mvebu_icu_nsr_msi_template; - - if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, tmpl, - ICU_MAX_IRQS, NULL, msi_data)) - return -ENOMEM; - } + sei = msi_data->subset_data->icu_group == ICU_GRP_SEI; + tmpl = sei ? &mvebu_icu_sei_msi_template : &mvebu_icu_nsr_msi_template; - irq_domain = platform_msi_create_device_tree_domain(dev, ICU_MAX_IRQS, - mvebu_icu_write_msg, - &mvebu_icu_domain_ops, - msi_data); - if (!irq_domain) { + if (!msi_create_device_irq_domain(dev, MSI_DEFAULT_DOMAIN, tmpl, + ICU_MAX_IRQS, NULL, msi_data)) { dev_err(dev, "Failed to create ICU MSI domain\n"); return -ENOMEM; } - return 0; } From patchwork Mon Nov 21 14:40:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 23873 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1646194wrr; Mon, 21 Nov 2022 07:11:37 -0800 (PST) X-Google-Smtp-Source: AA0mqf6NSGodHNDLBCoomVxlbyG7coLcYLpMAOhMZFAbp178V0uGT7qilSQgFUM+f5GDRy5qh8Bs X-Received: by 2002:a17:902:8604:b0:186:fe2d:f3cb with SMTP id f4-20020a170902860400b00186fe2df3cbmr3432016plo.132.1669043496976; Mon, 21 Nov 2022 07:11:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669043496; cv=none; d=google.com; s=arc-20160816; b=guxoq0hbmXxmZmyELpLUB5mZMz2aqa0KMuRKXMeEZqW2/4xlnauPwn4S8Kg7nxlKcr 1D6OIeTlk4TZ431nHzmaGXiQr7e3PO6uJgayKwrZFPOz3HcDq5px+/N4lGEPABSASLGH zZscm+M5KPNswRDcW+sV0dUEoqFsBL/DvItvZal/yp0KRWhQqTrwtO/vbn15vJf3F1C9 tM5ohx7JaWaUzPhX/jhFyeQOPXG3Qv3fz11byRz5nw88Cam9gg+BotQGEyau3y9UAH36 kZTnsTuXZP8Ic4lAj5Mabe61WRTT8LhAlQu8zmIZuSXk/imn7IE+vCG91BtyNZxfCzZy Nxiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=NGmCCnJedPVthQ5so0NTL3Zqtey0ARjNua+AbqFjFk0=; b=bhHgKwqt+qGWtVmzs75+tCbelLbsIH+W27VKV47tmPg7PnEgTP22ov+1HvxoIQHF3A Izgcv2LgANIdjKnt7Dpm2fUEpsEoMQGqydWGT92s7Cqc5S0MHOASuYzS20b7cB1JL9cI O9A37R/zK7ByUzdXezCzImG+KXh1HWCaYcHCI/gUuol0oarj9JLaybVG6CUwZiVy1GD4 +GiGjBLnVAioddPg5BqIeYA2q08czNGPXQ/Y+u5iElX/7eRXy37VFjMIt9g13HAIxUDe D/RvEvNqL0hIWIQZJG6iVRQb7AeIjeKZRaN6K9DGMSet6Tnfp5jVS5Zfq6AMr1L29pTj YWyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KJDqqWBZ; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Thomas Gleixner --- drivers/base/platform-msi.c | 352 -------------------------------------------- include/linux/msi.h | 31 --- kernel/irq/msi.c | 48 ------ 3 files changed, 3 insertions(+), 428 deletions(-) --- a/drivers/base/platform-msi.c +++ b/drivers/base/platform-msi.c @@ -4,357 +4,12 @@ * * Copyright (C) 2015 ARM Limited, All Rights Reserved. * Author: Marc Zyngier + * Copyright (C) 2022 Linutronix GmbH */ #include -#include -#include #include #include -#include - -/* Begin of removal area. Once everything is converted over. Cleanup the includes too! */ - -#define DEV_ID_SHIFT 21 -#define MAX_DEV_MSIS (1 << (32 - DEV_ID_SHIFT)) - -/* - * Internal data structure containing a (made up, but unique) devid - * and the callback to write the MSI message. - */ -struct platform_msi_priv_data { - struct device *dev; - void *host_data; - msi_alloc_info_t arg; - irq_write_msi_msg_t write_msg; - int devid; -}; - -/* The devid allocator */ -static DEFINE_IDA(platform_msi_devid_ida); - -#ifdef GENERIC_MSI_DOMAIN_OPS -/* - * Convert an msi_desc to a globaly unique identifier (per-device - * devid + msi_desc position in the msi_list). - */ -static irq_hw_number_t platform_msi_calc_hwirq(struct msi_desc *desc) -{ - u32 devid = desc->dev->msi.data->platform_data->devid; - - return (devid << (32 - DEV_ID_SHIFT)) | desc->msi_index; -} - -static void platform_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) -{ - arg->desc = desc; - arg->hwirq = platform_msi_calc_hwirq(desc); -} - -static int platform_msi_init(struct irq_domain *domain, - struct msi_domain_info *info, - unsigned int virq, irq_hw_number_t hwirq, - msi_alloc_info_t *arg) -{ - return irq_domain_set_hwirq_and_chip(domain, virq, hwirq, - info->chip, info->chip_data); -} - -static void platform_msi_set_proxy_dev(msi_alloc_info_t *arg) -{ - arg->flags |= MSI_ALLOC_FLAGS_PROXY_DEVICE; -} -#else -#define platform_msi_set_desc NULL -#define platform_msi_init NULL -#define platform_msi_set_proxy_dev(x) do {} while(0) -#endif - -static void platform_msi_update_dom_ops(struct msi_domain_info *info) -{ - struct msi_domain_ops *ops = info->ops; - - BUG_ON(!ops); - - if (ops->msi_init == NULL) - ops->msi_init = platform_msi_init; - if (ops->set_desc == NULL) - ops->set_desc = platform_msi_set_desc; -} - -static void platform_msi_write_msg(struct irq_data *data, struct msi_msg *msg) -{ - struct msi_desc *desc = irq_data_get_msi_desc(data); - - desc->dev->msi.data->platform_data->write_msg(desc, msg); -} - -static void platform_msi_update_chip_ops(struct msi_domain_info *info) -{ - struct irq_chip *chip = info->chip; - - BUG_ON(!chip); - if (!chip->irq_mask) - chip->irq_mask = irq_chip_mask_parent; - if (!chip->irq_unmask) - chip->irq_unmask = irq_chip_unmask_parent; - if (!chip->irq_eoi) - chip->irq_eoi = irq_chip_eoi_parent; - if (!chip->irq_set_affinity) - chip->irq_set_affinity = msi_domain_set_affinity; - if (!chip->irq_write_msi_msg) - chip->irq_write_msi_msg = platform_msi_write_msg; - if (WARN_ON((info->flags & MSI_FLAG_LEVEL_CAPABLE) && - !(chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI))) - info->flags &= ~MSI_FLAG_LEVEL_CAPABLE; -} - -/** - * platform_msi_create_irq_domain - Create a platform MSI interrupt domain - * @fwnode: Optional fwnode of the interrupt controller - * @info: MSI domain info - * @parent: Parent irq domain - * - * Updates the domain and chip ops and creates a platform MSI - * interrupt domain. - * - * Returns: - * A domain pointer or NULL in case of failure. - */ -struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent) -{ - struct irq_domain *domain; - - if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) - platform_msi_update_dom_ops(info); - if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) - platform_msi_update_chip_ops(info); - info->flags |= MSI_FLAG_DEV_SYSFS | MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | - MSI_FLAG_FREE_MSI_DESCS; - - domain = msi_create_irq_domain(fwnode, info, parent); - if (domain) - irq_domain_update_bus_token(domain, DOMAIN_BUS_PLATFORM_MSI); - - return domain; -} -EXPORT_SYMBOL_GPL(platform_msi_create_irq_domain); - -static int platform_msi_alloc_priv_data(struct device *dev, unsigned int nvec, - irq_write_msi_msg_t write_msi_msg) -{ - struct platform_msi_priv_data *datap; - int err; - - /* - * Limit the number of interrupts to 2048 per device. Should we - * need to bump this up, DEV_ID_SHIFT should be adjusted - * accordingly (which would impact the max number of MSI - * capable devices). - */ - if (!dev->msi.domain || !write_msi_msg || !nvec || nvec > MAX_DEV_MSIS) - return -EINVAL; - - if (dev->msi.domain->bus_token != DOMAIN_BUS_PLATFORM_MSI) { - dev_err(dev, "Incompatible msi_domain, giving up\n"); - return -EINVAL; - } - - err = msi_setup_device_data(dev); - if (err) - return err; - - /* Already initialized? */ - if (dev->msi.data->platform_data) - return -EBUSY; - - datap = kzalloc(sizeof(*datap), GFP_KERNEL); - if (!datap) - return -ENOMEM; - - datap->devid = ida_simple_get(&platform_msi_devid_ida, - 0, 1 << DEV_ID_SHIFT, GFP_KERNEL); - if (datap->devid < 0) { - err = datap->devid; - kfree(datap); - return err; - } - - datap->write_msg = write_msi_msg; - datap->dev = dev; - dev->msi.data->platform_data = datap; - return 0; -} - -static void platform_msi_free_priv_data(struct device *dev) -{ - struct platform_msi_priv_data *data = dev->msi.data->platform_data; - - dev->msi.data->platform_data = NULL; - ida_simple_remove(&platform_msi_devid_ida, data->devid); - kfree(data); -} - -/** - * platform_msi_domain_alloc_irqs - Allocate MSI interrupts for @dev - * @dev: The device for which to allocate interrupts - * @nvec: The number of interrupts to allocate - * @write_msi_msg: Callback to write an interrupt message for @dev - * - * Returns: - * Zero for success, or an error code in case of failure - */ -int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec, - irq_write_msi_msg_t write_msi_msg) -{ - int err; - - err = platform_msi_alloc_priv_data(dev, nvec, write_msi_msg); - if (err) - return err; - - err = msi_domain_alloc_irqs_range(dev, MSI_DEFAULT_DOMAIN, 0, nvec - 1); - if (err) - platform_msi_free_priv_data(dev); - - return err; -} -EXPORT_SYMBOL_GPL(platform_msi_domain_alloc_irqs); - -/** - * platform_msi_domain_free_irqs - Free MSI interrupts for @dev - * @dev: The device for which to free interrupts - */ -void platform_msi_domain_free_irqs(struct device *dev) -{ - msi_domain_free_irqs_all(dev, MSI_DEFAULT_DOMAIN); - platform_msi_free_priv_data(dev); -} -EXPORT_SYMBOL_GPL(platform_msi_domain_free_irqs); - -/** - * platform_msi_get_host_data - Query the private data associated with - * a platform-msi domain - * @domain: The platform-msi domain - * - * Return: The private data provided when calling - * platform_msi_create_device_domain(). - */ -void *platform_msi_get_host_data(struct irq_domain *domain) -{ - struct platform_msi_priv_data *data = domain->host_data; - - return data->host_data; -} - -static struct lock_class_key platform_device_msi_lock_class; - -/** - * __platform_msi_create_device_domain - Create a platform-msi device domain - * - * @dev: The device generating the MSIs - * @nvec: The number of MSIs that need to be allocated - * @is_tree: flag to indicate tree hierarchy - * @write_msi_msg: Callback to write an interrupt message for @dev - * @ops: The hierarchy domain operations to use - * @host_data: Private data associated to this domain - * - * Return: An irqdomain for @nvec interrupts on success, NULL in case of error. - * - * This is for interrupt domains which stack on a platform-msi domain - * created by platform_msi_create_irq_domain(). @dev->msi.domain points to - * that platform-msi domain which is the parent for the new domain. - */ -struct irq_domain * -__platform_msi_create_device_domain(struct device *dev, - unsigned int nvec, - bool is_tree, - irq_write_msi_msg_t write_msi_msg, - const struct irq_domain_ops *ops, - void *host_data) -{ - struct platform_msi_priv_data *data; - struct irq_domain *domain; - int err; - - err = platform_msi_alloc_priv_data(dev, nvec, write_msi_msg); - if (err) - return NULL; - - /* - * Use a separate lock class for the MSI descriptor mutex on - * platform MSI device domains because the descriptor mutex nests - * into the domain mutex. See alloc/free below. - */ - lockdep_set_class(&dev->msi.data->mutex, &platform_device_msi_lock_class); - - data = dev->msi.data->platform_data; - data->host_data = host_data; - domain = irq_domain_create_hierarchy(dev->msi.domain, 0, - is_tree ? 0 : nvec, - dev->fwnode, ops, data); - if (!domain) - goto free_priv; - - platform_msi_set_proxy_dev(&data->arg); - err = msi_domain_prepare_irqs(domain->parent, dev, nvec, &data->arg); - if (err) - goto free_domain; - - return domain; - -free_domain: - irq_domain_remove(domain); -free_priv: - platform_msi_free_priv_data(dev); - return NULL; -} - -/** - * platform_msi_device_domain_free - Free interrupts associated with a platform-msi - * device domain - * - * @domain: The platform-msi device domain - * @virq: The base irq from which to perform the free operation - * @nr_irqs: How many interrupts to free from @virq - */ -void platform_msi_device_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) -{ - struct platform_msi_priv_data *data = domain->host_data; - - msi_lock_descs(data->dev); - irq_domain_free_irqs_common(domain, virq, nr_irqs); - msi_free_msi_descs_range(data->dev, virq, virq + nr_irqs - 1); - msi_unlock_descs(data->dev); -} - -/** - * platform_msi_device_domain_alloc - Allocate interrupts associated with - * a platform-msi device domain - * - * @domain: The platform-msi device domain - * @virq: The base irq from which to perform the allocate operation - * @nr_irqs: How many interrupts to allocate from @virq - * - * Return 0 on success, or an error code on failure. Must be called - * with irq_domain_mutex held (which can only be done as part of a - * top-level interrupt allocation). - */ -int platform_msi_device_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) -{ - struct platform_msi_priv_data *data = domain->host_data; - struct device *dev = data->dev; - - return msi_domain_populate_irqs(domain->parent, dev, virq, nr_irqs, &data->arg); -} - -/* End of removal area */ - -/* Real per device domain interfaces */ /* * This indirection can go when platform_device_ims_init_and_alloc_irqs() @@ -415,15 +70,10 @@ int platform_device_ims_init_and_alloc_i irq_write_msi_msg_t write_msi_msg) { struct irq_domain *domain = dev->msi.domain; - int ret; if (!domain || !write_msi_msg) return -EINVAL; - /* Migration support. Will go away once everything is converted */ - if (!irq_domain_is_msi_parent(domain)) - return platform_msi_domain_alloc_irqs(dev, nvec, write_msi_msg); - /* * @write_msi_msg is stored in the resulting msi_domain_info::data. * The underlying domain creation mechanism will assign that --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -77,7 +77,6 @@ extern int pci_msi_ignore_mask; /* Helper functions */ struct msi_desc; struct pci_dev; -struct platform_msi_priv_data; struct device_attribute; struct irq_domain; struct irq_affinity_desc; @@ -216,7 +215,6 @@ enum msi_desc_filter { /** * msi_device_data - MSI per device data * @properties: MSI properties which are interesting to drivers - * @platform_data: Platform-MSI specific data * @mutex: Mutex protecting the MSI descriptor store * @__store: Xarray for storing MSI descriptor pointers * @__iter_idx: Index to search the next entry for iterators @@ -225,7 +223,6 @@ enum msi_desc_filter { */ struct msi_device_data { unsigned long properties; - struct platform_msi_priv_data *platform_data; struct mutex mutex; struct xarray __store; unsigned long __iter_idx; @@ -628,34 +625,6 @@ void msi_domain_free_irqs_all(struct dev struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain); -struct irq_domain *platform_msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent); -int platform_msi_domain_alloc_irqs(struct device *dev, unsigned int nvec, - irq_write_msi_msg_t write_msi_msg); -void platform_msi_domain_free_irqs(struct device *dev); - -/* When an MSI domain is used as an intermediate domain */ -int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, - int nvec, msi_alloc_info_t *args); -int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev, - int virq, int nvec, msi_alloc_info_t *args); -struct irq_domain * -__platform_msi_create_device_domain(struct device *dev, - unsigned int nvec, - bool is_tree, - irq_write_msi_msg_t write_msi_msg, - const struct irq_domain_ops *ops, - void *host_data); - -#define platform_msi_create_device_tree_domain(dev, nvec, write, ops, data) \ - __platform_msi_create_device_domain(dev, nvec, true, write, ops, data) - -int platform_msi_device_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs); -void platform_msi_device_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nvec); -void *platform_msi_get_host_data(struct irq_domain *domain); /* Per device platform MSI */ int platform_device_ims_init_and_alloc_irqs(struct device *dev, unsigned int nvec, irq_write_msi_msg_t write_msi_msg); --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1121,8 +1121,8 @@ bool msi_match_device_irq_domain(struct return ret; } -int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, - int nvec, msi_alloc_info_t *arg) +static int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, + int nvec, msi_alloc_info_t *arg) { struct msi_domain_info *info = domain->host_data; struct msi_domain_ops *ops = info->ops; @@ -1130,50 +1130,6 @@ int msi_domain_prepare_irqs(struct irq_d return ops->msi_prepare(domain, dev, nvec, arg); } -int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev, - int virq_base, int nvec, msi_alloc_info_t *arg) -{ - struct msi_domain_info *info = domain->host_data; - struct msi_domain_ops *ops = info->ops; - struct msi_ctrl ctrl = { - .domid = MSI_DEFAULT_DOMAIN, - .first = virq_base, - .last = virq_base + nvec - 1, - }; - struct msi_desc *desc; - int ret, virq; - - if (!msi_ctrl_range_valid(dev, &ctrl)) - return -EINVAL; - - msi_lock_descs(dev); - ret = msi_domain_add_simple_msi_descs(dev, &ctrl); - if (ret) - goto unlock; - - for (virq = virq_base; virq < virq_base + nvec; virq++) { - desc = xa_load(&dev->msi.data->__store, virq); - desc->irq = virq; - - ops->set_desc(arg, desc); - ret = irq_domain_alloc_irqs_hierarchy(domain, virq, 1, arg); - if (ret) - goto fail; - - irq_set_msi_desc(virq, desc); - } - msi_unlock_descs(dev); - return 0; - -fail: - for (--virq; virq >= virq_base; virq--) - irq_domain_free_irqs_common(domain, virq, 1); - msi_domain_free_descs(dev, &ctrl); -unlock: - msi_unlock_descs(dev); - return ret; -} - /* * Carefully check whether the device can use reservation mode. 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Signed-off-by: Thomas Gleixner --- include/linux/msi.h | 22 ---------------------- kernel/irq/msi.c | 24 ++++++++++++++++++++++-- 2 files changed, 22 insertions(+), 24 deletions(-) --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -21,11 +21,7 @@ #include #include #include -#include -#include -#include #include -#include #include @@ -212,24 +208,6 @@ enum msi_desc_filter { MSI_DESC_ASSOCIATED, }; -/** - * msi_device_data - MSI per device data - * @properties: MSI properties which are interesting to drivers - * @mutex: Mutex protecting the MSI descriptor store - * @__store: Xarray for storing MSI descriptor pointers - * @__iter_idx: Index to search the next entry for iterators - * @__iter_max: Index to limit the search - * @__irqdomains: Per device interrupt domains - */ -struct msi_device_data { - unsigned long properties; - struct mutex mutex; - struct xarray __store; - unsigned long __iter_idx; - unsigned long __iter_max; - struct irq_domain *__irqdomains[MSI_MAX_DEVICE_IRQDOMAINS]; -}; - int msi_setup_device_data(struct device *dev); void msi_lock_descs(struct device *dev); --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -8,18 +8,38 @@ * This file contains common code to support Message Signaled Interrupts for * PCI compatible and non PCI compatible devices. */ -#include #include #include #include #include +#include +#include #include #include -#include +#include +#include #include "internals.h" /** + * msi_device_data - MSI per device data + * @properties: MSI properties which are interesting to drivers + * @mutex: Mutex protecting the MSI descriptor store + * @__store: Xarray for storing MSI descriptor pointers + * @__iter_idx: Index to search the next entry for iterators + * @__iter_max: Index to limit the search + * @__irqdomains: Per device interrupt domains + */ +struct msi_device_data { + unsigned long properties; + struct mutex mutex; + struct xarray __store; + unsigned long __iter_idx; + unsigned long __iter_max; + struct irq_domain *__irqdomains[MSI_MAX_DEVICE_IRQDOMAINS]; +}; + +/** * struct msi_ctrl - MSI internal management control structure * @domid: ID of the domain on which management operations should be done * @first: First (hardware) slot index to operate on