From patchwork Mon Nov 21 09:08:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyan Thota X-Patchwork-Id: 23614 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1468708wrr; Mon, 21 Nov 2022 01:09:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf5DB/fJ1bajpF786OpdekrDF16uwxjEQRQ6NFKUW6pm0rcOraANE0ZBz5VLN1rqareDsPqR X-Received: by 2002:a17:90a:5d81:b0:212:cf2e:2b0b with SMTP id t1-20020a17090a5d8100b00212cf2e2b0bmr25442231pji.169.1669021766935; Mon, 21 Nov 2022 01:09:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669021766; cv=none; d=google.com; s=arc-20160816; b=nlno/Mjty50y4Opq04OiuZxdAXfpGVhe1JHF8BYuUuT8KY7oTMDMaBeYQNcXBZZYCs Nix4RnipZ46KhVpDg3C7+/U1U6LrgciFKOVUxk/d+jtA5Jzyvgvn9WVdz5G15BdysbS7 7HvPH7DmLbypzPSejXRUIPcEWK0hP5ajonS/ccKIz6fx2n3qHweEAV4yj5FQ9rUocd/w 2bMxQ9iBeARXymRbm5+e0+ck5cFpn9qD7fCxju5hZuhvDocbdf8cLxtUxPiL/hs226im iIsECOPgxOgLYWYFRhX5cDCnGQiNGbemxZTqPlca2HHuLEKfPMukTTMxrxZzMOmviA4E y0vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=Xbixi/D3kJQmqiT72xNXf1ix25tBfYqHviclOosD4ng=; b=zLN6ghy6K7/xCdh1YtoL+w3FNUaQiYhmRphk95xnutTYAyfKn3/bLJ9zSEKHLkjmk3 IGIipuvxprGkjdjO3zabHwE19twGsZBbT+/TzUIgTrFw3U4Hc/3cze/EE6qOAWMy4JjP +pBwoO64UdQCcb47zTjTB5GV5qXJ4f3dgsNYY84/tgctH750UJeA9LX8V6A+t7B+pb3k QmSEuAzCSHgGB5x/F8bSiSe2GDQlb+EklnwdiCRZTgIRXb2M29c32CETpQ9v6VPqT4Dr q5TnHsc4A75IB/5Np63aO3C5xCiYMbilfs5bl0zGLxIn/aoXOKE68wNdEmRF1Nf15sRk 1zCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Y4uc1L9F; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Mon, 21 Nov 2022 09:08:25 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 2AL98LMl032757; Mon, 21 Nov 2022 09:08:21 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3kxr7k3t7v-1; Mon, 21 Nov 2022 09:08:21 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2AL98Lne032751; Mon, 21 Nov 2022 09:08:21 GMT Received: from kalyant-linux.qualcomm.com (kalyant-linux.qualcomm.com [10.204.66.210]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 2AL98LmS032750; Mon, 21 Nov 2022 09:08:21 +0000 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id 4F24D349C; Mon, 21 Nov 2022 01:08:20 -0800 (PST) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Kalyan Thota , linux-kernel@vger.kernel.org, robdclark@chromium.org, dianders@chromium.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, dmitry.baryshkov@linaro.org, quic_abhinavk@quicinc.com Subject: [PATCH v4 1/3] drm/msm/disp/dpu1: pin 1 crtc to 1 encoder Date: Mon, 21 Nov 2022 01:08:13 -0800 Message-Id: <1669021695-4397-2-git-send-email-quic_kalyant@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1669021695-4397-1-git-send-email-quic_kalyant@quicinc.com> References: <1669021695-4397-1-git-send-email-quic_kalyant@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0W2KnGPIeZvLC8-_aXS-fMkQ7mxJ4YuC X-Proofpoint-ORIG-GUID: 0W2KnGPIeZvLC8-_aXS-fMkQ7mxJ4YuC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-21_06,2022-11-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211210071 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750096168127030794?= X-GMAIL-MSGID: =?utf-8?q?1750096168127030794?= Pin each crtc with one encoder. This arrangement will disallow crtc switching between encoders and also will facilitate to advertise certain features on crtc based on encoder type. Changes in v1: - use drm_for_each_encoder macro while iterating through encoder list (Dmitry) Changes in v2: - make sure no encoder miss to have a crtc (Dmitry) - revisit various factors in deciding the crtc count such as num_mixers, num_sspp (Dmitry) Changes in v3: - none Changes in v4: - use max_crtc_count instead of num_encoders in WARN (Dmitry) Reviewed-by: Dmitry Baryshkov Signed-off-by: Kalyan Thota --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 7a5fabc..d967eef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -747,6 +747,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret; int max_crtc_count; + dev = dpu_kms->dev; priv = dev->dev_private; catalog = dpu_kms->catalog; @@ -763,7 +764,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) drm_for_each_encoder(encoder, dev) num_encoders++; - max_crtc_count = min(catalog->mixer_count, num_encoders); + max_crtc_count = num_encoders; /* Create the planes, keeping track of one primary/cursor per crtc */ for (i = 0; i < catalog->sspp_count; i++) { @@ -795,22 +796,25 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) primary_planes[primary_planes_idx++] = plane; } - max_crtc_count = min(max_crtc_count, primary_planes_idx); + /* + * All the platforms should have at least 1 primary plane for a + * crtc. The below warn should help in setting up the catalog + */ + WARN_ON(max_crtc_count > primary_planes_idx); /* Create one CRTC per encoder */ - for (i = 0; i < max_crtc_count; i++) { + i = 0; + drm_for_each_encoder(encoder, dev) { crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); if (IS_ERR(crtc)) { ret = PTR_ERR(crtc); return ret; } priv->crtcs[priv->num_crtcs++] = crtc; + encoder->possible_crtcs = 1 << drm_crtc_index(crtc); + i++; } - /* All CRTCs are compatible with all encoders */ - drm_for_each_encoder(encoder, dev) - encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; - return 0; } From patchwork Mon Nov 21 09:08:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyan Thota X-Patchwork-Id: 23615 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1468879wrr; Mon, 21 Nov 2022 01:09:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf6Pyy1vMy/JZFKZaCiNdOVLI5fj8HjDsT72tN90Ctk272/EUdzAJobqxBsoT5KAfnv5YZvX X-Received: by 2002:a63:e617:0:b0:41a:4bd4:f466 with SMTP id g23-20020a63e617000000b0041a4bd4f466mr6468225pgh.499.1669021793091; Mon, 21 Nov 2022 01:09:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669021793; cv=none; d=google.com; s=arc-20160816; b=PSQFgeWS9e3mIzBrhStSaroAoZaPI3QfPO+um+jh2Ir3VdGlKpQmqsptQC7m1xmNiy gGneuNjIgryJkvccTJtvLnNkh+5EznC0PpvN/BroniZdlXo6sp7/e9gQWftYD8aknpXw V2EPerjybjMlQjkD/XfaNeT1S+roSkvgdf57TuOYKsGg2XxoZyv2cb+ywwO9rGwaUzOx EYuSMv6u0ZN5ox1IQoHZe8HjHsjp4dk9ntiUl1b9LahD70WjsLRvIaD13ksn0fnPVDvb sB1B/OfF26jZw++MLXHJGwdogv/7WRbS08p6tGc5eSjeqbMyFHQaX7A1TG5U3NjlXOMi 5ykg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=gWu3FAL7SNTqtCvUeN203XgMcssG6tMZhtleUGDkIfo=; b=MujBd3Pu2hXMnwM66TvSH7HWQ5ECpQUwugkNcD+TgJnf6y5LoN9AmU0RlF7WCuizHw 1Q4hkx+btBRJxhxn47+iNIj9HV0mJJXgcVL8GBceZO5JOlfmOufU2SxentlAtAYQm/sQ Dx2h0aLtx8TZiRG4MFqG21F2JTDRwNHM2+8Po3xEmqmytyQQc9NzipfRMJBz0CKFUuuE DlE+F3CQ3NfTs8sADB/cBRuMuw2Do2ttFv/H1UN1F0sXkk8+1qy/Bz7d8c3dpNLxLMHs hixYIPixhMUvkH3mvrxH8SGMTo3nQ7Xj5vmMFSMC2a32a1P12jlrr26+q4+IqxrUtevS lORQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=XSl7uWJd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Mon, 21 Nov 2022 09:08:26 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 2AL98MH7000301; Mon, 21 Nov 2022 09:08:22 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3kxr7k3t81-1; Mon, 21 Nov 2022 09:08:22 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2AL98JXF032737; Mon, 21 Nov 2022 09:08:22 GMT Received: from kalyant-linux.qualcomm.com (kalyant-linux.qualcomm.com [10.204.66.210]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 2AL98MDN032762; Mon, 21 Nov 2022 09:08:22 +0000 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id 3835734A4; Mon, 21 Nov 2022 01:08:21 -0800 (PST) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Kalyan Thota , linux-kernel@vger.kernel.org, robdclark@chromium.org, dianders@chromium.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, dmitry.baryshkov@linaro.org, quic_abhinavk@quicinc.com Subject: [PATCH v4 2/3] drm/msm/disp/dpu1: add helper to know if display is builtin Date: Mon, 21 Nov 2022 01:08:14 -0800 Message-Id: <1669021695-4397-3-git-send-email-quic_kalyant@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1669021695-4397-1-git-send-email-quic_kalyant@quicinc.com> References: <1669021695-4397-1-git-send-email-quic_kalyant@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VilkInZZ6Lz839DscdCPl5OGJCuSnL6J X-Proofpoint-ORIG-GUID: VilkInZZ6Lz839DscdCPl5OGJCuSnL6J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-21_05,2022-11-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=952 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211210071 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750096195835069805?= X-GMAIL-MSGID: =?utf-8?q?1750096195835069805?= Since DRM encoder type for few encoders can be similar (like eDP and DP), get the connector type for a given encoder to differentiate between builtin and pluggable displays. Changes in v1: - add connector type in the disp_info (Dmitry) - add helper functions to know encoder type - update commit text reflecting the change Changes in v2: - avoid hardcode of connector type for DSI as it may not be true (Dmitry) - get the HPD information from encoder bridge Changes in v3: - use connector type instead of bridge ops in determining connector (Dmitry) Changes in v4: - get type from the drm connector rather from bridge connector (Dmitry) Signed-off-by: Kalyan Thota Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 6 ++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 9c6817b..96db7fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -217,6 +217,32 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = { 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 }; +bool dpu_encoder_is_builtin(struct drm_encoder *encoder) +{ + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + struct drm_device *dev = encoder->dev; + int type = 0; + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + if (drm_connector_has_possible_encoder(connector, encoder)) { + type = connector->connector_type; + break; + } + } + drm_connector_list_iter_end(&conn_iter); + + switch (type) { + case DRM_MODE_CONNECTOR_LVDS: + case DRM_MODE_CONNECTOR_eDP: + case DRM_MODE_CONNECTOR_DSI: + case DRM_MODE_CONNECTOR_DPI: + return true; + default: + return false; + } +} bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 9e7236e..7f3d823 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -224,4 +224,10 @@ void dpu_encoder_cleanup_wb_job(struct drm_encoder *drm_enc, */ bool dpu_encoder_is_valid_for_commit(struct drm_encoder *drm_enc); +/** + * dpu_encoder_is_builtin - find if the encoder is of type builtin + * @drm_enc: Pointer to previously created drm encoder structure + */ +bool dpu_encoder_is_builtin(struct drm_encoder *drm_enc); + #endif /* __DPU_ENCODER_H__ */ From patchwork Mon Nov 21 09:08:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kalyan Thota X-Patchwork-Id: 23616 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp1468983wrr; Mon, 21 Nov 2022 01:10:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf5k6LmzTRy2QNw1IVrq4gtNI0HvFZTSIgYTiR7UktlaLpmvH0W8BErvsVAGGaMToWdQ+fmg X-Received: by 2002:a17:90a:7d0e:b0:218:7c5c:44b with SMTP id g14-20020a17090a7d0e00b002187c5c044bmr16973600pjl.23.1669021807180; Mon, 21 Nov 2022 01:10:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669021807; cv=none; d=google.com; s=arc-20160816; b=1CClxC2w1ovb4aWyPFKZwpfhwOWUXJmoa3KBy9C2l++cOVoXql0e063wqLJB5NBjoT tF0GZNATIa3h7qEhP8Mr9xouKWbzyOX+VEKLFROlS9/uXf/QI4Mw4okQXDAA9KOZLQJt p8dzHrGJrRZyLkfstXtI00FkzdxcnMUmNv/jCW1xss8C6bbC5f31zo2zH6X51OGnoiA3 1CxWaleFcYQuvJPUE5FC7LDnG4yLhGpm0OUuKz9cq0WU/sxR99fKLeArZE8GnlHoyu0n 9GJch/5nlD3Hb+N9kNf1uX/gEj++1oQC6RrbApwEvLJRFM3DYn98M//5gs24lIlDP5uz OXlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=1W1f8UH9EqIeBJHNQLHw8+dLhtc7tyzQLYpRIB2TrhE=; b=mTBNooJodoW5wuStqaDHg3g2RKKQnD2M8PrPjZCy97ABub6UAHjEahgNPbxjDT3D7B bLExIUYt/xz+qlwo3geiT++TTgZtYZYmBNB/nSqQ9NBKyAGqlue9KjZGpKeKAEGl1YTn b/AwaVuctRlvXmRhE8E63vGm0kzk8DRooDn12mfuQk2Xxxx6L3bIEKA3E5WgPHzL5VOh LgPPl5yadWzFMgy29f3fP65oaYB/mC9DrXw3g7dxsK2VjpGd5PeWlDUFtQSBTB66bi1H dewWHjs6ZoyhV6UDLQi9tHV4ryORswdAlZ5dZVkA4R1NTjTj9DwztrBtqTBeeOUa7FB5 tLgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=gtJqlXuW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Mon, 21 Nov 2022 09:08:27 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 2AL98LMm032757; Mon, 21 Nov 2022 09:08:24 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3kxr7k3t86-1; Mon, 21 Nov 2022 09:08:24 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2AL98OKZ000310; Mon, 21 Nov 2022 09:08:24 GMT Received: from kalyant-linux.qualcomm.com (kalyant-linux.qualcomm.com [10.204.66.210]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 2AL98Nmp000309; Mon, 21 Nov 2022 09:08:24 +0000 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id B1F28349C; Mon, 21 Nov 2022 01:08:22 -0800 (PST) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Kalyan Thota , linux-kernel@vger.kernel.org, robdclark@chromium.org, dianders@chromium.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, dmitry.baryshkov@linaro.org, quic_abhinavk@quicinc.com Subject: [PATCH v4 3/3] drm/msm/disp/dpu1: add color management support for the crtc Date: Mon, 21 Nov 2022 01:08:15 -0800 Message-Id: <1669021695-4397-4-git-send-email-quic_kalyant@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1669021695-4397-1-git-send-email-quic_kalyant@quicinc.com> References: <1669021695-4397-1-git-send-email-quic_kalyant@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: RpsPe8h3JH9O6sJxPTI8EVIBViL9TLt5 X-Proofpoint-ORIG-GUID: RpsPe8h3JH9O6sJxPTI8EVIBViL9TLt5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-21_06,2022-11-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2211210071 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750096210468666016?= X-GMAIL-MSGID: =?utf-8?q?1750096210468666016?= Add color management support for the crtc provided there are enough dspps that can be allocated from the catalog. Changes in v1: - cache color enabled state in the dpu crtc obj (Dmitry) - simplify dspp allocation while creating crtc (Dmitry) - register for color when crtc is created (Dmitry) Changes in v2: - avoid primary encoders in the documentation (Dmitry) Changes in v3: - add ctm for builtin encoders (Dmitry) Changes in v4: - few nits (Dmitry) Reviewed-by: Dmitry Baryshkov Signed-off-by: Kalyan Thota --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 +++-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 +++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 +++++- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 4170fbe..6cacaaf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1571,7 +1571,7 @@ static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { /* initialize crtc */ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, - struct drm_plane *cursor) + struct drm_plane *cursor, bool ctm) { struct drm_crtc *crtc = NULL; struct dpu_crtc *dpu_crtc = NULL; @@ -1583,6 +1583,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, crtc = &dpu_crtc->base; crtc->dev = dev; + dpu_crtc->color_enabled = ctm; spin_lock_init(&dpu_crtc->spin_lock); atomic_set(&dpu_crtc->frame_pending, 0); @@ -1604,7 +1605,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); - drm_crtc_enable_color_mgmt(crtc, 0, true, 0); + drm_crtc_enable_color_mgmt(crtc, 0, dpu_crtc->color_enabled, 0); /* save user friendly CRTC name for later */ snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h index 539b68b..792b4f0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -136,6 +136,7 @@ struct dpu_crtc_frame_event { * @enabled : whether the DPU CRTC is currently enabled. updated in the * commit-thread, not state-swap time which is earlier, so * safe to make decisions on during VBLANK on/off work + * @color_enabled : whether crtc supports color management * @feature_list : list of color processing features supported on a crtc * @active_list : list of color processing features are active * @dirty_list : list of color processing features are dirty @@ -164,6 +165,7 @@ struct dpu_crtc { u64 play_count; ktime_t vblank_cb_time; bool enabled; + bool color_enabled; struct list_head feature_list; struct list_head active_list; @@ -269,10 +271,11 @@ void dpu_crtc_complete_commit(struct drm_crtc *crtc); * @dev: dpu device * @plane: base plane * @cursor: cursor plane + * @ctm: ctm flag * @Return: new crtc object or error */ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, - struct drm_plane *cursor); + struct drm_plane *cursor, bool ctm); /** * dpu_crtc_register_custom_event - api for enabling/disabling crtc event diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 96db7fb..a585036 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -571,6 +571,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) static struct msm_display_topology dpu_encoder_get_topology( struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, + struct dpu_crtc *dpu_crtc, struct drm_display_mode *mode) { struct msm_display_topology topology = {0}; @@ -599,7 +600,7 @@ static struct msm_display_topology dpu_encoder_get_topology( else topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { + if (dpu_crtc->color_enabled) { if (dpu_kms->catalog->dspp && (dpu_kms->catalog->dspp_count >= topology.num_lm)) topology.num_dspp = topology.num_lm; @@ -634,6 +635,7 @@ static int dpu_encoder_virt_atomic_check( struct drm_display_mode *adj_mode; struct msm_display_topology topology; struct dpu_global_state *global_state; + struct dpu_crtc *dpu_crtc; int i = 0; int ret = 0; @@ -644,6 +646,7 @@ static int dpu_encoder_virt_atomic_check( } dpu_enc = to_dpu_encoder_virt(drm_enc); + dpu_crtc = to_dpu_crtc(crtc_state->crtc); DPU_DEBUG_ENC(dpu_enc, "\n"); priv = drm_enc->dev->dev_private; @@ -669,7 +672,7 @@ static int dpu_encoder_virt_atomic_check( } } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, dpu_crtc, adj_mode); /* Reserve dynamic resources now. */ if (!ret) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index d967eef..53e0163 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -805,7 +805,11 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) /* Create one CRTC per encoder */ i = 0; drm_for_each_encoder(encoder, dev) { - crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]); + bool _ctm = false; + + if (catalog->dspp_count && dpu_encoder_is_builtin(encoder)) + _ctm = true; + crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i], _ctm); if (IS_ERR(crtc)) { ret = PTR_ERR(crtc); return ret;