From patchwork Sun Nov 20 02:23:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 23372 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp945884wrr; Sat, 19 Nov 2022 18:27:30 -0800 (PST) X-Google-Smtp-Source: AA0mqf6FdTV8w8nWWJcYuQWdc44EgRHzdnWsCJ02by278oaM8fl5CpzbaZ9owZpfVFAdQUueOhAs X-Received: by 2002:a05:6402:4498:b0:458:8e63:d667 with SMTP id er24-20020a056402449800b004588e63d667mr9173118edb.354.1668911250323; Sat, 19 Nov 2022 18:27:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668911250; cv=none; d=google.com; s=arc-20160816; b=Q/qWeWQmTClpZXF7SA2XqX2mdgNNvIvqtold1AN97FfDWpWeyIygbSJAfdHSf3Krnq GyS00Ce0fYt3bOz9j/slHNCvpdj+onavCYq197Ph6e0hoILGYfBhWU1Hzc4DcpWIm3gp sZtOAheuNnREEMzkv3Yl4NM0VmIGvsH12qIR/5Yyffx4um9e5OQGsbUxKnSKp5F5ua5M 2Mx3PyfeTung/Gv/UJYlpWWBkYNWG8UYlsxlQxAusAkbUBt6OdKwXEMrYq88b5GUvKWG XFauTQhBGZF4CkdEj5XMoR5KGPhAqJoObEpvRPfEEBz7QAItzT/mQoQ0PMdPpZ/TuxX3 4YBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=LnBakVdf7u+nVk+8LXBI5i4K1BrAHwBdB3BA5VIFQ20=; b=kTGOLOk/FDg/OTG9DdyLx+oDa81kbG47d6y2ztf0I+/FkP/llrs5HM3T3jCY+SeIeT VlUoMXF8pFq03kvHDUmH+OndyMwWHdq3uD4Notqbs3JKTNAVe5W+KNfuXDHD8GeP5Y/b xE5CA82g16MUL+stmUCLh0Ne5H1/yUIyITydguCAEEbwqUmFdRSacLU8nG9fVIE192hl PD8s1G+Uing2eZwTiwlBJff9GgVVqSApqQg9yTQNc7hDJpw/XP7L9l8Q2uaU867VysjL VmaHV9va9we7/jb4/GpL9dnonJ/NloxzGTFEOl88YuSMjwRZRXbHJ+SD6eo6wcdgtoDz IZeg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=xwO3YbrD; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id n22-20020a05640205d600b0045d22bc81a0si6336765edx.231.2022.11.19.18.27.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Nov 2022 18:27:30 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=xwO3YbrD; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8E9F9389EC4D for ; Sun, 20 Nov 2022 02:27:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8E9F9389EC4D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668911226; bh=LnBakVdf7u+nVk+8LXBI5i4K1BrAHwBdB3BA5VIFQ20=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=xwO3YbrDHTKQBJzm5G6FPNkD3C2zIlxp1LoFgthVllBWsl52hunIeyoZjPAyMpM4m VF1PXCPm0q3S4KAtD9uGMxBWeeSKpEFrTUQqBvZgmQI5AUgOa4l72AoX/1z2Cbo1fO FmYAnqM6Qusz4Z/9Zzkw9QO8GMjtCFYjGmaEtTiY= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 861BB3898395; Sun, 20 Nov 2022 02:24:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 861BB3898395 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 76E0D30008A; Sun, 20 Nov 2022 02:24:03 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v3 1/3] RISC-V: Make "priv-spec" overridable Date: Sun, 20 Nov 2022 02:23:27 +0000 Message-Id: <94304c8d9174ae7e9cf52abc3af6ccf5e3e0ecd9.1668910970.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749980282823900039?= X-GMAIL-MSGID: =?utf-8?q?1749980282823900039?= From: Tsukasa OI This commit makes existing disassembler option "priv-spec" overridable on ELF files with attributes. Existing implementation is helpful on debugging binary files but on ELF files, the value specified by "priv-spec" option must match the attributes. However, there's a case where privileged specification ELF attributes and actual CSRs as used in the program differs. For instance, OpenSBI is the prime example. This commit enables objdump and GDB to ignore ELF attributes but instead use custom specification (e.g. even if OpenSBI is compiled with priv-spec 1.11 toolchain, we can correctly disassemble with priv-spec=1.12 option). gas/ChangeLog: * testsuite/gas/riscv/dis-priv-spec-override.s: New privileged specification override tests. * testsuite/gas/riscv/dis-priv-spec-override-1.d: Likewise. * testsuite/gas/riscv/dis-priv-spec-override-2.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (default_priv_spec) Set to initial default version. (priv_spec, is_custom_priv_spec) New. (is_init_csr): Define as a file-scope variable instead a local variable of print_insn_args. (init_riscv_dis_state_for_arch_and_options): Keep track of "priv-spec" changes. (set_default_riscv_dis_options): Initialize "priv-spec". (parse_riscv_dis_option): Make "priv-spec" overridable. (print_insn_args): Use file-scope is_init_csr variable. (riscv_get_disassembler): Move fallback of default_priv_spec from print_insn_args. Initialize "priv-spec". --- .../gas/riscv/dis-priv-spec-override-1.d | 10 +++ .../gas/riscv/dis-priv-spec-override-2.d | 10 +++ .../gas/riscv/dis-priv-spec-override.s | 2 + opcodes/riscv-dis.c | 70 ++++++++++++------- 4 files changed, 68 insertions(+), 24 deletions(-) create mode 100644 gas/testsuite/gas/riscv/dis-priv-spec-override-1.d create mode 100644 gas/testsuite/gas/riscv/dis-priv-spec-override-2.d create mode 100644 gas/testsuite/gas/riscv/dis-priv-spec-override.s diff --git a/gas/testsuite/gas/riscv/dis-priv-spec-override-1.d b/gas/testsuite/gas/riscv/dis-priv-spec-override-1.d new file mode 100644 index 000000000000..2cceebbf35a4 --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-priv-spec-override-1.d @@ -0,0 +1,10 @@ +#as: -march=rv64i_zicsr -mpriv-spec=1.11 +#source: dis-priv-spec-override.s +#objdump: -d -M priv-spec=1.12 + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+3d002573[ ]+csrr[ ]+a0,pmpaddr32 diff --git a/gas/testsuite/gas/riscv/dis-priv-spec-override-2.d b/gas/testsuite/gas/riscv/dis-priv-spec-override-2.d new file mode 100644 index 000000000000..200955e0ffe5 --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-priv-spec-override-2.d @@ -0,0 +1,10 @@ +#as: -march=rv64i_zicsr -mpriv-spec=1.12 +#source: dis-priv-spec-override.s +#objdump: -d -M priv-spec=1.11 + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+3d002573[ ]+csrr[ ]+a0,0x3d0 diff --git a/gas/testsuite/gas/riscv/dis-priv-spec-override.s b/gas/testsuite/gas/riscv/dis-priv-spec-override.s new file mode 100644 index 000000000000..c3d1726e0b5a --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-priv-spec-override.s @@ -0,0 +1,2 @@ +target: + csrr a0, 0x3d0 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 328a34501549..e7dded63c402 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -49,7 +49,16 @@ static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; /* Default privileged specification (as specified by the ELF attributes or the `priv-spec' option). */ -static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; +static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1; + +/* Current privileged specification version. */ +static enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_DRAFT - 1; + +/* If set, a custom privileged specification is specified. */ +static bool is_custom_priv_spec = false; + +/* Reset when reinitializing the CSR hash table is required. */ +static bool is_init_csr = false; /* RISC-V disassembler architecture context type. */ typedef struct @@ -205,6 +214,18 @@ init_riscv_dis_state_for_arch (void) static void init_riscv_dis_state_for_arch_and_options (void) { + static bool init = false; + static enum riscv_spec_class prev_priv_spec; + /* Set current privileged specification. */ + if (!is_custom_priv_spec) + priv_spec = default_priv_spec; + /* First call to this function. */ + if (!init) + { + init = true; + /* Save initial options. */ + prev_priv_spec = priv_spec; + } /* If the architecture string is changed, update XLEN. */ if (is_arch_changed) update_riscv_dis_xlen (NULL); @@ -215,7 +236,12 @@ init_riscv_dis_state_for_arch_and_options (void) = !riscv_subset_supports (&riscv_rps_dis, "zfinx") ? (is_numeric ? riscv_fpr_names_numeric : riscv_fpr_names_abi) : riscv_gpr_names; + /* Reset CSR hash table if either the architecture or the privileged + specification version is changed. */ + if (prev_priv_spec != priv_spec) + is_init_csr = false; /* Save previous options and mark them "unchanged". */ + prev_priv_spec = priv_spec; is_arch_changed = false; } @@ -267,6 +293,7 @@ set_default_riscv_dis_options (void) { no_aliases = false; is_numeric = false; + is_custom_priv_spec = false; } /* Parse RISC-V disassembler option (without arguments). */ @@ -314,21 +341,18 @@ parse_riscv_dis_option (const char *option) value = equal + 1; if (strcmp (option, "priv-spec") == 0) { - enum riscv_spec_class priv_spec = PRIV_SPEC_CLASS_NONE; - const char *name = NULL; - - RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec); - if (priv_spec == PRIV_SPEC_CLASS_NONE) - opcodes_error_handler (_("unknown privileged spec set by %s=%s"), - option, value); - else if (default_priv_spec == PRIV_SPEC_CLASS_NONE) - default_priv_spec = priv_spec; - else if (default_priv_spec != priv_spec) + enum riscv_spec_class priv_spec_new = PRIV_SPEC_CLASS_NONE; + RISCV_GET_PRIV_SPEC_CLASS (value, priv_spec_new); + if (priv_spec_new == PRIV_SPEC_CLASS_NONE) { - RISCV_GET_PRIV_SPEC_NAME (name, default_priv_spec); - opcodes_error_handler (_("mis-matched privilege spec set by %s=%s, " - "the elf privilege attribute is %s"), - option, value, name); + opcodes_error_handler (_ ("unknown privileged spec set by %s=%s." + "not overriding"), + option, value); + } + else + { + is_custom_priv_spec = true; + priv_spec = priv_spec_new; } } else @@ -721,31 +745,26 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'E': { static const char *riscv_csr_hash[4096]; /* Total 2^12 CSRs. */ - static bool init_csr = false; unsigned int csr = EXTRACT_OPERAND (CSR, l); - if (!init_csr) + if (!is_init_csr) { unsigned int i; for (i = 0; i < 4096; i++) riscv_csr_hash[i] = NULL; - /* Set to the newest privileged version. */ - if (default_priv_spec == PRIV_SPEC_CLASS_NONE) - default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1; - #define DECLARE_CSR(name, num, class, define_version, abort_version) \ if (riscv_csr_hash[num] == NULL \ && ((define_version == PRIV_SPEC_CLASS_NONE \ && abort_version == PRIV_SPEC_CLASS_NONE) \ - || (default_priv_spec >= define_version \ - && default_priv_spec < abort_version))) \ + || (priv_spec >= define_version \ + && priv_spec < abort_version))) \ riscv_csr_hash[num] = #name; #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \ DECLARE_CSR (name, num, class, define_version, abort_version) #include "opcode/riscv-opc.h" #undef DECLARE_CSR - init_csr = true; + is_init_csr = true; } if (riscv_csr_hash[csr] != NULL) @@ -1283,6 +1302,9 @@ riscv_get_disassembler (bfd *abfd) in the attributes, use the default value. */ if (!default_arch) default_arch = initial_default_arch; + /* By default, set to the newest privileged version. */ + if (default_priv_spec == PRIV_SPEC_CLASS_NONE) + default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1; } } From patchwork Sun Nov 20 02:23:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 23371 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp945531wrr; Sat, 19 Nov 2022 18:25:40 -0800 (PST) X-Google-Smtp-Source: AA0mqf5x0KEiNFiFcPOksh0A95tYlDpDSSQm2DYWFMG43xqzvieZLFfAhaUfLXu0Fc6fkYi8KIJK X-Received: by 2002:a17:906:a18c:b0:7ad:9629:fb96 with SMTP id s12-20020a170906a18c00b007ad9629fb96mr10873373ejy.751.1668911140341; Sat, 19 Nov 2022 18:25:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668911140; cv=none; d=google.com; s=arc-20160816; b=dZ/kVKdbM8IeRWFuKHNKjGdmDH1WtL3RHLufEdnE88DFveQciaOLr3Ac1FdnJsrDVi cMBBN2Z9Br9cZsBtGAg0CPY9cTB3PBSIEil6bQRZcMpUqEdMxKszbh4MgMoUHCHMimAQ dhRZJHGu6FZPzEYIKM4ky0dAJnr2aOjn9PW8U6kXzQ1LyUTNx7okoCuqCffHrtCgw7Tp iCf8a6hDZ/MvRCmieoexIjgffSTZBE+wxOQxllx1i+VH2Gkg2XQPmNzJjet50m/PAzjd tu1QwugpLDia1XI2Q7D/7EgYlJfKaDvXqJph1jYNTfB8ESVY61EgISetE596Qtjfd0lN B5Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=i/OcYqt9FaY8kwx6z12Y1Ri6Um4hxoYATCnQMmTy8KE=; b=kMR5ow0rLHxyj4yDdsipzIRiJODjVhrkt+b6FX9rustYUVV/nAObsMEDHWZbVpJE5n W2LhSAzeonjWSE0JqKOZfOKOofp/Xsr0APW9ry4ZufGnDMC4oAm++GNRDyN7yGOskWLY jCZ/8iDUMhelp37GgTgNZfB61JfEGNRWjAuuJYN5RPFjrrbV9WVUytHZxAZGqwjSkfPA rs4XuEihbbpBhnjjuxpQv8Xypy6dq2odSzcI8RG8ZQ+NBTjtEY/kn9UPRRDXISiNupvw 7gnwTNFOGNKcEIq7H1EmLRb+il0omCumq/Q6rs4QxPSMRBxkiIyDVSAppxLgjm8HvfQ8 o6Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=KBGSWczz; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id sg42-20020a170907a42a00b007ade82b9e73si7119883ejc.757.2022.11.19.18.25.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Nov 2022 18:25:40 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=KBGSWczz; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C7C3938983B7 for ; Sun, 20 Nov 2022 02:25:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C7C3938983B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668911135; bh=i/OcYqt9FaY8kwx6z12Y1Ri6Um4hxoYATCnQMmTy8KE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=KBGSWczzxKVhg3McucjoJual48zYg8/c4UnARK1rlpL/NxrIH6MyHbmRONvD2tjxb fpIWK75W4/Clh1G2V37jk/4rPLkaCeQdPSr25rIYVyqT9jbnHprVKVe5An/d9YK6PI 24XQcblnEa/yjD1QnA1wgOZB0pMvMQAZwQTRaypA= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id A4119389850F; Sun, 20 Nov 2022 02:24:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A4119389850F Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id F2F56300089; Sun, 20 Nov 2022 02:24:13 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v3 2/3] RISC-V: Add "arch" disassembler option Date: Sun, 20 Nov 2022 02:23:28 +0000 Message-Id: <9d6008e38402c4e60ada6f3d3db14b92815177d8.1668910970.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749980167812374108?= X-GMAIL-MSGID: =?utf-8?q?1749980167812374108?= From: Tsukasa OI This commit adds new disassembler option "arch" to override architecture string. Existing implementations is helpful on regular ELF files but for instance, when debugging a binary with OpenOCD + GDB, there's a case where such information is not available. Also, there's a case where changing the architecture to disassemble is helpful, even on ELF files. For instance, OpenSBI is the prime example. This commit enables objdump and GDB to use custom architecture string instead of ELF attributes and mapping symbols (e.g. even if OpenSBI is compiled with -march=rv64gc, we can enable H extension when disassembling OpenSBI by specifying an architecture string: rv64gch). It can be also helpful to test overwrapping encodings (e.g. standard hints). gas/ChangeLog: * testsuite/gas/riscv/dis-arch-override.s: New arch override tests. * testsuite/gas/riscv/dis-arch-override-1.d: Likewise. * testsuite/gas/riscv/dis-arch-override-2.d: Likewise. * testsuite/gas/riscv/dis-arch-override-3.d: Likewise. opcodes/ChangeLog: * riscv-dis.c (is_custom_arch) New. (update_riscv_dis_xlen): Update XLEN precedence rules. (set_default_riscv_dis_options): Initialize "arch". (parse_riscv_dis_option): Add the "arch" option. (riscv_get_map_state): Ignore ISA string from mapping symbols if custom "arch" is specified. (riscv_get_disassembler): Update the architecture depending on the custom "arch" option. (riscv_option_arg_t) Add RISCV_OPTION_ARG_ARCH. (riscv_options): Add the "arch" option. (disassembler_options_riscv): Add the "arch" option. --- gas/testsuite/gas/riscv/dis-arch-override-1.d | 13 ++++++ gas/testsuite/gas/riscv/dis-arch-override-2.d | 13 ++++++ gas/testsuite/gas/riscv/dis-arch-override-3.d | 13 ++++++ gas/testsuite/gas/riscv/dis-arch-override.s | 45 +++++++++++++++++++ opcodes/riscv-dis.c | 30 +++++++++++-- 5 files changed, 111 insertions(+), 3 deletions(-) create mode 100644 gas/testsuite/gas/riscv/dis-arch-override-1.d create mode 100644 gas/testsuite/gas/riscv/dis-arch-override-2.d create mode 100644 gas/testsuite/gas/riscv/dis-arch-override-3.d create mode 100644 gas/testsuite/gas/riscv/dis-arch-override.s diff --git a/gas/testsuite/gas/riscv/dis-arch-override-1.d b/gas/testsuite/gas/riscv/dis-arch-override-1.d new file mode 100644 index 000000000000..1df81236e2aa --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-arch-override-1.d @@ -0,0 +1,13 @@ +#as: -march=rv64imfd_zbb +#source: dis-arch-override.s +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+00c5f053[ ]+fadd\.s[ ]+ft0,fa1,fa2 +[ ]+[0-9a-f]+:[ ]+02c5f053[ ]+fadd\.d[ ]+ft0,fa1,fa2 +[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext\.h[ ]+a0,a1 diff --git a/gas/testsuite/gas/riscv/dis-arch-override-2.d b/gas/testsuite/gas/riscv/dis-arch-override-2.d new file mode 100644 index 000000000000..a556f293fb52 --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-arch-override-2.d @@ -0,0 +1,13 @@ +#as: -march=rv64imfd_zbb +#source: dis-arch-override.s +#objdump: -d -M arch=rv32im_zfinx_zbkb + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+00c5f053[ ]+fadd\.s[ ]+zero,a1,a2 +[ ]+[0-9a-f]+:[ ]+02c5f053[ ]+\.4byte[ ]+0x2c5f053 +[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+packw[ ]+a0,a1,zero diff --git a/gas/testsuite/gas/riscv/dis-arch-override-3.d b/gas/testsuite/gas/riscv/dis-arch-override-3.d new file mode 100644 index 000000000000..924da72b2797 --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-arch-override-3.d @@ -0,0 +1,13 @@ +#as: -march=rv64imfd_zbb +#source: dis-arch-override.s +#objdump: -d -m riscv -M arch=rv32im_zfinx_zbkb,numeric + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+00c5f053[ ]+fadd\.s[ ]+x0,x11,x12 +[ ]+[0-9a-f]+:[ ]+02c5f053[ ]+\.4byte[ ]+0x2c5f053 +[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+x10,misa +[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+\.4byte[ ]+0x805c53b diff --git a/gas/testsuite/gas/riscv/dis-arch-override.s b/gas/testsuite/gas/riscv/dis-arch-override.s new file mode 100644 index 000000000000..0c2fec44ed3a --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-arch-override.s @@ -0,0 +1,45 @@ +# Assembler configuration: +# -march=rv64imfd_zbb +# Disassembler configurations: +# Test 1: -d +# Test 2: -d -M arch=rv32im_zfinx_zbkb +# Test 3: -d -m riscv -M arch=rv32im_zfinx_zbkb,numeric + +target: + # Assembler : fadd.s (F) + # Disassembler (test 2/3) : fadd.s (Zfinx) + # Test that all three operands point to GPRs. + fadd.s ft0, fa1, fa2 + + # Assembler : fadd.d (D) + # Disassembler (test 2/3) : (invalid) + # On disassembler option on test 2, Zdinx is not present. So, + # it should be disassembled as an invalid instruction. + fadd.d ft0, fa1, fa2 + + # Assembler : csrr (Zicsr) + # Disassembler (test 2/3) : csrr (Zicsr) + # When assembling, Zicsr is implied by F. When disassembling, + # Zicsr is implied by Zfinx. On both cases, csrr should be + # disassembled as csrr. + csrr a0, misa + + # Assembler : zext.h (Zbb) + # Disassembler (test 2) : packw (Zbkb) + # Disassembler (test 3) : (invalid) + # Since zext.h specialized instruction does not exist in Zbkb + # and we disassemble the output with Zbkb, this instruction + # should be disassembled as a packw instruction (on RV64). + # + # We specify arch=rv32im_zfinx_zbkb on disassembling on test + # 2 and 3. But, XLEN part of the ISA string is effective + # only if XLEN-neutral machine is specified by `-m riscv' option + # (because we are disassembling 64-bit RISC-V ELF file, BFD + # architecture is set to `riscv:rv64' unless `-m' option + # is specified). + # + # As a result, test 3 (with `-m riscv' option) disassembles with + # RV32 but test 2 (without it) does with RV64. + # It changes the result of disassembling since packw instruction + # is invalid on RV32. + zext.h a0, a1 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index e7dded63c402..03272d4f64ce 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -35,6 +35,9 @@ /* Default architecture string (if not available). */ static const char *const initial_default_arch = "rv64gc"; +/* If set, a custom architecture string is specified. */ +static bool is_custom_arch = false; + /* Current XLEN for the disassembler. */ static unsigned xlen = 0; @@ -183,8 +186,10 @@ update_riscv_dis_xlen (struct disassemble_info *info) This is only effective if XLEN-specific BFD machine architecture is chosen. If XLEN-neutral (like riscv), BFD machine architecture is ignored on XLEN selection. - 2. Non-default RISC-V architecture string set by either an ELF - attribute or a mapping symbol with ISA string. + 2. Non-default RISC-V architecture string set by either: + a. -M arch=... option (GDB: set disassembler-options arch=...), + b. A mapping symbol with ISA string or + c. An ELF attribute 3. ELF class in dummy ELF header. */ if (xlen_by_mach != 0) xlen = xlen_by_mach; @@ -294,6 +299,7 @@ set_default_riscv_dis_options (void) no_aliases = false; is_numeric = false; is_custom_priv_spec = false; + is_custom_arch = false; } /* Parse RISC-V disassembler option (without arguments). */ @@ -355,6 +361,11 @@ parse_riscv_dis_option (const char *option) priv_spec = priv_spec_new; } } + else if (strcmp (option, "arch") == 0) + { + is_custom_arch = true; + update_riscv_dis_arch (&dis_arch_context_override, value); + } else { /* xgettext:c-format */ @@ -1024,6 +1035,9 @@ riscv_get_map_state (int n, *state = newstate; if (newstate == MAP_INSN && update) { + /* Skip if a custom architecture is specified. */ + if (is_custom_arch) + return true; if (arch) { /* Override the architecture. */ @@ -1308,7 +1322,10 @@ riscv_get_disassembler (bfd *abfd) } } - update_riscv_dis_arch (&dis_arch_context_default, default_arch); + if (is_custom_arch) + set_riscv_dis_arch_context (&dis_arch_context_default, default_arch); + else + update_riscv_dis_arch (&dis_arch_context_default, default_arch); return print_insn_riscv; } @@ -1359,6 +1376,7 @@ riscv_symbol_is_valid (asymbol * sym, typedef enum { RISCV_OPTION_ARG_NONE = -1, + RISCV_OPTION_ARG_ARCH, RISCV_OPTION_ARG_PRIV_SPEC, RISCV_OPTION_ARG_COUNT @@ -1376,6 +1394,9 @@ static struct { "numeric", N_("Print numeric register names, rather than ABI names."), RISCV_OPTION_ARG_NONE }, + { "arch=", + N_("Disassemble using specified ISA and extensions."), + RISCV_OPTION_ARG_ARCH }, { "no-aliases", N_("Disassemble only into canonical instructions."), RISCV_OPTION_ARG_NONE }, @@ -1403,6 +1424,9 @@ disassembler_options_riscv (void) args = XNEWVEC (disasm_option_arg_t, num_args + 1); + args[RISCV_OPTION_ARG_ARCH].name = "ARCH"; + args[RISCV_OPTION_ARG_ARCH].values = NULL; + args[RISCV_OPTION_ARG_PRIV_SPEC].name = "SPEC"; priv_spec_count = PRIV_SPEC_CLASS_DRAFT - PRIV_SPEC_CLASS_NONE - 1; args[RISCV_OPTION_ARG_PRIV_SPEC].values From patchwork Sun Nov 20 02:23:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 23370 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp945431wrr; Sat, 19 Nov 2022 18:25:10 -0800 (PST) X-Google-Smtp-Source: AA0mqf7N5AHIipiiEd00W/n16CKLM9yEasgRp1DK1oif1DnMrvntgoDTYPc6eDcatRS9oqWDPOJc X-Received: by 2002:a17:906:3792:b0:7aa:97c7:2bfe with SMTP id n18-20020a170906379200b007aa97c72bfemr10869264ejc.196.1668911110579; Sat, 19 Nov 2022 18:25:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668911110; cv=none; d=google.com; s=arc-20160816; b=lR+DMhLIrNLlR1qxyUH9x/x3D1IYO09Tu6VOS2NBUhbW1aNBONA0f4nqpWrDWAxTAF G2yabShltT9xX174bvv8U2Og/6i6tO8peHm6G5uMsH/uqPZ9IVpb5i4dtEU9qESzTR7h L7FKa0+XLIMn21s8wDrumVrIOaer2q6yVW5g+8wSEapSsnO/2+pa8d7tDBZ2UPNmYmX1 9a8PPpZEf9viDB4Je9fqdRcVJMAsdzKDsW4GmKVQC6yszpQOJP9pyxPPs68IEddpF1Va P2UW4rm75gJCMFKkFrxHVqu9sXyj03w0TEOfVhw+gbiECzYZJr3Vy4mDeL9BGOUn5hh7 PjOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=JaJBVhZ8mV4vtN4bz/lG4FB8PjFnD3ypvajKIjkEdXQ=; b=xo2HVtNXkgO9nQbkoVsvJDZO/hn2HweRGK+20vfHaG4miKLDioD75PwD78aSzsklM8 zneBD/ANQUXJIFQTHnW8VoAnk2xAKj2zgIbYw++7UCHxW4oCsQw8GXIUO4xjL4ujC+c8 elIq215SarWlTCcX3dJmO4yyugXwsEYgMSwg3cOKP0/kuoOAcTBMdWUhZ3ob5xHyBx9D xIdWlNlTajmPjY+57NPm1hfswMvpf/uVdo5vwqaz8GbM5tZS2CIHob4yZ6IBYBo9yDhy FwfxwfOynPcPUEuv3HSl2Hi4IdDitMbCoeH01t3iPTTMJolFB88dYMBbuTCmNH89nWL+ inXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=HBBvWRE6; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id hc42-20020a17090716aa00b007ae814af68dsi8377489ejc.355.2022.11.19.18.25.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Nov 2022 18:25:10 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=HBBvWRE6; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 97E813899016 for ; Sun, 20 Nov 2022 02:25:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 97E813899016 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668911108; bh=JaJBVhZ8mV4vtN4bz/lG4FB8PjFnD3ypvajKIjkEdXQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=HBBvWRE6+U1t8KbomUBdt1qukYY2VajyyvGZbyBXekYFnIP3Jqnsurs6wtkoZ1uQU fSqtI3/DveEKWM8diAlXm8fafNb73F5JUGGypMgA0kdcFM7OTGrVOjD0uUGKPAJtSW 4BaqiH9etk/GT2vAY36rKfDmus323twwEsRT0ZSc= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 40B30389851D; Sun, 20 Nov 2022 02:24:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 40B30389851D Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 7F3C430008C; Sun, 20 Nov 2022 02:24:24 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v3 3/3] gdb/testsuite: RISC-V disassembler option tests Date: Sun, 20 Nov 2022 02:23:29 +0000 Message-Id: <70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749980136490811395?= X-GMAIL-MSGID: =?utf-8?q?1749980136490811395?= From: Tsukasa OI This commit adds RISC-V disassembler option tests for: - "no-aliases" and "numeric" options - overridable "priv-spec" option - new "arch" option and makes sure that option override correctly works and they can be unset thereafter (with "set disassembler-options" with no options). --- .../gdb.arch/riscv-disassembler-options.exp | 129 ++++++++++++++++++ .../gdb.arch/riscv-disassembler-options.s | 29 ++++ 2 files changed, 158 insertions(+) create mode 100644 gdb/testsuite/gdb.arch/riscv-disassembler-options.exp create mode 100644 gdb/testsuite/gdb.arch/riscv-disassembler-options.s diff --git a/gdb/testsuite/gdb.arch/riscv-disassembler-options.exp b/gdb/testsuite/gdb.arch/riscv-disassembler-options.exp new file mode 100644 index 000000000000..e5548eb426d3 --- /dev/null +++ b/gdb/testsuite/gdb.arch/riscv-disassembler-options.exp @@ -0,0 +1,129 @@ +# Copyright 2022 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# Test RISC-V disassembler options. + +if {![istarget "riscv*-*-*"]} { + verbose "Skipping ${gdb_test_file_name}." + return +} + +standard_testfile .s +set objfile [standard_output_file ${testfile}.o] + +set compile_flags { \ + "additional_flags=-march=rv64i_zicsr -mabi=lp64" \ + "additional_flags=-Xassembler -mpriv-spec=1.11" \ + } + +if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${objfile}" object \ + ${compile_flags}] != "" } { + untested "could not compile test program" + return +} + +clean_restart ${objfile} + +proc riscv_set_disassembler_options { opts } { + gdb_test_no_output "set disassembler-options $opts" + gdb_test "show disassembler-options" \ + "The current disassembler options are '$opts'\r\n.*" \ + "show disassembler-options: $opts" +} + +# We can disable disassembly using alias instructions. +riscv_set_disassembler_options "no-aliases" +gdb_test_sequence "disassemble test_func" "option: no-aliases" { + "Dump of assembler code for function test_func:\r\n" + "\[^:\]+:\taddi\ta0,zero,1\r\n" + "\[^:\]+:\tcsrrs\ta0,0x3d0,zero\r\n" + "\[^:\]+:\t\\.4byte\t0x62000073\r\n" + "\[^:\]+:\tjalr\tzero,0\\(ra\\)\r\n" + "End of assembler dump\." +} + +# We can disassemble using numeric register names. +riscv_set_disassembler_options "numeric" +gdb_test_sequence "disassemble test_func" "option: numeric" { + "Dump of assembler code for function test_func:\r\n" + "\[^:\]+:\tli\tx10,1\r\n" + "\[^:\]+:\tcsrr\tx10,0x3d0\r\n" + "\[^:\]+:\t\\.4byte\t0x62000073\r\n" + "\[^:\]+:\tret\r\n" + "End of assembler dump\." +} + +# We can switch to the privileged specification 1.11. +riscv_set_disassembler_options "priv-spec=1.11" +gdb_test_sequence "disassemble test_func" "privileged specification 1.11 CSRs" { + "Dump of assembler code for function test_func:\r\n" + "\[^:\]+:\tli\ta0,1\r\n" + "\[^:\]+:\tcsrr\ta0,0x3d0\r\n" + "\[^:\]+:\t\\.4byte\t0x62000073\r\n" + "\[^:\]+:\tret\r\n" + "End of assembler dump\." +} + +# We can switch to the privileged specification 1.12. +riscv_set_disassembler_options "priv-spec=1.12" +gdb_test_sequence "disassemble test_func" "privileged specification 1.12 CSRs" { + "Dump of assembler code for function test_func:\r\n" + "\[^:\]+:\tli\ta0,1\r\n" + "\[^:\]+:\tcsrr\ta0,pmpaddr32\r\n" + "\[^:\]+:\t\\.4byte\t0x62000073\r\n" + "\[^:\]+:\tret\r\n" + "End of assembler dump\." +} + +# We can enable the 'H'-extension support. +riscv_set_disassembler_options "arch=rv64gch" +gdb_test_sequence "disassemble test_func" "'H'-extension" { + "Dump of assembler code for function test_func:\r\n" + "\[^:\]+:\tli\ta0,1\r\n" + "\[^:\]+:\tcsrr\ta0,0x3d0\r\n" + "\[^:\]+:\thfence\\.gvma\r\n" + "\[^:\]+:\tret\r\n" + "End of assembler dump\." +} + +# We can set multiple comma-separated options +riscv_set_disassembler_options "arch=rv64gch,priv-spec=1.12,no-aliases,numeric" +gdb_test_sequence "disassemble test_func" "multiple options" { + "Dump of assembler code for function test_func:\r\n" + "\[^:\]+:\taddi\tx10,x0,1\r\n" + "\[^:\]+:\tcsrrs\tx10,pmpaddr32,x0\r\n" + "\[^:\]+:\thfence\\.gvma\tx0,x0\r\n" + "\[^:\]+:\tjalr\tx0,0\\(x1\\)\r\n" + "End of assembler dump\." +} + +# Once we set empty disassembler option, we can restore the default one. +# Defaults: +# - enable aliases +# - ABI register names +# - priv-spec=1.11 +# - arch=rv64i_zicsr +gdb_test_no_output "set disassembler-options" "set NULL disassembler-options" +gdb_test "show disassembler-options" \ + "The current disassembler options are ''\r\n.*" \ + "show NULL disassembler-options" +gdb_test_sequence "disassemble test_func" "restore to default" { + "Dump of assembler code for function test_func:\r\n" + "\[^:\]+:\tli\ta0,1\r\n" + "\[^:\]+:\tcsrr\ta0,0x3d0\r\n" + "\[^:\]+:\t\\.4byte\t0x62000073\r\n" + "\[^:\]+:\tret\r\n" + "End of assembler dump\." +} diff --git a/gdb/testsuite/gdb.arch/riscv-disassembler-options.s b/gdb/testsuite/gdb.arch/riscv-disassembler-options.s new file mode 100644 index 000000000000..fc33b03b0c00 --- /dev/null +++ b/gdb/testsuite/gdb.arch/riscv-disassembler-options.s @@ -0,0 +1,29 @@ +/* Copyright 2022 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + + .attribute arch, "rv64i_zicsr" + .option nopic + .text + + .align 1 + .globl test_func + .type test_func, @function +test_func: + li a0, 1 + csrr a0, 0x3d0 + # hfence.gvma (an alias of hfence.gvma zero,zero) + .insn 0x62000073 + ret + .size test_func, .-test_func