From patchwork Sat Nov 19 23:04:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23339 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp896998wrr; Sat, 19 Nov 2022 15:05:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf7y6PlqrFAB51lQW+NNG5tCiGXOrlrP33YZxL6Nuf7aFDXZOTgao4wiKC814IYkN7ASIJ0x X-Received: by 2002:a63:f503:0:b0:470:4acb:1eb with SMTP id w3-20020a63f503000000b004704acb01ebmr11959782pgh.440.1668899132564; Sat, 19 Nov 2022 15:05:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899132; cv=none; d=google.com; s=arc-20160816; b=nDEAJRWiEeQG/bSbFrlHelA4NsqNmQvTutRWHlBKI408l6f4bLKWOerMdsYmDEtrcV WQ/xzHLzN/K4D43xCk4HdP5r5Srp68nlnuhPzSfe7AFWREFyAXx/Piw6yvfb+aDcJahK 775MYW5Xi/ih+/kpmLXQrhnCIWfSq1xkmkDmRdKVK4j3A1erdDj5+NeB4P8q9FOT45om zLu1pPkIjcyo4MNe9JwUq8sXioKu1Q/Zu5+j/PSeP7zMBEo2hgYn7uCnmfmbtujlDHSv FSnyQ4y+ds1sDHb0AZAY49U8509fD2a0dYKUQ5JAENTzmi+vvvV4RAnk/GbYhbTC/kFG oZ7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :feedback-id:references:in-reply-to:message-id:subject:cc:from:to :dkim-signature:date; bh=2+sOxC40kt2h/1Sz9kRo5GxpGnAXAGHbxk3TUs+fmSg=; b=mj1ehwsrWzL7HU83QJ0VYuFrIzA5Q1Fth5+bwENvc5Yp/nFhd/bUwqnacRAPizOHKf XnU19oyJMZJ6+AR+68NadBqlqHFK4KfASjsDj1oc3isUCc+Pgwvb6SrNTC8zVCGwzDA7 Nc/RFldEG8EUxW6CvmMJu72uiYMdpkxUv/WkhFARWT3Ejof4OO3PBqXE4eNfrKDrUnDy WXUFFdgKwgd1Mwnc1Lt7BArNI3btbUNNk5g4n4WzIvz+3PsMfSt9HRXnNLE/2KkbLkxS T6XPXJeqZ5BGqSGj2gAuTokIf6L8vxdVQZhrkLnAsa3gehljYb1DTq97lhibzgE2tTkN vDPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=jAjIY4B0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m8-20020a056a00080800b0056d89d8fba7si8356031pfk.154.2022.11.19.15.05.20; Sat, 19 Nov 2022 15:05:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=jAjIY4B0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234739AbiKSXEb (ORCPT + 99 others); Sat, 19 Nov 2022 18:04:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234728AbiKSXE3 (ORCPT ); Sat, 19 Nov 2022 18:04:29 -0500 Received: from mail-40134.protonmail.ch (mail-40134.protonmail.ch [185.70.40.134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE78E13D59; Sat, 19 Nov 2022 15:04:27 -0800 (PST) Date: Sat, 19 Nov 2022 23:04:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899066; x=1669158266; bh=2+sOxC40kt2h/1Sz9kRo5GxpGnAXAGHbxk3TUs+fmSg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=jAjIY4B0YN1LB7N8qwiwUWlFcsxMt9pRvkXj5uAappI40qAbxYMLRmBS/xbgf6UFg 8GP/4XFuSAiyX34JLKshx8QtDxyhLcwSg8dsUeAKR5DfHzJODZFz1SS7SFpqQWSE92 kQkHtGjvsLiAqMdChUFKvytUa2fSL2QHtyEw3OxIuXIZ6zn3iVDmoDx/5VThDaHwLy U5vkbtRx4Hbwa65avysoi42FPMolv/YzFlQXS86B4CWA/9FQaxRSg3BNwMEp9QINq6 E/CLZ0Sbuqy/cKsHn9Qrqq78W1vpYmSF+x1q3ltCWUp6CgeZTkZAX7neHMpso+F+82 pVYfmgihEegcw== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/18] block/rnbd: fix mixed module-builtin object Message-ID: <20221119225650.1044591-2-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967576901636845?= X-GMAIL-MSGID: =?utf-8?q?1749967576901636845?= From: Masahiro Yamada With CONFIG_BLK_DEV_RNBD_CLIENT=m and CONFIG_BLK_DEV_RNBD_SERVER=y (or vice versa), rnbd-common.o is linked to a module and also to vmlinux even though CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Turn rnbd_access_mode_str() into an inline function. Signed-off-by: Masahiro Yamada Reviewed-and-tested-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- drivers/block/rnbd/Makefile | 6 ++---- drivers/block/rnbd/rnbd-common.c | 23 ----------------------- drivers/block/rnbd/rnbd-proto.h | 14 +++++++++++++- 3 files changed, 15 insertions(+), 28 deletions(-) delete mode 100644 drivers/block/rnbd/rnbd-common.c -- 2.38.1 diff --git a/drivers/block/rnbd/Makefile b/drivers/block/rnbd/Makefile index 40b31630822c..208e5f865497 100644 --- a/drivers/block/rnbd/Makefile +++ b/drivers/block/rnbd/Makefile @@ -3,13 +3,11 @@ ccflags-y := -I$(srctree)/drivers/infiniband/ulp/rtrs rnbd-client-y := rnbd-clt.o \ - rnbd-clt-sysfs.o \ - rnbd-common.o + rnbd-clt-sysfs.o CFLAGS_rnbd-srv-trace.o = -I$(src) -rnbd-server-y := rnbd-common.o \ - rnbd-srv.o \ +rnbd-server-y := rnbd-srv.o \ rnbd-srv-sysfs.o \ rnbd-srv-trace.o diff --git a/drivers/block/rnbd/rnbd-common.c b/drivers/block/rnbd/rnbd-common.c deleted file mode 100644 index 596c3f732403..000000000000 --- a/drivers/block/rnbd/rnbd-common.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * RDMA Network Block Driver - * - * Copyright (c) 2014 - 2018 ProfitBricks GmbH. All rights reserved. - * Copyright (c) 2018 - 2019 1&1 IONOS Cloud GmbH. All rights reserved. - * Copyright (c) 2019 - 2020 1&1 IONOS SE. All rights reserved. - */ -#include "rnbd-proto.h" - -const char *rnbd_access_mode_str(enum rnbd_access_mode mode) -{ - switch (mode) { - case RNBD_ACCESS_RO: - return "ro"; - case RNBD_ACCESS_RW: - return "rw"; - case RNBD_ACCESS_MIGRATION: - return "migration"; - default: - return "unknown"; - } -} diff --git a/drivers/block/rnbd/rnbd-proto.h b/drivers/block/rnbd/rnbd-proto.h index ea7ac8bca63c..1849e7039fa1 100644 --- a/drivers/block/rnbd/rnbd-proto.h +++ b/drivers/block/rnbd/rnbd-proto.h @@ -300,6 +300,18 @@ static inline u32 rq_to_rnbd_flags(struct request *rq) return rnbd_opf; } -const char *rnbd_access_mode_str(enum rnbd_access_mode mode); +static inline const char *rnbd_access_mode_str(enum rnbd_access_mode mode) +{ + switch (mode) { + case RNBD_ACCESS_RO: + return "ro"; + case RNBD_ACCESS_RW: + return "rw"; + case RNBD_ACCESS_MIGRATION: + return "migration"; + default: + return "unknown"; + } +} #endif /* RNBD_PROTO_H */ From patchwork Sat Nov 19 23:04:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23340 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp897177wrr; Sat, 19 Nov 2022 15:06:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf7SC39PkL01D4IGc5HGfD24jjiNzvntWWd6RxmfDokIYw6s1/kb7Vtlq27XES5PBgGZw7zl X-Received: by 2002:a17:903:1342:b0:188:63db:f23a with SMTP id jl2-20020a170903134200b0018863dbf23amr5717604plb.21.1668899162491; Sat, 19 Nov 2022 15:06:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899162; cv=none; d=google.com; s=arc-20160816; b=fDayLejqnEKBiBSs7JIIYsoguP2xBC8FqizpSw5oL5VPz+RXvxm1/6fBU4JMQ8p0li DpZlGAgqWI3yMilpCoE1XsEe6IUUmRdrP/OUV9HPEF2NkzV1wr8P80W70SJKFOzbar3N zxquH7JzMiewFFQaoJY6NICthQIGdubYqkb+kZMm2ZjcIwMFMSKLbRutmo7hXSD0NUDY NcqtnhoQHSIe+izRt5Q4hnIgQZv3qWifcN/sJDVuveY8DcZe+7PT6PpmuwUbpGqCzWXp 9HZ3rI/ghZ9tKaMYpZBof/YKkulxXQKJphBYawIJcVStJEpodc0Qrf5KK2RLdVwt9Dbs twjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :feedback-id:references:in-reply-to:message-id:subject:cc:from:to :dkim-signature:date; bh=ievoQBFWTfCyBGr8jW3lYbJQQvItYo3e13YnLNOYLHM=; b=p128sg28KAmgNIR/PaJ5sdx1xESLgQHxpZcU+xpfVAwaIKuvhCP01vx6GQGiX+IT4J CmqpQ8/sQ2ZyKc4yOVEVjLzZu12wvayu/+C534X+TN+8aK6Mk65wEKgm1lMMpqZcHwL5 s+Xn0OvysumXdmEwO6HXRIC/ENuFwUZQlrUIycpAHZzGNdBgEaBVopRxXe8RtitQyPnq a0aI0ClTiy+fXK5WxKkMKrNuE5ICwQ4Ms8hw22TpEF5CnBefyuDQcWN/3hoL5DH9ICc8 ktYKwWekge+i02t/oMIhJobxuLNdaMKACoJo62l8sKg7OSTZDcTstcj3IhbRnErGl3uC 9u8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=e9J7IW5S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q4-20020a632a04000000b0043ce223c86dsi7817677pgq.843.2022.11.19.15.05.49; Sat, 19 Nov 2022 15:06:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=e9J7IW5S; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234742AbiKSXFA (ORCPT + 99 others); Sat, 19 Nov 2022 18:05:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234334AbiKSXE6 (ORCPT ); Sat, 19 Nov 2022 18:04:58 -0500 Received: from mail-0301.mail-europe.com (mail-0301.mail-europe.com [188.165.51.139]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2456C13DC1; Sat, 19 Nov 2022 15:04:56 -0800 (PST) Date: Sat, 19 Nov 2022 23:04:41 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899092; x=1669158292; bh=ievoQBFWTfCyBGr8jW3lYbJQQvItYo3e13YnLNOYLHM=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=e9J7IW5S3DnhO59r0K0Emw2L2P685+iyrKvjbkKrMS/2hVMWSVut0lLR85o6K7/1Q MLZ6eDVmohh8v7RCfD4GwHTAyOUZQlc2QphVOWui+pU6MQW7Aq8iCyonR5/7z9JJR/ iKA893NOj09UdoDSwEDZxFU4VaztPwqV0mgdaqzkG1akQk7iOXHnNsT2my4xKQbB/x 9GPdJuBViZhix+PR4NpUZpXsOLBcezq6c2Z2jxPABku56M3fwka3yj/2vudGLTFlZY abmrXk16Qhrz50WVYjw3r453UIqHPJ/pkWBxE+3W46ENx62GqSWCo139KesL+NDB9E CrJ0cOSx2zjlw== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/18] drm/bridge: imx: fix mixed module-builtin object Message-ID: <20221119225650.1044591-3-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967608233523637?= X-GMAIL-MSGID: =?utf-8?q?1749967608233523637?= From: Masahiro Yamada With CONFIG_DRM_IMX8QM_LDB=m and CONFIG_DRM_IMX8QXP_LDB=y (or vice versa), imx-ldb-helper.o is linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Turn helpers in imx-ldb-helper.c into inline functions. Signed-off-by: Masahiro Yamada Reviewed-and-tested-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- drivers/gpu/drm/bridge/imx/Makefile | 4 +- drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 221 -------------------- drivers/gpu/drm/bridge/imx/imx-ldb-helper.h | 213 +++++++++++++++++-- 3 files changed, 197 insertions(+), 241 deletions(-) delete mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c -- 2.38.1 diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index aa90ec8d5433..64b93009376a 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,7 +1,7 @@ -imx8qm-ldb-objs := imx-ldb-helper.o imx8qm-ldb-drv.o +imx8qm-ldb-objs := imx8qm-ldb-drv.o obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o -imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o +imx8qxp-ldb-objs := imx8qxp-ldb-drv.o obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c deleted file mode 100644 index 7338b84bc83d..000000000000 --- a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.c +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Sascha Hauer, Pengutronix - * Copyright 2019,2020,2022 NXP - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include "imx-ldb-helper.h" - -bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch) -{ - return ldb_ch->link_type == LDB_CH_SINGLE_LINK; -} - -bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch) -{ - return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS || - ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; -} - -int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - - ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format; - ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format; - - return 0; -} - -void ldb_bridge_mode_set_helper(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - bool is_split = ldb_channel_is_split_link(ldb_ch); - - if (is_split) - ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; - - switch (ldb_ch->out_bus_format) { - case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: - break; - case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: - if (ldb_ch->chno == 0 || is_split) - ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; - if (ldb_ch->chno == 1 || is_split) - ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; - break; - case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: - if (ldb_ch->chno == 0 || is_split) - ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | - LDB_BIT_MAP_CH0_JEIDA; - if (ldb_ch->chno == 1 || is_split) - ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | - LDB_BIT_MAP_CH1_JEIDA; - break; - } -} - -void ldb_bridge_enable_helper(struct drm_bridge *bridge) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - - /* - * Platform specific bridge drivers should set ldb_ctrl properly - * for the enablement, so just write the ctrl_reg here. - */ - regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); -} - -void ldb_bridge_disable_helper(struct drm_bridge *bridge) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - bool is_split = ldb_channel_is_split_link(ldb_ch); - - if (ldb_ch->chno == 0 || is_split) - ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; - if (ldb_ch->chno == 1 || is_split) - ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; - - regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); -} - -int ldb_bridge_attach_helper(struct drm_bridge *bridge, - enum drm_bridge_attach_flags flags) -{ - struct ldb_channel *ldb_ch = bridge->driver_private; - struct ldb *ldb = ldb_ch->ldb; - - if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { - DRM_DEV_ERROR(ldb->dev, - "do not support creating a drm_connector\n"); - return -EINVAL; - } - - if (!bridge->encoder) { - DRM_DEV_ERROR(ldb->dev, "missing encoder\n"); - return -ENODEV; - } - - return drm_bridge_attach(bridge->encoder, - ldb_ch->next_bridge, bridge, - DRM_BRIDGE_ATTACH_NO_CONNECTOR); -} - -int ldb_init_helper(struct ldb *ldb) -{ - struct device *dev = ldb->dev; - struct device_node *np = dev->of_node; - struct device_node *child; - int ret; - u32 i; - - ldb->regmap = syscon_node_to_regmap(np->parent); - if (IS_ERR(ldb->regmap)) { - ret = PTR_ERR(ldb->regmap); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret); - return ret; - } - - for_each_available_child_of_node(np, child) { - struct ldb_channel *ldb_ch; - - ret = of_property_read_u32(child, "reg", &i); - if (ret || i > MAX_LDB_CHAN_NUM - 1) { - ret = -EINVAL; - DRM_DEV_ERROR(dev, - "invalid channel node address: %u\n", i); - of_node_put(child); - return ret; - } - - ldb_ch = ldb->channel[i]; - ldb_ch->ldb = ldb; - ldb_ch->chno = i; - ldb_ch->is_available = true; - ldb_ch->np = child; - - ldb->available_ch_cnt++; - } - - return 0; -} - -int ldb_find_next_bridge_helper(struct ldb *ldb) -{ - struct device *dev = ldb->dev; - struct ldb_channel *ldb_ch; - int ret, i; - - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { - ldb_ch = ldb->channel[i]; - - if (!ldb_ch->is_available) - continue; - - ldb_ch->next_bridge = devm_drm_of_get_bridge(dev, ldb_ch->np, - 1, 0); - if (IS_ERR(ldb_ch->next_bridge)) { - ret = PTR_ERR(ldb_ch->next_bridge); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, - "failed to get next bridge: %d\n", - ret); - return ret; - } - } - - return 0; -} - -void ldb_add_bridge_helper(struct ldb *ldb, - const struct drm_bridge_funcs *bridge_funcs) -{ - struct ldb_channel *ldb_ch; - int i; - - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { - ldb_ch = ldb->channel[i]; - - if (!ldb_ch->is_available) - continue; - - ldb_ch->bridge.driver_private = ldb_ch; - ldb_ch->bridge.funcs = bridge_funcs; - ldb_ch->bridge.of_node = ldb_ch->np; - - drm_bridge_add(&ldb_ch->bridge); - } -} - -void ldb_remove_bridge_helper(struct ldb *ldb) -{ - struct ldb_channel *ldb_ch; - int i; - - for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { - ldb_ch = ldb->channel[i]; - - if (!ldb_ch->is_available) - continue; - - drm_bridge_remove(&ldb_ch->bridge); - } -} diff --git a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h index a0a5cde27fbc..42e9b4aa8399 100644 --- a/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h +++ b/drivers/gpu/drm/bridge/imx/imx-ldb-helper.h @@ -65,32 +65,209 @@ struct ldb { #define bridge_to_ldb_ch(b) container_of(b, struct ldb_channel, bridge) -bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch); -bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch); +static inline bool ldb_channel_is_single_link(struct ldb_channel *ldb_ch) +{ + return ldb_ch->link_type == LDB_CH_SINGLE_LINK; +} -int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state); +static inline bool ldb_channel_is_split_link(struct ldb_channel *ldb_ch) +{ + return ldb_ch->link_type == LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS || + ldb_ch->link_type == LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; +} -void ldb_bridge_mode_set_helper(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode); +static inline int ldb_bridge_atomic_check_helper(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; -void ldb_bridge_enable_helper(struct drm_bridge *bridge); + ldb_ch->in_bus_format = bridge_state->input_bus_cfg.format; + ldb_ch->out_bus_format = bridge_state->output_bus_cfg.format; -void ldb_bridge_disable_helper(struct drm_bridge *bridge); + return 0; +} -int ldb_bridge_attach_helper(struct drm_bridge *bridge, - enum drm_bridge_attach_flags flags); +static inline void ldb_bridge_mode_set_helper(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + bool is_split = ldb_channel_is_split_link(ldb_ch); -int ldb_init_helper(struct ldb *ldb); + if (is_split) + ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; -int ldb_find_next_bridge_helper(struct ldb *ldb); + switch (ldb_ch->out_bus_format) { + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | + LDB_BIT_MAP_CH0_JEIDA; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | + LDB_BIT_MAP_CH1_JEIDA; + break; + } +} -void ldb_add_bridge_helper(struct ldb *ldb, - const struct drm_bridge_funcs *bridge_funcs); +static inline void ldb_bridge_enable_helper(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; -void ldb_remove_bridge_helper(struct ldb *ldb); + /* + * Platform specific bridge drivers should set ldb_ctrl properly + * for the enablement, so just write the ctrl_reg here. + */ + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} + +static inline void ldb_bridge_disable_helper(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + bool is_split = ldb_channel_is_split_link(ldb_ch); + + if (ldb_ch->chno == 0 || is_split) + ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; + if (ldb_ch->chno == 1 || is_split) + ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; + + regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); +} + +static inline int ldb_bridge_attach_helper(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct ldb *ldb = ldb_ch->ldb; + + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { + DRM_DEV_ERROR(ldb->dev, + "do not support creating a drm_connector\n"); + return -EINVAL; + } + + if (!bridge->encoder) { + DRM_DEV_ERROR(ldb->dev, "missing encoder\n"); + return -ENODEV; + } + + return drm_bridge_attach(bridge->encoder, + ldb_ch->next_bridge, bridge, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); +} + +static inline int ldb_init_helper(struct ldb *ldb) +{ + struct device *dev = ldb->dev; + struct device_node *np = dev->of_node; + struct device_node *child; + int ret; + u32 i; + + ldb->regmap = syscon_node_to_regmap(np->parent); + if (IS_ERR(ldb->regmap)) { + ret = PTR_ERR(ldb->regmap); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + for_each_available_child_of_node(np, child) { + struct ldb_channel *ldb_ch; + + ret = of_property_read_u32(child, "reg", &i); + if (ret || i > MAX_LDB_CHAN_NUM - 1) { + ret = -EINVAL; + DRM_DEV_ERROR(dev, + "invalid channel node address: %u\n", i); + of_node_put(child); + return ret; + } + + ldb_ch = ldb->channel[i]; + ldb_ch->ldb = ldb; + ldb_ch->chno = i; + ldb_ch->is_available = true; + ldb_ch->np = child; + + ldb->available_ch_cnt++; + } + + return 0; +} + +static inline int ldb_find_next_bridge_helper(struct ldb *ldb) +{ + struct device *dev = ldb->dev; + struct ldb_channel *ldb_ch; + int ret, i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + ldb_ch->next_bridge = devm_drm_of_get_bridge(dev, ldb_ch->np, + 1, 0); + if (IS_ERR(ldb_ch->next_bridge)) { + ret = PTR_ERR(ldb_ch->next_bridge); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(dev, + "failed to get next bridge: %d\n", + ret); + return ret; + } + } + + return 0; +} + +static inline void ldb_add_bridge_helper(struct ldb *ldb, + const struct drm_bridge_funcs *bridge_funcs) +{ + struct ldb_channel *ldb_ch; + int i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + ldb_ch->bridge.driver_private = ldb_ch; + ldb_ch->bridge.funcs = bridge_funcs; + ldb_ch->bridge.of_node = ldb_ch->np; + + drm_bridge_add(&ldb_ch->bridge); + } +} + +static inline void ldb_remove_bridge_helper(struct ldb *ldb) +{ + struct ldb_channel *ldb_ch; + int i; + + for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { + ldb_ch = ldb->channel[i]; + + if (!ldb_ch->is_available) + continue; + + drm_bridge_remove(&ldb_ch->bridge); + } +} #endif /* __IMX_LDB_HELPER__ */ From patchwork Sat Nov 19 23:05:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23341 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp897222wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g5-20020a056a0023c500b00572e6576462si8566108pfc.97.2022.11.19.15.05.57; Sat, 19 Nov 2022 15:06:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=pSRcJSOl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234939AbiKSXFS (ORCPT + 99 others); Sat, 19 Nov 2022 18:05:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234831AbiKSXFM (ORCPT ); Sat, 19 Nov 2022 18:05:12 -0500 Received: from mail-0301.mail-europe.com (mail-0301.mail-europe.com [188.165.51.139]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F12D193C8; Sat, 19 Nov 2022 15:05:11 -0800 (PST) Date: Sat, 19 Nov 2022 23:05:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899107; x=1669158307; bh=qtJUwxO1gU/9fogSlSe7LmUizU2SKQNHgO3ln3wm+PE=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=pSRcJSOlcTylSXarISf52/2BAmUavEpID44NiT/wMnPrAYn3+VBP0sKkLkA9wKzqd y9N1Ckan+Hd/mP3sXhritgwwaPVD6jtn+aEeqUXubi6Z6f43iMemZ2a+qLYu8wFYGi Y5dbWF3YSDzlhnxRzIiGQWWRcvSaK3uf/7LGOlcq6X+oEiIWM/mPgSScCv19nDtchu y5If6PZ5lYfhLEM7Xl/kwGiHWN9BY53dvTU1zKE7gyOAy4UgTI0NK4QKTde6CIiJam N4smsEoa/BdSCoji/tjSdksz6HghrKdHHxS0FMGwHs/JnQvHDyNGBvZ0CGv7dF9pJb gJgGETOYJrGSA== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/18] drm/bridge: imx: turn imx8{qm,qxp}-ldb into single-object modules Message-ID: <20221119225650.1044591-4-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967616204694641?= X-GMAIL-MSGID: =?utf-8?q?1749967616204694641?= From: Masahiro Yamada With the previous fix, these modules are built from a single C file. Rename the source files so they match the module names. Signed-off-by: Masahiro Yamada Reviewed-and-tested-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- drivers/gpu/drm/bridge/imx/Makefile | 4 ---- drivers/gpu/drm/bridge/imx/{imx8qm-ldb-drv.c => imx8qm-ldb.c} | 0 .../gpu/drm/bridge/imx/{imx8qxp-ldb-drv.c => imx8qxp-ldb.c} | 0 3 files changed, 4 deletions(-) rename drivers/gpu/drm/bridge/imx/{imx8qm-ldb-drv.c => imx8qm-ldb.c} (100%) rename drivers/gpu/drm/bridge/imx/{imx8qxp-ldb-drv.c => imx8qxp-ldb.c} (100%) -- 2.38.1 diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile index 64b93009376a..c102443f7286 100644 --- a/drivers/gpu/drm/bridge/imx/Makefile +++ b/drivers/gpu/drm/bridge/imx/Makefile @@ -1,9 +1,5 @@ -imx8qm-ldb-objs := imx8qm-ldb-drv.o obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o - -imx8qxp-ldb-objs := imx8qxp-ldb-drv.o obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o - obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb.c similarity index 100% rename from drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c rename to drivers/gpu/drm/bridge/imx/imx8qm-ldb.c diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c similarity index 100% rename from drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c rename to drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c From patchwork Sat Nov 19 23:05:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23342 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp897417wrr; Sat, 19 Nov 2022 15:06:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf72akofS4InMy12JO6GM0SbFvMbwejGwJMKUhrqTlezyFCJ97NEqJ4VPL//4cuZEVZW+mWV X-Received: by 2002:aa7:8693:0:b0:56b:823d:e3b5 with SMTP id d19-20020aa78693000000b0056b823de3b5mr14036014pfo.81.1668899198237; Sat, 19 Nov 2022 15:06:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899198; cv=none; d=google.com; s=arc-20160816; b=bn4+VJYXkyOhMupRXyvrex6j/7boVlxHPje9dc+sQqsxgSQ91q7OLbdRzRvOzhTGZQ t1y5fMusS3ntDidOeIIwsPRjEdXOF/JKalcaKSwO+iNhW5UeqeO2BQW2hYhSkyz3w1Lj tI9pSmTqnUus+r/ClBTpwBQ5Hruw2R2d+oVDzYZYiRjfBJlOq4wM2v2GyIYoKCWAjRSW E4iAc9gNTLtGUVewNdj/mFOAylNb+c1VyoCNCT3iH/iPP51cTl3AlByE3dfXhf+cYIJn JBBjBIjQJXpViSox9QJ8J4j0tWz1YXBy+E2vUmLRWFOmjehPjcxyqJPqE16xCEsbc3FI LzYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :feedback-id:references:in-reply-to:message-id:subject:cc:from:to :dkim-signature:date; bh=V3uAiCPOJvJO1/bAuuTiv4LrpZ20hZIiLLgtCVRDo4U=; b=dFMA35DetLCWQzGwMjrqjItjfodIu5fPvQHIoPjAqQgVgaGbwuH3YFe2rQBau4r8qb enC3DCKKLwfYrazpx2HNH6x0jHkcIGWQNWju7ebyXVPEd30ikMrYqCPkuERiYDeT7hxz sGsRqpvkf2leXY0dmJHG8zjM4eQGt2VyBC02y3MbgOIvp0UPby43Wncg7A02ERucFfu5 /QQHXjkhvZ7Ab5uoPJ92hWbQwwXBoQ1V5MBQIPcb46k38UiEWfFu6zm5jmW6cZoQWvhv 7B9Pvom4vMuoH105dD+/KC1HzO780UPVQkajbv/hrN2E1HcXhwryjhvUP5D6VgDV/+tn 6ZKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=eR6tRKz8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b17-20020a056a000a9100b005634d0b379dsi7951003pfl.115.2022.11.19.15.06.24; Sat, 19 Nov 2022 15:06:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=eR6tRKz8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234992AbiKSXFs (ORCPT + 99 others); Sat, 19 Nov 2022 18:05:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234908AbiKSXFm (ORCPT ); Sat, 19 Nov 2022 18:05:42 -0500 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 342B51A059; Sat, 19 Nov 2022 15:05:39 -0800 (PST) Date: Sat, 19 Nov 2022 23:05:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899136; x=1669158336; bh=V3uAiCPOJvJO1/bAuuTiv4LrpZ20hZIiLLgtCVRDo4U=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=eR6tRKz8seLDf7+ry5VHWMW0aHe5eJO0B7j0qstJY24kVIMAkmXqMjud2QPK7gtUl 2BAYOURlrT+277C2HhtJl/GGjy4BJXoCOO3pyhrO8P5DrhQNfoMxQui+DwFTLDH/+r ElkIsDqhtD+AjG1taIiQY0gDhsfj4b5tuNBi56nRSNNvlDot706nBu4CyBK/dJHyWs bZXkeFsik5erghU87capqul7Ohjuhv8r+Jczpr3f1vfUVDa+R7fOtaf90yY//1VMrG bzfPOZwpmlKViFlc4Hvb9ze6144L8JO9VQN0gHJKBHFOxzCGvajZEwsmBdLvfP/PCt iDqFlEJuNlWBw== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/18] sound: fix mixed module-builtin object Message-ID: <20221119225650.1044591-5-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967645538110094?= X-GMAIL-MSGID: =?utf-8?q?1749967645538110094?= From: Masahiro Yamada With 'y' and 'm' mixed for CONFIG_SNC_SOC_WCD93{35,4X,8X}, wcd-clsh-v2.o is linked to module(s) and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Turn helpers in wcd-clsh-v2.o into inline functions. Signed-off-by: Masahiro Yamada Reviewed-and-tested-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- sound/soc/codecs/Makefile | 6 +- sound/soc/codecs/wcd-clsh-v2.c | 903 -------------------------------- sound/soc/codecs/wcd-clsh-v2.h | 917 ++++++++++++++++++++++++++++++++- 3 files changed, 907 insertions(+), 919 deletions(-) delete mode 100644 sound/soc/codecs/wcd-clsh-v2.c -- 2.38.1 diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9170ee1447dd..90c3c610a72f 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -279,9 +279,9 @@ snd-soc-uda1334-objs := uda1334.o snd-soc-uda134x-objs := uda134x.o snd-soc-uda1380-objs := uda1380.o snd-soc-wcd-mbhc-objs := wcd-mbhc-v2.o -snd-soc-wcd9335-objs := wcd-clsh-v2.o wcd9335.o -snd-soc-wcd934x-objs := wcd-clsh-v2.o wcd934x.o -snd-soc-wcd938x-objs := wcd938x.o wcd-clsh-v2.o +snd-soc-wcd9335-objs := wcd9335.o +snd-soc-wcd934x-objs := wcd934x.o +snd-soc-wcd938x-objs := wcd938x.o snd-soc-wcd938x-sdw-objs := wcd938x-sdw.o snd-soc-wl1273-objs := wl1273.o snd-soc-wm-adsp-objs := wm_adsp.o diff --git a/sound/soc/codecs/wcd-clsh-v2.c b/sound/soc/codecs/wcd-clsh-v2.c deleted file mode 100644 index 4c7ebc7fb400..000000000000 --- a/sound/soc/codecs/wcd-clsh-v2.c +++ /dev/null @@ -1,903 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. -// Copyright (c) 2017-2018, Linaro Limited - -#include -#include -#include -#include -#include "wcd9335.h" -#include "wcd-clsh-v2.h" - -struct wcd_clsh_ctrl { - int state; - int mode; - int flyback_users; - int buck_users; - int clsh_users; - int codec_version; - struct snd_soc_component *comp; -}; - -/* Class-H registers for codecs from and above WCD9335 */ -#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0xB, 0x42) -#define WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK BIT(6) -#define WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE BIT(6) -#define WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE 0 -#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0xB, 0x56) -#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0xB, 0x6A) -#define WCD9XXX_A_CDC_CLSH_K1_MSB WCD9335_REG(0xC, 0x08) -#define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK GENMASK(3, 0) -#define WCD9XXX_A_CDC_CLSH_K1_LSB WCD9335_REG(0xC, 0x09) -#define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK GENMASK(7, 0) -#define WCD9XXX_A_ANA_RX_SUPPLIES WCD9335_REG(0x6, 0x08) -#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK BIT(1) -#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H 0 -#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB BIT(1) -#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK BIT(2) -#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA BIT(2) -#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT 0 -#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK BIT(3) -#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA BIT(3) -#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT 0 -#define WCD9XXX_A_ANA_RX_VNEG_EN_MASK BIT(6) -#define WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT 6 -#define WCD9XXX_A_ANA_RX_VNEG_ENABLE BIT(6) -#define WCD9XXX_A_ANA_RX_VNEG_DISABLE 0 -#define WCD9XXX_A_ANA_RX_VPOS_EN_MASK BIT(7) -#define WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT 7 -#define WCD9XXX_A_ANA_RX_VPOS_ENABLE BIT(7) -#define WCD9XXX_A_ANA_RX_VPOS_DISABLE 0 -#define WCD9XXX_A_ANA_HPH WCD9335_REG(0x6, 0x09) -#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK GENMASK(3, 2) -#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA 0x08 -#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP 0x04 -#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL 0x0 -#define WCD9XXX_A_CDC_CLSH_CRC WCD9335_REG(0xC, 0x01) -#define WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK BIT(0) -#define WCD9XXX_A_CDC_CLSH_CRC_CLK_ENABLE BIT(0) -#define WCD9XXX_A_CDC_CLSH_CRC_CLK_DISABLE 0 -#define WCD9XXX_FLYBACK_EN WCD9335_REG(0x6, 0xA4) -#define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK GENMASK(6, 5) -#define WCD9XXX_FLYBACK_EN_DELAY_26P25_US 0x40 -#define WCD9XXX_FLYBACK_EN_RESET_BY_EXT_MASK BIT(4) -#define WCD9XXX_FLYBACK_EN_PWDN_WITHOUT_DELAY BIT(4) -#define WCD9XXX_FLYBACK_EN_PWDN_WITH_DELAY 0 -#define WCD9XXX_RX_BIAS_FLYB_BUFF WCD9335_REG(0x6, 0xC7) -#define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4) -#define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0) -#define WCD9XXX_HPH_L_EN WCD9335_REG(0x6, 0xD3) -#define WCD9XXX_HPH_CONST_SEL_L_MASK GENMASK(7, 3) -#define WCD9XXX_HPH_CONST_SEL_BYPASS 0 -#define WCD9XXX_HPH_CONST_SEL_LP_PATH 0x40 -#define WCD9XXX_HPH_CONST_SEL_HQ_PATH 0x80 -#define WCD9XXX_HPH_R_EN WCD9335_REG(0x6, 0xD6) -#define WCD9XXX_HPH_REFBUFF_UHQA_CTL WCD9335_REG(0x6, 0xDD) -#define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK GENMASK(2, 0) -#define WCD9XXX_CLASSH_CTRL_VCL_2 WCD9335_REG(0x6, 0x9B) -#define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK GENMASK(5, 4) -#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM 0x20 -#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM 0x0 -#define WCD9XXX_CDC_RX1_RX_PATH_CTL WCD9335_REG(0xB, 0x55) -#define WCD9XXX_CDC_RX2_RX_PATH_CTL WCD9335_REG(0xB, 0x69) -#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0xD, 0x41) -#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0) -#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_11P3_EN_MASK BIT(1) -#define WCD9XXX_CLASSH_CTRL_CCL_1 WCD9335_REG(0x6, 0x9C) -#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK GENMASK(7, 4) -#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA 0x50 -#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA 0x30 - -#define WCD9XXX_BASE_ADDRESS 0x3000 -#define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008) -#define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009) -#define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098) -#define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099) -#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5) -#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8) -#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF) -#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF) -#define WCD9XXX_V3_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7) -#define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1) -#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138) - -#define CLSH_REQ_ENABLE true -#define CLSH_REQ_DISABLE false -#define WCD_USLEEP_RANGE 50 - -enum { - DAC_GAIN_0DB = 0, - DAC_GAIN_0P2DB, - DAC_GAIN_0P4DB, - DAC_GAIN_0P6DB, - DAC_GAIN_0P8DB, - DAC_GAIN_M0P2DB, - DAC_GAIN_M0P4DB, - DAC_GAIN_M0P6DB, -}; - -static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl, - bool enable) -{ - struct snd_soc_component *comp = ctrl->comp; - - if ((enable && ++ctrl->clsh_users == 1) || - (!enable && --ctrl->clsh_users == 0)) - snd_soc_component_update_bits(comp, WCD9XXX_A_CDC_CLSH_CRC, - WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK, - enable); - if (ctrl->clsh_users < 0) - ctrl->clsh_users = 0; -} - -static inline bool wcd_clsh_enable_status(struct snd_soc_component *comp) -{ - return snd_soc_component_read(comp, WCD9XXX_A_CDC_CLSH_CRC) & - WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK; -} - -static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *comp, - int mode) -{ - /* set to HIFI */ - if (mode == CLS_H_HIFI) - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK, - WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA); - else - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK, - WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT); -} - -static void wcd_clsh_v3_set_buck_mode(struct snd_soc_component *component, - int mode) -{ - if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI || - mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) - snd_soc_component_update_bits(component, - WCD9XXX_ANA_RX_SUPPLIES, - 0x08, 0x08); /* set to HIFI */ - else - snd_soc_component_update_bits(component, - WCD9XXX_ANA_RX_SUPPLIES, - 0x08, 0x00); /* set to default */ -} - -static inline void wcd_clsh_set_flyback_mode(struct snd_soc_component *comp, - int mode) -{ - /* set to HIFI */ - if (mode == CLS_H_HIFI) - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK, - WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA); - else - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK, - WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT); -} - -static void wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl *ctrl, - int mode, - bool enable) -{ - struct snd_soc_component *comp = ctrl->comp; - - /* enable/disable buck */ - if ((enable && (++ctrl->buck_users == 1)) || - (!enable && (--ctrl->buck_users == 0))) - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_VPOS_EN_MASK, - enable << WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT); - /* - * 500us sleep is required after buck enable/disable - * as per HW requirement - */ - usleep_range(500, 500 + WCD_USLEEP_RANGE); -} - -static void wcd_clsh_v3_buck_ctrl(struct snd_soc_component *component, - struct wcd_clsh_ctrl *ctrl, - int mode, - bool enable) -{ - /* enable/disable buck */ - if ((enable && (++ctrl->buck_users == 1)) || - (!enable && (--ctrl->buck_users == 0))) { - snd_soc_component_update_bits(component, - WCD9XXX_ANA_RX_SUPPLIES, - (1 << 7), (enable << 7)); - /* - * 500us sleep is required after buck enable/disable - * as per HW requirement - */ - usleep_range(500, 510); - if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP || - mode == CLS_H_HIFI || mode == CLS_H_LP) - snd_soc_component_update_bits(component, - WCD9XXX_CLASSH_MODE_3, - 0x02, 0x00); - - snd_soc_component_update_bits(component, - WCD9XXX_CLASSH_MODE_2, - 0xFF, 0x3A); - /* 500usec delay is needed as per HW requirement */ - usleep_range(500, 500 + WCD_USLEEP_RANGE); - } -} - -static void wcd_clsh_flyback_ctrl(struct wcd_clsh_ctrl *ctrl, - int mode, - bool enable) -{ - struct snd_soc_component *comp = ctrl->comp; - - /* enable/disable flyback */ - if ((enable && (++ctrl->flyback_users == 1)) || - (!enable && (--ctrl->flyback_users == 0))) { - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_VNEG_EN_MASK, - enable << WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT); - /* 100usec delay is needed as per HW requirement */ - usleep_range(100, 110); - } - /* - * 500us sleep is required after flyback enable/disable - * as per HW requirement - */ - usleep_range(500, 500 + WCD_USLEEP_RANGE); -} - -static void wcd_clsh_set_gain_path(struct wcd_clsh_ctrl *ctrl, int mode) -{ - struct snd_soc_component *comp = ctrl->comp; - int val = 0; - - switch (mode) { - case CLS_H_NORMAL: - case CLS_AB: - val = WCD9XXX_HPH_CONST_SEL_BYPASS; - break; - case CLS_H_HIFI: - val = WCD9XXX_HPH_CONST_SEL_HQ_PATH; - break; - case CLS_H_LP: - val = WCD9XXX_HPH_CONST_SEL_LP_PATH; - break; - } - - snd_soc_component_update_bits(comp, WCD9XXX_HPH_L_EN, - WCD9XXX_HPH_CONST_SEL_L_MASK, - val); - - snd_soc_component_update_bits(comp, WCD9XXX_HPH_R_EN, - WCD9XXX_HPH_CONST_SEL_L_MASK, - val); -} - -static void wcd_clsh_v2_set_hph_mode(struct snd_soc_component *comp, int mode) -{ - int val = 0, gain = 0, res_val; - int ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; - - res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM; - switch (mode) { - case CLS_H_NORMAL: - res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM; - val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL; - gain = DAC_GAIN_0DB; - ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; - break; - case CLS_AB: - val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL; - gain = DAC_GAIN_0DB; - ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; - break; - case CLS_H_HIFI: - val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA; - gain = DAC_GAIN_M0P2DB; - ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; - break; - case CLS_H_LP: - val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP; - ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA; - break; - } - - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_HPH, - WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK, val); - snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_VCL_2, - WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK, - res_val); - if (mode != CLS_H_LP) - snd_soc_component_update_bits(comp, - WCD9XXX_HPH_REFBUFF_UHQA_CTL, - WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK, - gain); - snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_CCL_1, - WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK, - ipeak); -} - -static void wcd_clsh_v3_set_hph_mode(struct snd_soc_component *component, - int mode) -{ - u8 val; - - switch (mode) { - case CLS_H_NORMAL: - val = 0x00; - break; - case CLS_AB: - case CLS_H_ULP: - val = 0x0C; - break; - case CLS_AB_HIFI: - case CLS_H_HIFI: - val = 0x08; - break; - case CLS_H_LP: - case CLS_H_LOHIFI: - case CLS_AB_LP: - case CLS_AB_LOHIFI: - val = 0x04; - break; - default: - dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode); - return; - } - - snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val); -} - -void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl, int mode) -{ - struct snd_soc_component *comp = ctrl->comp; - - if (ctrl->codec_version >= WCD937X) - wcd_clsh_v3_set_hph_mode(comp, mode); - else - wcd_clsh_v2_set_hph_mode(comp, mode); - -} - -static void wcd_clsh_set_flyback_current(struct snd_soc_component *comp, - int mode) -{ - - snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF, - WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK, 0x0A); - snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF, - WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK, 0x0A); - /* Sleep needed to avoid click and pop as per HW requirement */ - usleep_range(100, 110); -} - -static void wcd_clsh_set_buck_regulator_mode(struct snd_soc_component *comp, - int mode) -{ - if (mode == CLS_AB) - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK, - WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB); - else - snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, - WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK, - WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H); -} - -static void wcd_clsh_v3_set_buck_regulator_mode(struct snd_soc_component *component, - int mode) -{ - snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES, - 0x02, 0x00); -} - -static void wcd_clsh_v3_set_flyback_mode(struct snd_soc_component *component, - int mode) -{ - if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI || - mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) { - snd_soc_component_update_bits(component, - WCD9XXX_ANA_RX_SUPPLIES, - 0x04, 0x04); - snd_soc_component_update_bits(component, - WCD9XXX_FLYBACK_VNEG_CTRL_4, - 0xF0, 0x80); - } else { - snd_soc_component_update_bits(component, - WCD9XXX_ANA_RX_SUPPLIES, - 0x04, 0x00); /* set to Default */ - snd_soc_component_update_bits(component, - WCD9XXX_FLYBACK_VNEG_CTRL_4, - 0xF0, 0x70); - } -} - -static void wcd_clsh_v3_force_iq_ctl(struct snd_soc_component *component, - int mode, bool enable) -{ - if (enable) { - snd_soc_component_update_bits(component, - WCD9XXX_FLYBACK_VNEGDAC_CTRL_2, - 0xE0, 0xA0); - /* 100usec delay is needed as per HW requirement */ - usleep_range(100, 110); - snd_soc_component_update_bits(component, - WCD9XXX_CLASSH_MODE_3, - 0x02, 0x02); - snd_soc_component_update_bits(component, - WCD9XXX_CLASSH_MODE_2, - 0xFF, 0x1C); - if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) { - snd_soc_component_update_bits(component, - WCD9XXX_HPH_NEW_INT_PA_MISC2, - 0x20, 0x20); - snd_soc_component_update_bits(component, - WCD9XXX_RX_BIAS_HPH_LOWPOWER, - 0xF0, 0xC0); - snd_soc_component_update_bits(component, - WCD9XXX_HPH_PA_CTL1, - 0x0E, 0x02); - } - } else { - snd_soc_component_update_bits(component, - WCD9XXX_HPH_NEW_INT_PA_MISC2, - 0x20, 0x00); - snd_soc_component_update_bits(component, - WCD9XXX_RX_BIAS_HPH_LOWPOWER, - 0xF0, 0x80); - snd_soc_component_update_bits(component, - WCD9XXX_HPH_PA_CTL1, - 0x0E, 0x06); - } -} - -static void wcd_clsh_v3_flyback_ctrl(struct snd_soc_component *component, - struct wcd_clsh_ctrl *ctrl, - int mode, - bool enable) -{ - /* enable/disable flyback */ - if ((enable && (++ctrl->flyback_users == 1)) || - (!enable && (--ctrl->flyback_users == 0))) { - snd_soc_component_update_bits(component, - WCD9XXX_FLYBACK_VNEG_CTRL_1, - 0xE0, 0xE0); - snd_soc_component_update_bits(component, - WCD9XXX_ANA_RX_SUPPLIES, - (1 << 6), (enable << 6)); - /* - * 100us sleep is required after flyback enable/disable - * as per HW requirement - */ - usleep_range(100, 110); - snd_soc_component_update_bits(component, - WCD9XXX_FLYBACK_VNEGDAC_CTRL_2, - 0xE0, 0xE0); - /* 500usec delay is needed as per HW requirement */ - usleep_range(500, 500 + WCD_USLEEP_RANGE); - } -} - -static void wcd_clsh_v3_set_flyback_current(struct snd_soc_component *component, - int mode) -{ - snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF, - 0x0F, 0x0A); - snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF, - 0xF0, 0xA0); - /* Sleep needed to avoid click and pop as per HW requirement */ - usleep_range(100, 110); -} - -static void wcd_clsh_v3_state_aux(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *component = ctrl->comp; - - if (is_enable) { - wcd_clsh_v3_set_buck_mode(component, mode); - wcd_clsh_v3_set_flyback_mode(component, mode); - wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); - wcd_clsh_v3_set_flyback_current(component, mode); - wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); - } else { - wcd_clsh_v3_buck_ctrl(component, ctrl, mode, false); - wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, false); - wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); - wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); - } -} - -static void wcd_clsh_state_lo(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *comp = ctrl->comp; - - if (mode != CLS_AB) { - dev_err(comp->dev, "%s: LO cannot be in this mode: %d\n", - __func__, mode); - return; - } - - if (is_enable) { - wcd_clsh_set_buck_regulator_mode(comp, mode); - wcd_clsh_set_buck_mode(comp, mode); - wcd_clsh_set_flyback_mode(comp, mode); - wcd_clsh_flyback_ctrl(ctrl, mode, true); - wcd_clsh_set_flyback_current(comp, mode); - wcd_clsh_buck_ctrl(ctrl, mode, true); - } else { - wcd_clsh_buck_ctrl(ctrl, mode, false); - wcd_clsh_flyback_ctrl(ctrl, mode, false); - wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); - wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); - wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL); - } -} - -static void wcd_clsh_v3_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *component = ctrl->comp; - - if (mode == CLS_H_NORMAL) { - dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n", - __func__); - return; - } - - if (is_enable) { - wcd_clsh_v3_set_buck_regulator_mode(component, mode); - wcd_clsh_v3_set_flyback_mode(component, mode); - wcd_clsh_v3_force_iq_ctl(component, mode, true); - wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); - wcd_clsh_v3_set_flyback_current(component, mode); - wcd_clsh_v3_set_buck_mode(component, mode); - wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); - wcd_clsh_v3_set_hph_mode(component, mode); - } else { - wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL); - - /* buck and flyback set to default mode and disable */ - wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false); - wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false); - wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false); - wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); - wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); - } -} - -static void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *comp = ctrl->comp; - - if (mode == CLS_H_NORMAL) { - dev_err(comp->dev, "%s: Normal mode not applicable for hph_r\n", - __func__); - return; - } - - if (is_enable) { - if (mode != CLS_AB) { - wcd_enable_clsh_block(ctrl, true); - /* - * These K1 values depend on the Headphone Impedance - * For now it is assumed to be 16 ohm - */ - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_CLSH_K1_MSB, - WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK, - 0x00); - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_CLSH_K1_LSB, - WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK, - 0xC0); - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_RX2_RX_PATH_CFG0, - WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, - WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE); - } - wcd_clsh_set_buck_regulator_mode(comp, mode); - wcd_clsh_set_flyback_mode(comp, mode); - wcd_clsh_flyback_ctrl(ctrl, mode, true); - wcd_clsh_set_flyback_current(comp, mode); - wcd_clsh_set_buck_mode(comp, mode); - wcd_clsh_buck_ctrl(ctrl, mode, true); - wcd_clsh_v2_set_hph_mode(comp, mode); - wcd_clsh_set_gain_path(ctrl, mode); - } else { - wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL); - - if (mode != CLS_AB) { - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_RX2_RX_PATH_CFG0, - WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, - WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE); - wcd_enable_clsh_block(ctrl, false); - } - /* buck and flyback set to default mode and disable */ - wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false); - wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false); - wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); - wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); - wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL); - } -} - -static void wcd_clsh_v3_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *component = ctrl->comp; - - if (mode == CLS_H_NORMAL) { - dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n", - __func__); - return; - } - - if (is_enable) { - wcd_clsh_v3_set_buck_regulator_mode(component, mode); - wcd_clsh_v3_set_flyback_mode(component, mode); - wcd_clsh_v3_force_iq_ctl(component, mode, true); - wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); - wcd_clsh_v3_set_flyback_current(component, mode); - wcd_clsh_v3_set_buck_mode(component, mode); - wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); - wcd_clsh_v3_set_hph_mode(component, mode); - } else { - wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL); - - /* set buck and flyback to Default Mode */ - wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false); - wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false); - wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false); - wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); - wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); - } -} - -static void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *comp = ctrl->comp; - - if (mode == CLS_H_NORMAL) { - dev_err(comp->dev, "%s: Normal mode not applicable for hph_l\n", - __func__); - return; - } - - if (is_enable) { - if (mode != CLS_AB) { - wcd_enable_clsh_block(ctrl, true); - /* - * These K1 values depend on the Headphone Impedance - * For now it is assumed to be 16 ohm - */ - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_CLSH_K1_MSB, - WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK, - 0x00); - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_CLSH_K1_LSB, - WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK, - 0xC0); - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_RX1_RX_PATH_CFG0, - WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, - WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE); - } - wcd_clsh_set_buck_regulator_mode(comp, mode); - wcd_clsh_set_flyback_mode(comp, mode); - wcd_clsh_flyback_ctrl(ctrl, mode, true); - wcd_clsh_set_flyback_current(comp, mode); - wcd_clsh_set_buck_mode(comp, mode); - wcd_clsh_buck_ctrl(ctrl, mode, true); - wcd_clsh_v2_set_hph_mode(comp, mode); - wcd_clsh_set_gain_path(ctrl, mode); - } else { - wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL); - - if (mode != CLS_AB) { - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_RX1_RX_PATH_CFG0, - WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, - WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE); - wcd_enable_clsh_block(ctrl, false); - } - /* set buck and flyback to Default Mode */ - wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false); - wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false); - wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); - wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); - wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL); - } -} - -static void wcd_clsh_v3_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *component = ctrl->comp; - - if (is_enable) { - wcd_clsh_v3_set_buck_regulator_mode(component, mode); - wcd_clsh_v3_set_flyback_mode(component, mode); - wcd_clsh_v3_force_iq_ctl(component, mode, true); - wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); - wcd_clsh_v3_set_flyback_current(component, mode); - wcd_clsh_v3_set_buck_mode(component, mode); - wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); - wcd_clsh_v3_set_hph_mode(component, mode); - } else { - wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL); - - /* set buck and flyback to Default Mode */ - wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false); - wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false); - wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false); - wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); - wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); - } -} - -static void wcd_clsh_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - struct snd_soc_component *comp = ctrl->comp; - - if (mode != CLS_H_NORMAL) { - dev_err(comp->dev, "%s: mode: %d cannot be used for EAR\n", - __func__, mode); - return; - } - - if (is_enable) { - wcd_enable_clsh_block(ctrl, true); - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_RX0_RX_PATH_CFG0, - WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, - WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE); - wcd_clsh_set_buck_mode(comp, mode); - wcd_clsh_set_flyback_mode(comp, mode); - wcd_clsh_flyback_ctrl(ctrl, mode, true); - wcd_clsh_set_flyback_current(comp, mode); - wcd_clsh_buck_ctrl(ctrl, mode, true); - } else { - snd_soc_component_update_bits(comp, - WCD9XXX_A_CDC_RX0_RX_PATH_CFG0, - WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, - WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE); - wcd_enable_clsh_block(ctrl, false); - wcd_clsh_buck_ctrl(ctrl, mode, false); - wcd_clsh_flyback_ctrl(ctrl, mode, false); - wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); - wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); - } -} - -static int _wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, int req_state, - bool is_enable, int mode) -{ - switch (req_state) { - case WCD_CLSH_STATE_EAR: - if (ctrl->codec_version >= WCD937X) - wcd_clsh_v3_state_ear(ctrl, req_state, is_enable, mode); - else - wcd_clsh_state_ear(ctrl, req_state, is_enable, mode); - break; - case WCD_CLSH_STATE_HPHL: - if (ctrl->codec_version >= WCD937X) - wcd_clsh_v3_state_hph_l(ctrl, req_state, is_enable, mode); - else - wcd_clsh_state_hph_l(ctrl, req_state, is_enable, mode); - break; - case WCD_CLSH_STATE_HPHR: - if (ctrl->codec_version >= WCD937X) - wcd_clsh_v3_state_hph_r(ctrl, req_state, is_enable, mode); - else - wcd_clsh_state_hph_r(ctrl, req_state, is_enable, mode); - break; - case WCD_CLSH_STATE_LO: - if (ctrl->codec_version < WCD937X) - wcd_clsh_state_lo(ctrl, req_state, is_enable, mode); - break; - case WCD_CLSH_STATE_AUX: - if (ctrl->codec_version >= WCD937X) - wcd_clsh_v3_state_aux(ctrl, req_state, is_enable, mode); - break; - default: - break; - } - - return 0; -} - -/* - * Function: wcd_clsh_is_state_valid - * Params: state - * Description: - * Provides information on valid states of Class H configuration - */ -static bool wcd_clsh_is_state_valid(int state) -{ - switch (state) { - case WCD_CLSH_STATE_IDLE: - case WCD_CLSH_STATE_EAR: - case WCD_CLSH_STATE_HPHL: - case WCD_CLSH_STATE_HPHR: - case WCD_CLSH_STATE_LO: - case WCD_CLSH_STATE_AUX: - return true; - default: - return false; - }; -} - -/* - * Function: wcd_clsh_fsm - * Params: ctrl, req_state, req_type, clsh_event - * Description: - * This function handles PRE DAC and POST DAC conditions of different devices - * and updates class H configuration of different combination of devices - * based on validity of their states. ctrl will contain current - * class h state information - */ -int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, - enum wcd_clsh_event clsh_event, - int nstate, - enum wcd_clsh_mode mode) -{ - struct snd_soc_component *comp = ctrl->comp; - - if (nstate == ctrl->state) - return 0; - - if (!wcd_clsh_is_state_valid(nstate)) { - dev_err(comp->dev, "Class-H not a valid new state:\n"); - return -EINVAL; - } - - switch (clsh_event) { - case WCD_CLSH_EVENT_PRE_DAC: - _wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_ENABLE, mode); - break; - case WCD_CLSH_EVENT_POST_PA: - _wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_DISABLE, mode); - break; - } - - ctrl->state = nstate; - ctrl->mode = mode; - - return 0; -} - -int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl) -{ - return ctrl->state; -} - -struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(struct snd_soc_component *comp, - int version) -{ - struct wcd_clsh_ctrl *ctrl; - - ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) - return ERR_PTR(-ENOMEM); - - ctrl->state = WCD_CLSH_STATE_IDLE; - ctrl->comp = comp; - ctrl->codec_version = version; - - return ctrl; -} - -void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl) -{ - kfree(ctrl); -} diff --git a/sound/soc/codecs/wcd-clsh-v2.h b/sound/soc/codecs/wcd-clsh-v2.h index 4e3653058275..3074e9b235d4 100644 --- a/sound/soc/codecs/wcd-clsh-v2.h +++ b/sound/soc/codecs/wcd-clsh-v2.h @@ -2,8 +2,14 @@ #ifndef _WCD_CLSH_V2_H_ #define _WCD_CLSH_V2_H_ + +#include +#include +#include #include +#include "wcd9335.h" + enum wcd_clsh_event { WCD_CLSH_EVENT_PRE_DAC = 1, WCD_CLSH_EVENT_POST_PA, @@ -48,18 +54,903 @@ enum wcd_codec_version { WCD937X = 2, WCD938X = 3, }; -struct wcd_clsh_ctrl; - -extern struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc( - struct snd_soc_component *comp, - int version); -extern void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl); -extern int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl); -extern int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, - enum wcd_clsh_event clsh_event, - int nstate, - enum wcd_clsh_mode mode); -extern void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl, - int mode); + +struct wcd_clsh_ctrl { + int state; + int mode; + int flyback_users; + int buck_users; + int clsh_users; + int codec_version; + struct snd_soc_component *comp; +}; + +/* Class-H registers for codecs from and above WCD9335 */ +#define WCD9XXX_A_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0xB, 0x42) +#define WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK BIT(6) +#define WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE BIT(6) +#define WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE 0 +#define WCD9XXX_A_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0xB, 0x56) +#define WCD9XXX_A_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0xB, 0x6A) +#define WCD9XXX_A_CDC_CLSH_K1_MSB WCD9335_REG(0xC, 0x08) +#define WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK GENMASK(3, 0) +#define WCD9XXX_A_CDC_CLSH_K1_LSB WCD9335_REG(0xC, 0x09) +#define WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK GENMASK(7, 0) +#define WCD9XXX_A_ANA_RX_SUPPLIES WCD9335_REG(0x6, 0x08) +#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK BIT(1) +#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H 0 +#define WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB BIT(1) +#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK BIT(2) +#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA BIT(2) +#define WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT 0 +#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK BIT(3) +#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA BIT(3) +#define WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT 0 +#define WCD9XXX_A_ANA_RX_VNEG_EN_MASK BIT(6) +#define WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT 6 +#define WCD9XXX_A_ANA_RX_VNEG_ENABLE BIT(6) +#define WCD9XXX_A_ANA_RX_VNEG_DISABLE 0 +#define WCD9XXX_A_ANA_RX_VPOS_EN_MASK BIT(7) +#define WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT 7 +#define WCD9XXX_A_ANA_RX_VPOS_ENABLE BIT(7) +#define WCD9XXX_A_ANA_RX_VPOS_DISABLE 0 +#define WCD9XXX_A_ANA_HPH WCD9335_REG(0x6, 0x09) +#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK GENMASK(3, 2) +#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA 0x08 +#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP 0x04 +#define WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL 0x0 +#define WCD9XXX_A_CDC_CLSH_CRC WCD9335_REG(0xC, 0x01) +#define WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK BIT(0) +#define WCD9XXX_A_CDC_CLSH_CRC_CLK_ENABLE BIT(0) +#define WCD9XXX_A_CDC_CLSH_CRC_CLK_DISABLE 0 +#define WCD9XXX_FLYBACK_EN WCD9335_REG(0x6, 0xA4) +#define WCD9XXX_FLYBACK_EN_DELAY_SEL_MASK GENMASK(6, 5) +#define WCD9XXX_FLYBACK_EN_DELAY_26P25_US 0x40 +#define WCD9XXX_FLYBACK_EN_RESET_BY_EXT_MASK BIT(4) +#define WCD9XXX_FLYBACK_EN_PWDN_WITHOUT_DELAY BIT(4) +#define WCD9XXX_FLYBACK_EN_PWDN_WITH_DELAY 0 +#define WCD9XXX_RX_BIAS_FLYB_BUFF WCD9335_REG(0x6, 0xC7) +#define WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4) +#define WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0) +#define WCD9XXX_HPH_L_EN WCD9335_REG(0x6, 0xD3) +#define WCD9XXX_HPH_CONST_SEL_L_MASK GENMASK(7, 3) +#define WCD9XXX_HPH_CONST_SEL_BYPASS 0 +#define WCD9XXX_HPH_CONST_SEL_LP_PATH 0x40 +#define WCD9XXX_HPH_CONST_SEL_HQ_PATH 0x80 +#define WCD9XXX_HPH_R_EN WCD9335_REG(0x6, 0xD6) +#define WCD9XXX_HPH_REFBUFF_UHQA_CTL WCD9335_REG(0x6, 0xDD) +#define WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK GENMASK(2, 0) +#define WCD9XXX_CLASSH_CTRL_VCL_2 WCD9335_REG(0x6, 0x9B) +#define WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK GENMASK(5, 4) +#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM 0x20 +#define WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM 0x0 +#define WCD9XXX_CDC_RX1_RX_PATH_CTL WCD9335_REG(0xB, 0x55) +#define WCD9XXX_CDC_RX2_RX_PATH_CTL WCD9335_REG(0xB, 0x69) +#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0xD, 0x41) +#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0) +#define WCD9XXX_CDC_CLK_RST_CTRL_MCLK_11P3_EN_MASK BIT(1) +#define WCD9XXX_CLASSH_CTRL_CCL_1 WCD9335_REG(0x6, 0x9C) +#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK GENMASK(7, 4) +#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA 0x50 +#define WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA 0x30 + +#define WCD9XXX_BASE_ADDRESS 0x3000 +#define WCD9XXX_ANA_RX_SUPPLIES (WCD9XXX_BASE_ADDRESS+0x008) +#define WCD9XXX_ANA_HPH (WCD9XXX_BASE_ADDRESS+0x009) +#define WCD9XXX_CLASSH_MODE_2 (WCD9XXX_BASE_ADDRESS+0x098) +#define WCD9XXX_CLASSH_MODE_3 (WCD9XXX_BASE_ADDRESS+0x099) +#define WCD9XXX_FLYBACK_VNEG_CTRL_1 (WCD9XXX_BASE_ADDRESS+0x0A5) +#define WCD9XXX_FLYBACK_VNEG_CTRL_4 (WCD9XXX_BASE_ADDRESS+0x0A8) +#define WCD9XXX_FLYBACK_VNEGDAC_CTRL_2 (WCD9XXX_BASE_ADDRESS+0x0AF) +#define WCD9XXX_RX_BIAS_HPH_LOWPOWER (WCD9XXX_BASE_ADDRESS+0x0BF) +#define WCD9XXX_V3_RX_BIAS_FLYB_BUFF (WCD9XXX_BASE_ADDRESS+0x0C7) +#define WCD9XXX_HPH_PA_CTL1 (WCD9XXX_BASE_ADDRESS+0x0D1) +#define WCD9XXX_HPH_NEW_INT_PA_MISC2 (WCD9XXX_BASE_ADDRESS+0x138) + +#define CLSH_REQ_ENABLE true +#define CLSH_REQ_DISABLE false +#define WCD_USLEEP_RANGE 50 + +enum { + DAC_GAIN_0DB = 0, + DAC_GAIN_0P2DB, + DAC_GAIN_0P4DB, + DAC_GAIN_0P6DB, + DAC_GAIN_0P8DB, + DAC_GAIN_M0P2DB, + DAC_GAIN_M0P4DB, + DAC_GAIN_M0P6DB, +}; + +static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl, + bool enable) +{ + struct snd_soc_component *comp = ctrl->comp; + + if ((enable && ++ctrl->clsh_users == 1) || + (!enable && --ctrl->clsh_users == 0)) + snd_soc_component_update_bits(comp, WCD9XXX_A_CDC_CLSH_CRC, + WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK, + enable); + if (ctrl->clsh_users < 0) + ctrl->clsh_users = 0; +} + +static inline bool wcd_clsh_enable_status(struct snd_soc_component *comp) +{ + return snd_soc_component_read(comp, WCD9XXX_A_CDC_CLSH_CRC) & + WCD9XXX_A_CDC_CLSH_CRC_CLK_EN_MASK; +} + +static inline void wcd_clsh_set_buck_mode(struct snd_soc_component *comp, + int mode) +{ + /* set to HIFI */ + if (mode == CLS_H_HIFI) + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK, + WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_UHQA); + else + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_MASK, + WCD9XXX_A_ANA_RX_VPOS_PWR_LVL_DEFAULT); +} + +static inline void wcd_clsh_v3_set_buck_mode(struct snd_soc_component *component, + int mode) +{ + if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI || + mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) + snd_soc_component_update_bits(component, + WCD9XXX_ANA_RX_SUPPLIES, + 0x08, 0x08); /* set to HIFI */ + else + snd_soc_component_update_bits(component, + WCD9XXX_ANA_RX_SUPPLIES, + 0x08, 0x00); /* set to default */ +} + +static inline void wcd_clsh_set_flyback_mode(struct snd_soc_component *comp, + int mode) +{ + /* set to HIFI */ + if (mode == CLS_H_HIFI) + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK, + WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_UHQA); + else + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_MASK, + WCD9XXX_A_ANA_RX_VNEG_PWR_LVL_DEFAULT); +} + +static inline void wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl *ctrl, + int mode, + bool enable) +{ + struct snd_soc_component *comp = ctrl->comp; + + /* enable/disable buck */ + if ((enable && (++ctrl->buck_users == 1)) || + (!enable && (--ctrl->buck_users == 0))) + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_VPOS_EN_MASK, + enable << WCD9XXX_A_ANA_RX_VPOS_EN_SHIFT); + /* + * 500us sleep is required after buck enable/disable + * as per HW requirement + */ + usleep_range(500, 500 + WCD_USLEEP_RANGE); +} + +static inline void wcd_clsh_v3_buck_ctrl(struct snd_soc_component *component, + struct wcd_clsh_ctrl *ctrl, + int mode, + bool enable) +{ + /* enable/disable buck */ + if ((enable && (++ctrl->buck_users == 1)) || + (!enable && (--ctrl->buck_users == 0))) { + snd_soc_component_update_bits(component, + WCD9XXX_ANA_RX_SUPPLIES, + (1 << 7), (enable << 7)); + /* + * 500us sleep is required after buck enable/disable + * as per HW requirement + */ + usleep_range(500, 510); + if (mode == CLS_H_LOHIFI || mode == CLS_H_ULP || + mode == CLS_H_HIFI || mode == CLS_H_LP) + snd_soc_component_update_bits(component, + WCD9XXX_CLASSH_MODE_3, + 0x02, 0x00); + + snd_soc_component_update_bits(component, + WCD9XXX_CLASSH_MODE_2, + 0xFF, 0x3A); + /* 500usec delay is needed as per HW requirement */ + usleep_range(500, 500 + WCD_USLEEP_RANGE); + } +} + +static inline void wcd_clsh_flyback_ctrl(struct wcd_clsh_ctrl *ctrl, + int mode, + bool enable) +{ + struct snd_soc_component *comp = ctrl->comp; + + /* enable/disable flyback */ + if ((enable && (++ctrl->flyback_users == 1)) || + (!enable && (--ctrl->flyback_users == 0))) { + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_VNEG_EN_MASK, + enable << WCD9XXX_A_ANA_RX_VNEG_EN_SHIFT); + /* 100usec delay is needed as per HW requirement */ + usleep_range(100, 110); + } + /* + * 500us sleep is required after flyback enable/disable + * as per HW requirement + */ + usleep_range(500, 500 + WCD_USLEEP_RANGE); +} + +static inline void wcd_clsh_set_gain_path(struct wcd_clsh_ctrl *ctrl, int mode) +{ + struct snd_soc_component *comp = ctrl->comp; + int val = 0; + + switch (mode) { + case CLS_H_NORMAL: + case CLS_AB: + val = WCD9XXX_HPH_CONST_SEL_BYPASS; + break; + case CLS_H_HIFI: + val = WCD9XXX_HPH_CONST_SEL_HQ_PATH; + break; + case CLS_H_LP: + val = WCD9XXX_HPH_CONST_SEL_LP_PATH; + break; + } + + snd_soc_component_update_bits(comp, WCD9XXX_HPH_L_EN, + WCD9XXX_HPH_CONST_SEL_L_MASK, + val); + + snd_soc_component_update_bits(comp, WCD9XXX_HPH_R_EN, + WCD9XXX_HPH_CONST_SEL_L_MASK, + val); +} + +static inline void wcd_clsh_v2_set_hph_mode(struct snd_soc_component *comp, + int mode) +{ + int val = 0, gain = 0, res_val; + int ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; + + res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_0KOHM; + switch (mode) { + case CLS_H_NORMAL: + res_val = WCD9XXX_CLASSH_CTRL_VCL_VREF_FILT_R_50KOHM; + val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL; + gain = DAC_GAIN_0DB; + ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; + break; + case CLS_AB: + val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_NORMAL; + gain = DAC_GAIN_0DB; + ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; + break; + case CLS_H_HIFI: + val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_UHQA; + gain = DAC_GAIN_M0P2DB; + ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_50MA; + break; + case CLS_H_LP: + val = WCD9XXX_A_ANA_HPH_PWR_LEVEL_LP; + ipeak = WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_30MA; + break; + } + + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_HPH, + WCD9XXX_A_ANA_HPH_PWR_LEVEL_MASK, val); + snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_VCL_2, + WCD9XXX_CLASSH_CTRL_VCL_2_VREF_FILT_1_MASK, + res_val); + if (mode != CLS_H_LP) + snd_soc_component_update_bits(comp, + WCD9XXX_HPH_REFBUFF_UHQA_CTL, + WCD9XXX_HPH_REFBUFF_UHQA_GAIN_MASK, + gain); + snd_soc_component_update_bits(comp, WCD9XXX_CLASSH_CTRL_CCL_1, + WCD9XXX_CLASSH_CTRL_CCL_1_DELTA_IPEAK_MASK, + ipeak); +} + +static inline void wcd_clsh_v3_set_hph_mode(struct snd_soc_component *component, + int mode) +{ + u8 val; + + switch (mode) { + case CLS_H_NORMAL: + val = 0x00; + break; + case CLS_AB: + case CLS_H_ULP: + val = 0x0C; + break; + case CLS_AB_HIFI: + case CLS_H_HIFI: + val = 0x08; + break; + case CLS_H_LP: + case CLS_H_LOHIFI: + case CLS_AB_LP: + case CLS_AB_LOHIFI: + val = 0x04; + break; + default: + dev_err(component->dev, "%s:Invalid mode %d\n", __func__, mode); + return; + } + + snd_soc_component_update_bits(component, WCD9XXX_ANA_HPH, 0x0C, val); +} + +static inline void wcd_clsh_set_hph_mode(struct wcd_clsh_ctrl *ctrl, int mode) +{ + struct snd_soc_component *comp = ctrl->comp; + + if (ctrl->codec_version >= WCD937X) + wcd_clsh_v3_set_hph_mode(comp, mode); + else + wcd_clsh_v2_set_hph_mode(comp, mode); + +} + +static inline void wcd_clsh_set_flyback_current(struct snd_soc_component *comp, + int mode) +{ + + snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF, + WCD9XXX_RX_BIAS_FLYB_VPOS_5_UA_MASK, 0x0A); + snd_soc_component_update_bits(comp, WCD9XXX_RX_BIAS_FLYB_BUFF, + WCD9XXX_RX_BIAS_FLYB_VNEG_5_UA_MASK, 0x0A); + /* Sleep needed to avoid click and pop as per HW requirement */ + usleep_range(100, 110); +} + +static inline void wcd_clsh_set_buck_regulator_mode(struct snd_soc_component *comp, + int mode) +{ + if (mode == CLS_AB) + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK, + WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_AB); + else + snd_soc_component_update_bits(comp, WCD9XXX_A_ANA_RX_SUPPLIES, + WCD9XXX_A_ANA_RX_REGULATOR_MODE_MASK, + WCD9XXX_A_ANA_RX_REGULATOR_MODE_CLS_H); +} + +static inline void wcd_clsh_v3_set_buck_regulator_mode(struct snd_soc_component *component, + int mode) +{ + snd_soc_component_update_bits(component, WCD9XXX_ANA_RX_SUPPLIES, + 0x02, 0x00); +} + +static inline void wcd_clsh_v3_set_flyback_mode(struct snd_soc_component *component, + int mode) +{ + if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI || + mode == CLS_AB_HIFI || mode == CLS_AB_LOHIFI) { + snd_soc_component_update_bits(component, + WCD9XXX_ANA_RX_SUPPLIES, + 0x04, 0x04); + snd_soc_component_update_bits(component, + WCD9XXX_FLYBACK_VNEG_CTRL_4, + 0xF0, 0x80); + } else { + snd_soc_component_update_bits(component, + WCD9XXX_ANA_RX_SUPPLIES, + 0x04, 0x00); /* set to Default */ + snd_soc_component_update_bits(component, + WCD9XXX_FLYBACK_VNEG_CTRL_4, + 0xF0, 0x70); + } +} + +static inline void wcd_clsh_v3_force_iq_ctl(struct snd_soc_component *component, + int mode, bool enable) +{ + if (enable) { + snd_soc_component_update_bits(component, + WCD9XXX_FLYBACK_VNEGDAC_CTRL_2, + 0xE0, 0xA0); + /* 100usec delay is needed as per HW requirement */ + usleep_range(100, 110); + snd_soc_component_update_bits(component, + WCD9XXX_CLASSH_MODE_3, + 0x02, 0x02); + snd_soc_component_update_bits(component, + WCD9XXX_CLASSH_MODE_2, + 0xFF, 0x1C); + if (mode == CLS_H_LOHIFI || mode == CLS_AB_LOHIFI) { + snd_soc_component_update_bits(component, + WCD9XXX_HPH_NEW_INT_PA_MISC2, + 0x20, 0x20); + snd_soc_component_update_bits(component, + WCD9XXX_RX_BIAS_HPH_LOWPOWER, + 0xF0, 0xC0); + snd_soc_component_update_bits(component, + WCD9XXX_HPH_PA_CTL1, + 0x0E, 0x02); + } + } else { + snd_soc_component_update_bits(component, + WCD9XXX_HPH_NEW_INT_PA_MISC2, + 0x20, 0x00); + snd_soc_component_update_bits(component, + WCD9XXX_RX_BIAS_HPH_LOWPOWER, + 0xF0, 0x80); + snd_soc_component_update_bits(component, + WCD9XXX_HPH_PA_CTL1, + 0x0E, 0x06); + } +} + +static inline void wcd_clsh_v3_flyback_ctrl(struct snd_soc_component *component, + struct wcd_clsh_ctrl *ctrl, + int mode, + bool enable) +{ + /* enable/disable flyback */ + if ((enable && (++ctrl->flyback_users == 1)) || + (!enable && (--ctrl->flyback_users == 0))) { + snd_soc_component_update_bits(component, + WCD9XXX_FLYBACK_VNEG_CTRL_1, + 0xE0, 0xE0); + snd_soc_component_update_bits(component, + WCD9XXX_ANA_RX_SUPPLIES, + (1 << 6), (enable << 6)); + /* + * 100us sleep is required after flyback enable/disable + * as per HW requirement + */ + usleep_range(100, 110); + snd_soc_component_update_bits(component, + WCD9XXX_FLYBACK_VNEGDAC_CTRL_2, + 0xE0, 0xE0); + /* 500usec delay is needed as per HW requirement */ + usleep_range(500, 500 + WCD_USLEEP_RANGE); + } +} + +static inline void wcd_clsh_v3_set_flyback_current(struct snd_soc_component *component, + int mode) +{ + snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF, + 0x0F, 0x0A); + snd_soc_component_update_bits(component, WCD9XXX_V3_RX_BIAS_FLYB_BUFF, + 0xF0, 0xA0); + /* Sleep needed to avoid click and pop as per HW requirement */ + usleep_range(100, 110); +} + +static inline void wcd_clsh_v3_state_aux(struct wcd_clsh_ctrl *ctrl, int req_state, + bool is_enable, int mode) +{ + struct snd_soc_component *component = ctrl->comp; + + if (is_enable) { + wcd_clsh_v3_set_buck_mode(component, mode); + wcd_clsh_v3_set_flyback_mode(component, mode); + wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); + wcd_clsh_v3_set_flyback_current(component, mode); + wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); + } else { + wcd_clsh_v3_buck_ctrl(component, ctrl, mode, false); + wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, false); + wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); + wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); + } +} + +static inline void wcd_clsh_state_lo(struct wcd_clsh_ctrl *ctrl, int req_state, + bool is_enable, int mode) +{ + struct snd_soc_component *comp = ctrl->comp; + + if (mode != CLS_AB) { + dev_err(comp->dev, "%s: LO cannot be in this mode: %d\n", + __func__, mode); + return; + } + + if (is_enable) { + wcd_clsh_set_buck_regulator_mode(comp, mode); + wcd_clsh_set_buck_mode(comp, mode); + wcd_clsh_set_flyback_mode(comp, mode); + wcd_clsh_flyback_ctrl(ctrl, mode, true); + wcd_clsh_set_flyback_current(comp, mode); + wcd_clsh_buck_ctrl(ctrl, mode, true); + } else { + wcd_clsh_buck_ctrl(ctrl, mode, false); + wcd_clsh_flyback_ctrl(ctrl, mode, false); + wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); + wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); + wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL); + } +} + +static inline void wcd_clsh_v3_state_hph_r(struct wcd_clsh_ctrl *ctrl, + int req_state, + bool is_enable, int mode) +{ + struct snd_soc_component *component = ctrl->comp; + + if (mode == CLS_H_NORMAL) { + dev_dbg(component->dev, "%s: Normal mode not applicable for hph_r\n", + __func__); + return; + } + + if (is_enable) { + wcd_clsh_v3_set_buck_regulator_mode(component, mode); + wcd_clsh_v3_set_flyback_mode(component, mode); + wcd_clsh_v3_force_iq_ctl(component, mode, true); + wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); + wcd_clsh_v3_set_flyback_current(component, mode); + wcd_clsh_v3_set_buck_mode(component, mode); + wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); + wcd_clsh_v3_set_hph_mode(component, mode); + } else { + wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL); + + /* buck and flyback set to default mode and disable */ + wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false); + wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false); + wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false); + wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); + wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); + } +} + +static inline void wcd_clsh_state_hph_r(struct wcd_clsh_ctrl *ctrl, + int req_state, bool is_enable, int mode) +{ + struct snd_soc_component *comp = ctrl->comp; + + if (mode == CLS_H_NORMAL) { + dev_err(comp->dev, "%s: Normal mode not applicable for hph_r\n", + __func__); + return; + } + + if (is_enable) { + if (mode != CLS_AB) { + wcd_enable_clsh_block(ctrl, true); + /* + * These K1 values depend on the Headphone Impedance + * For now it is assumed to be 16 ohm + */ + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_CLSH_K1_MSB, + WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK, + 0x00); + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_CLSH_K1_LSB, + WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK, + 0xC0); + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_RX2_RX_PATH_CFG0, + WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, + WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE); + } + wcd_clsh_set_buck_regulator_mode(comp, mode); + wcd_clsh_set_flyback_mode(comp, mode); + wcd_clsh_flyback_ctrl(ctrl, mode, true); + wcd_clsh_set_flyback_current(comp, mode); + wcd_clsh_set_buck_mode(comp, mode); + wcd_clsh_buck_ctrl(ctrl, mode, true); + wcd_clsh_v2_set_hph_mode(comp, mode); + wcd_clsh_set_gain_path(ctrl, mode); + } else { + wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL); + + if (mode != CLS_AB) { + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_RX2_RX_PATH_CFG0, + WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, + WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE); + wcd_enable_clsh_block(ctrl, false); + } + /* buck and flyback set to default mode and disable */ + wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false); + wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false); + wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); + wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); + wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL); + } +} + +static inline void wcd_clsh_v3_state_hph_l(struct wcd_clsh_ctrl *ctrl, + int req_state, bool is_enable, + int mode) +{ + struct snd_soc_component *component = ctrl->comp; + + if (mode == CLS_H_NORMAL) { + dev_dbg(component->dev, "%s: Normal mode not applicable for hph_l\n", + __func__); + return; + } + + if (is_enable) { + wcd_clsh_v3_set_buck_regulator_mode(component, mode); + wcd_clsh_v3_set_flyback_mode(component, mode); + wcd_clsh_v3_force_iq_ctl(component, mode, true); + wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); + wcd_clsh_v3_set_flyback_current(component, mode); + wcd_clsh_v3_set_buck_mode(component, mode); + wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); + wcd_clsh_v3_set_hph_mode(component, mode); + } else { + wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL); + + /* set buck and flyback to Default Mode */ + wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false); + wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false); + wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false); + wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); + wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); + } +} + +static inline void wcd_clsh_state_hph_l(struct wcd_clsh_ctrl *ctrl, + int req_state, bool is_enable, int mode) +{ + struct snd_soc_component *comp = ctrl->comp; + + if (mode == CLS_H_NORMAL) { + dev_err(comp->dev, "%s: Normal mode not applicable for hph_l\n", + __func__); + return; + } + + if (is_enable) { + if (mode != CLS_AB) { + wcd_enable_clsh_block(ctrl, true); + /* + * These K1 values depend on the Headphone Impedance + * For now it is assumed to be 16 ohm + */ + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_CLSH_K1_MSB, + WCD9XXX_A_CDC_CLSH_K1_MSB_COEF_MASK, + 0x00); + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_CLSH_K1_LSB, + WCD9XXX_A_CDC_CLSH_K1_LSB_COEF_MASK, + 0xC0); + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_RX1_RX_PATH_CFG0, + WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, + WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE); + } + wcd_clsh_set_buck_regulator_mode(comp, mode); + wcd_clsh_set_flyback_mode(comp, mode); + wcd_clsh_flyback_ctrl(ctrl, mode, true); + wcd_clsh_set_flyback_current(comp, mode); + wcd_clsh_set_buck_mode(comp, mode); + wcd_clsh_buck_ctrl(ctrl, mode, true); + wcd_clsh_v2_set_hph_mode(comp, mode); + wcd_clsh_set_gain_path(ctrl, mode); + } else { + wcd_clsh_v2_set_hph_mode(comp, CLS_H_NORMAL); + + if (mode != CLS_AB) { + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_RX1_RX_PATH_CFG0, + WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, + WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE); + wcd_enable_clsh_block(ctrl, false); + } + /* set buck and flyback to Default Mode */ + wcd_clsh_buck_ctrl(ctrl, CLS_H_NORMAL, false); + wcd_clsh_flyback_ctrl(ctrl, CLS_H_NORMAL, false); + wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); + wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); + wcd_clsh_set_buck_regulator_mode(comp, CLS_H_NORMAL); + } +} + +static inline void wcd_clsh_v3_state_ear(struct wcd_clsh_ctrl *ctrl, + int req_state, bool is_enable, + int mode) +{ + struct snd_soc_component *component = ctrl->comp; + + if (is_enable) { + wcd_clsh_v3_set_buck_regulator_mode(component, mode); + wcd_clsh_v3_set_flyback_mode(component, mode); + wcd_clsh_v3_force_iq_ctl(component, mode, true); + wcd_clsh_v3_flyback_ctrl(component, ctrl, mode, true); + wcd_clsh_v3_set_flyback_current(component, mode); + wcd_clsh_v3_set_buck_mode(component, mode); + wcd_clsh_v3_buck_ctrl(component, ctrl, mode, true); + wcd_clsh_v3_set_hph_mode(component, mode); + } else { + wcd_clsh_v3_set_hph_mode(component, CLS_H_NORMAL); + + /* set buck and flyback to Default Mode */ + wcd_clsh_v3_flyback_ctrl(component, ctrl, CLS_H_NORMAL, false); + wcd_clsh_v3_buck_ctrl(component, ctrl, CLS_H_NORMAL, false); + wcd_clsh_v3_force_iq_ctl(component, CLS_H_NORMAL, false); + wcd_clsh_v3_set_flyback_mode(component, CLS_H_NORMAL); + wcd_clsh_v3_set_buck_mode(component, CLS_H_NORMAL); + } +} + +static inline void wcd_clsh_state_ear(struct wcd_clsh_ctrl *ctrl, int req_state, + bool is_enable, int mode) +{ + struct snd_soc_component *comp = ctrl->comp; + + if (mode != CLS_H_NORMAL) { + dev_err(comp->dev, "%s: mode: %d cannot be used for EAR\n", + __func__, mode); + return; + } + + if (is_enable) { + wcd_enable_clsh_block(ctrl, true); + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_RX0_RX_PATH_CFG0, + WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, + WCD9XXX_A_CDC_RX_PATH_CLSH_ENABLE); + wcd_clsh_set_buck_mode(comp, mode); + wcd_clsh_set_flyback_mode(comp, mode); + wcd_clsh_flyback_ctrl(ctrl, mode, true); + wcd_clsh_set_flyback_current(comp, mode); + wcd_clsh_buck_ctrl(ctrl, mode, true); + } else { + snd_soc_component_update_bits(comp, + WCD9XXX_A_CDC_RX0_RX_PATH_CFG0, + WCD9XXX_A_CDC_RX_PATH_CLSH_EN_MASK, + WCD9XXX_A_CDC_RX_PATH_CLSH_DISABLE); + wcd_enable_clsh_block(ctrl, false); + wcd_clsh_buck_ctrl(ctrl, mode, false); + wcd_clsh_flyback_ctrl(ctrl, mode, false); + wcd_clsh_set_flyback_mode(comp, CLS_H_NORMAL); + wcd_clsh_set_buck_mode(comp, CLS_H_NORMAL); + } +} + +static inline int _wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, + int req_state, bool is_enable, + int mode) +{ + switch (req_state) { + case WCD_CLSH_STATE_EAR: + if (ctrl->codec_version >= WCD937X) + wcd_clsh_v3_state_ear(ctrl, req_state, is_enable, mode); + else + wcd_clsh_state_ear(ctrl, req_state, is_enable, mode); + break; + case WCD_CLSH_STATE_HPHL: + if (ctrl->codec_version >= WCD937X) + wcd_clsh_v3_state_hph_l(ctrl, req_state, is_enable, mode); + else + wcd_clsh_state_hph_l(ctrl, req_state, is_enable, mode); + break; + case WCD_CLSH_STATE_HPHR: + if (ctrl->codec_version >= WCD937X) + wcd_clsh_v3_state_hph_r(ctrl, req_state, is_enable, mode); + else + wcd_clsh_state_hph_r(ctrl, req_state, is_enable, mode); + break; + case WCD_CLSH_STATE_LO: + if (ctrl->codec_version < WCD937X) + wcd_clsh_state_lo(ctrl, req_state, is_enable, mode); + break; + case WCD_CLSH_STATE_AUX: + if (ctrl->codec_version >= WCD937X) + wcd_clsh_v3_state_aux(ctrl, req_state, is_enable, mode); + break; + default: + break; + } + + return 0; +} + +/* + * Function: wcd_clsh_is_state_valid + * Params: state + * Description: + * Provides information on valid states of Class H configuration + */ +static inline bool wcd_clsh_is_state_valid(int state) +{ + switch (state) { + case WCD_CLSH_STATE_IDLE: + case WCD_CLSH_STATE_EAR: + case WCD_CLSH_STATE_HPHL: + case WCD_CLSH_STATE_HPHR: + case WCD_CLSH_STATE_LO: + case WCD_CLSH_STATE_AUX: + return true; + default: + return false; + }; +} + +/* + * Function: wcd_clsh_fsm + * Params: ctrl, req_state, req_type, clsh_event + * Description: + * This function handles PRE DAC and POST DAC conditions of different devices + * and updates class H configuration of different combination of devices + * based on validity of their states. ctrl will contain current + * class h state information + */ +static inline int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl, + enum wcd_clsh_event clsh_event, + int nstate, + enum wcd_clsh_mode mode) +{ + struct snd_soc_component *comp = ctrl->comp; + + if (nstate == ctrl->state) + return 0; + + if (!wcd_clsh_is_state_valid(nstate)) { + dev_err(comp->dev, "Class-H not a valid new state:\n"); + return -EINVAL; + } + + switch (clsh_event) { + case WCD_CLSH_EVENT_PRE_DAC: + _wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_ENABLE, mode); + break; + case WCD_CLSH_EVENT_POST_PA: + _wcd_clsh_ctrl_set_state(ctrl, nstate, CLSH_REQ_DISABLE, mode); + break; + } + + ctrl->state = nstate; + ctrl->mode = mode; + + return 0; +} + +static inline int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl) +{ + return ctrl->state; +} + +static inline struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(struct snd_soc_component *comp, + int version) +{ + struct wcd_clsh_ctrl *ctrl; + + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return ERR_PTR(-ENOMEM); + + ctrl->state = WCD_CLSH_STATE_IDLE; + ctrl->comp = comp; + ctrl->codec_version = version; + + return ctrl; +} + +static inline void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl) +{ + kfree(ctrl); +} #endif /* _WCD_CLSH_V2_H_ */ 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id c13-20020a170903234d00b0016da027a727si8254436plh.116.2022.11.19.15.06.33; Sat, 19 Nov 2022 15:06:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=euSIxToF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231666AbiKSXGE (ORCPT + 99 others); Sat, 19 Nov 2022 18:06:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234334AbiKSXF7 (ORCPT ); Sat, 19 Nov 2022 18:05:59 -0500 X-Greylist: delayed 64 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sat, 19 Nov 2022 15:05:57 PST Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C5B819C35; Sat, 19 Nov 2022 15:05:57 -0800 (PST) Date: Sat, 19 Nov 2022 23:05:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899155; x=1669158355; bh=os6z3ba01+YXEoGx1b8Zwzyato7B2D5Y3WgXf8vG8a0=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=euSIxToFxm3b5kV2z4QSpdEhp/M2qP87Z7/nF7qW0RbkUB18Qr5BvHy9d0Y9XHjDb 3LrhPo2OmnhdnRrmFSIXxR+F0yBxPHvFeKwqUrQ4GLQcjDpoyiFYbhMwfDBeDMHGk7 /TtkNpy4nCP8L7b/5h2XeR/9keyCzOnIpJcerLKDYt8JTnrwtBgBSkMXeRs2Mkd7J/ KJDAzsJFsa/7pqnoPueRjCve9rg/EhL6hOScGKWZ4Xegm1l88FzlQ2a5L7iGoCySty QmeihC2zQKpjMJH9K3knmyWWs4OCWkELkv8M/vWege356kVN4dFtEs3Mog7LsPQ02J Sbt7yWJq9brVA== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/18] mfd: rsmu: fix mixed module-builtin object Message-ID: <20221119225650.1044591-6-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967654540622115?= X-GMAIL-MSGID: =?utf-8?q?1749967654540622115?= From: Masahiro Yamada With CONFIG_MFD_RSMU_I2C=m and CONFIG_MFD_RSMU_SPI=y (or vice versa), rsmu_core.o is linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Split rsmu-core into a separate module. Signed-off-by: Masahiro Yamada Reviewed-and-tested-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- drivers/mfd/Kconfig | 8 ++++++-- drivers/mfd/Makefile | 6 ++++-- drivers/mfd/rsmu_core.c | 3 +++ 3 files changed, 13 insertions(+), 4 deletions(-) -- 2.38.1 diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 8b93856de432..f52efa1a968d 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2232,10 +2232,14 @@ config MFD_INTEL_M10_BMC additional drivers must be enabled in order to use the functionality of the device. +config MFD_RSMU_CORE + tristate + select MFD_CORE + config MFD_RSMU_I2C tristate "Renesas Synchronization Management Unit with I2C" depends on I2C && OF - select MFD_CORE + select MFD_RSMU_CORE select REGMAP_I2C help Support for the Renesas Synchronization Management Unit, such as @@ -2249,7 +2253,7 @@ config MFD_RSMU_I2C config MFD_RSMU_SPI tristate "Renesas Synchronization Management Unit with SPI" depends on SPI && OF - select MFD_CORE + select MFD_RSMU_CORE select REGMAP_SPI help Support for the Renesas Synchronization Management Unit, such as diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 7ed3ef4a698c..d40d6619bacd 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -276,7 +276,9 @@ obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o -rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o -rsmu-spi-objs := rsmu_core.o rsmu_spi.o +rsmu-core-objs := rsmu_core.o +rsmu-i2c-objs := rsmu_i2c.o +rsmu-spi-objs := rsmu_spi.o +obj-$(CONFIG_MFD_RSMU_CORE) += rsmu-core.o obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o diff --git a/drivers/mfd/rsmu_core.c b/drivers/mfd/rsmu_core.c index 29437fd0bd5b..5bf1e23a47e5 100644 --- a/drivers/mfd/rsmu_core.c +++ b/drivers/mfd/rsmu_core.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. */ +#include #include #include #include @@ -78,11 +79,13 @@ int rsmu_core_init(struct rsmu_ddata *rsmu) return ret; } +EXPORT_SYMBOL_GPL(rsmu_core_init); void rsmu_core_exit(struct rsmu_ddata *rsmu) { mutex_destroy(&rsmu->lock); } +EXPORT_SYMBOL_GPL(rsmu_core_exit); MODULE_DESCRIPTION("Renesas SMU core driver"); MODULE_LICENSE("GPL"); From patchwork Sat Nov 19 23:06:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23344 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp897581wrr; Sat, 19 Nov 2022 15:07:06 -0800 (PST) X-Google-Smtp-Source: AA0mqf6uS0RgjOFPNbpvby5FjilAa3PW3WsextTkEwcLPYCvefK7HyugUpi7168RAqZqLKpcqPzO X-Received: by 2002:a17:902:c7d1:b0:179:b756:5b60 with SMTP id r17-20020a170902c7d100b00179b7565b60mr5638427pla.22.1668899225900; Sat, 19 Nov 2022 15:07:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899225; cv=none; d=google.com; s=arc-20160816; b=oeGbiJW95u4ekOiYJ3YN6U6WT8svYKbEvM3sWfCWxfR69Og8IAnY8OASK5caH1SCo3 y/ijzzMZ+puJR8lxan8mj+ASYTEOQJ3Xtv5WIlEDasYpC0Ge5mslWsdGIVZaFh8gYGb4 CusULQzvdu1Tv+w86kqIgrx6i0GGi9YNBrQPKMHp5UnDGeodVxh8Xak9fe8HXAgMfjs0 NU0KVGFLfB7NDEXsdMl3c6xWro/AABz5KA2Rlla18Kr7e5evRxuj5d18fNR0gE7b7qNL E4vWNe1HPmhF2KkbLIm6CbiPHbzcK+1b0EAUsoU8KqT+nayUqRRyjSUvt9XtSPKXZYk8 ZOAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :feedback-id:references:in-reply-to:message-id:subject:cc:from:to :dkim-signature:date; bh=aAU7Nf2uHGDsr5PzJ0A6nAFZICy8pn9hVi79vE0ftbI=; b=DxWERdsGRZlBKrEecb9R1sDdL9hXzmeA8YMRb2qgx43TLeNAFskdPztRYb/LukekMq 1QOOnSJqmWwEN7Q2ffo8jSLXTdng0yVeBTB6ubYvLiheF9puo1gOL7oyQkWvi8tAhgXd 6/dyf79ZDytpKD4w/6K0mh8oKO+UzI43W5Pr2pO+1Mo/k+3BcgQ/eQ6V0Ix9cGgqvQrV pG9zLe/Qz5elmqXEYtKD29Aba05CxZEme5SlnvbZVfpFlXma6VzCMF9o0c/fMFB8Gn8F 51dqvjQSTzfOCyOa3a9AqZckP/ABCSkAl8EYXArfEsQK3KZJJegtM0JeDMrf+JVXd6hs 6d6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=b6avCPJr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l2-20020a17090a660200b0020d5dfb9d69si6370825pjj.187.2022.11.19.15.06.52; Sat, 19 Nov 2022 15:07:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=b6avCPJr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234976AbiKSXGe (ORCPT + 99 others); Sat, 19 Nov 2022 18:06:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235116AbiKSXG1 (ORCPT ); Sat, 19 Nov 2022 18:06:27 -0500 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFB321A07B; Sat, 19 Nov 2022 15:06:25 -0800 (PST) Date: Sat, 19 Nov 2022 23:06:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899184; x=1669158384; bh=aAU7Nf2uHGDsr5PzJ0A6nAFZICy8pn9hVi79vE0ftbI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=b6avCPJr+q/icECeZWKkziIPgEI2mvFKP4d8mR7bPYlphqYYONYBUxnWKpHcTX+ON v7O/4bjbo6hISfOzqY9xstmLWjblx3TWlh2tguanWBNcu5wjzGaXJlLl5A9+uvM1OC IUUwa6yWf4SEiYPxlQLWEcRof6N4AoZNAlu+dPSgj40ioeLIM2GFm1Uo7J5p0oii7m aPNSRGweRg3o+SBTTPf7w28WX8jqcW08QAZqYQD6Fr5BMN4z/djBnYlPUCPMDrVWcO 40FVIf3lylmBnVDl2Vj3EkqDAlhpDqiK+do0ypeXcjsvDlo1R5O1bs0EArXQ6EnzPx M5Uq8fjD5WHAQ== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/18] mfd: rsmu: turn rsmu-{core,i2c,spi} into single-object modules Message-ID: <20221119225650.1044591-7-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967674451245660?= X-GMAIL-MSGID: =?utf-8?q?1749967674451245660?= From: Masahiro Yamada With the previous fix, these modules are built from a single C file. Rename the source files so they match the module names. Signed-off-by: Masahiro Yamada Reviewed-and-tested-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- drivers/mfd/Makefile | 3 --- drivers/mfd/{rsmu_core.c => rsmu-core.c} | 0 drivers/mfd/{rsmu_i2c.c => rsmu-i2c.c} | 0 drivers/mfd/{rsmu_spi.c => rsmu-spi.c} | 0 4 files changed, 3 deletions(-) rename drivers/mfd/{rsmu_core.c => rsmu-core.c} (100%) rename drivers/mfd/{rsmu_i2c.c => rsmu-i2c.c} (100%) rename drivers/mfd/{rsmu_spi.c => rsmu-spi.c} (100%) -- 2.38.1 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index d40d6619bacd..cd436c50c5c0 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -276,9 +276,6 @@ obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o -rsmu-core-objs := rsmu_core.o -rsmu-i2c-objs := rsmu_i2c.o -rsmu-spi-objs := rsmu_spi.o obj-$(CONFIG_MFD_RSMU_CORE) += rsmu-core.o obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o diff --git a/drivers/mfd/rsmu_core.c b/drivers/mfd/rsmu-core.c similarity index 100% rename from drivers/mfd/rsmu_core.c rename to drivers/mfd/rsmu-core.c diff --git a/drivers/mfd/rsmu_i2c.c b/drivers/mfd/rsmu-i2c.c similarity index 100% rename from drivers/mfd/rsmu_i2c.c rename to drivers/mfd/rsmu-i2c.c diff --git a/drivers/mfd/rsmu_spi.c b/drivers/mfd/rsmu-spi.c similarity index 100% rename from drivers/mfd/rsmu_spi.c rename to drivers/mfd/rsmu-spi.c From patchwork Sat Nov 19 23:06:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23345 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp897741wrr; Sat, 19 Nov 2022 15:07:33 -0800 (PST) X-Google-Smtp-Source: AA0mqf6HFmo9Nbib3Sw60CZIiSpPU7EHsxTcxkPFEQsn7KUngP351GgEwyXDgOfpdpCj1LI7oVwA X-Received: by 2002:a17:903:4051:b0:170:f343:ba14 with SMTP id n17-20020a170903405100b00170f343ba14mr5569316pla.70.1668899253246; Sat, 19 Nov 2022 15:07:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899253; cv=none; d=google.com; s=arc-20160816; b=N6KE6yOTL9uJW6oe1wDLm2b0/YEPe5jnGhMIJyaN1zfynY6+DA8E+wMUaO7fuwUS4J 2mpMW649Cv4WvDeYYEgbkh3AUdZWv4qOIh9g5j0IS+MuNjciIuyD9cXo0kl+Hv3Nr0uo ShKDuLkK50WF+xfnquMQxeXUX4l8IfSEmXrvWPWtrqbGXtweemwwH5xGVxx0e12jQY0J IiCZTuZLXUU/GGIVxgCAnQj5C3Y0BP+73dUElrdRnZ4R/lRcxf+PS5EKlKLz2i2broqK QcID/Mk0EcycVtWP/PKZUdiQ8G53BDQufMxbfN7+O62M/xioO8xWIl/m/0AKKvwyNHU5 /+4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :feedback-id:references:in-reply-to:message-id:subject:cc:from:to :dkim-signature:date; bh=lbZKtCBwWfNwOVR25jTIi8OG7VvrK+r2B3/eBoo3gB8=; b=Hv6mAhI659rkWSfE2QpK1+69OqSCYwsgD8efFrjWpVbAdbTAGpgYa0nEyDz3oF5YH7 CU3k1/anEs6sXdaqNIG0/RicdX3KTy/gbQTukp/S+obWXOe6GkOAECByxTCsBCigKhio RnN1DKz1ByGxpWBBRp/wZ6i7WHANZlpd2wlc+Cna5LnLHzANqTmUudvmO/TcMCDyEFXQ AZlY6jHFNaGX/MdkZFPmPALMBLnPI0sYmQ2Wk3t+sJUO2mUeNYTRrq8t8CQWgpVhKbMy w4d6OW1FHSxz7nPdJSw7Ut44jOdW58XwLI6gYEqLbl9GCNiFEz9z/SqzyfaO42oArK5B bsBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=UHAhvoKA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 23-20020a630117000000b004573e877892si7518573pgb.769.2022.11.19.15.07.20; Sat, 19 Nov 2022 15:07:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=UHAhvoKA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235059AbiKSXGu (ORCPT + 99 others); Sat, 19 Nov 2022 18:06:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235051AbiKSXGq (ORCPT ); Sat, 19 Nov 2022 18:06:46 -0500 X-Greylist: delayed 158 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Sat, 19 Nov 2022 15:06:43 PST Received: from mail-40133.protonmail.ch (mail-40133.protonmail.ch [185.70.40.133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05EBA1A06D; Sat, 19 Nov 2022 15:06:42 -0800 (PST) Date: Sat, 19 Nov 2022 23:06:34 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899200; x=1669158400; bh=lbZKtCBwWfNwOVR25jTIi8OG7VvrK+r2B3/eBoo3gB8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=UHAhvoKATaZJKk/Jkr+I3eF8oqnHbm041ftOuuQ7P7qWXfP65nuSsiNoJSM3ANlWs Y81h32ZfbrGt/tSCNRToaEw2ZCtss+IwPofc/Kisbobyb7Texrd3SU7Xt4mUdi0oZk hiISov9f+QCjpEFSZoCR3F+G/pFxBKN3LevLHbnl3bFy7Dzd63GJR1Zrom04XO/zKZ /itC7lfh7mW0JBwJDAJ3FyORWuTFrdj0lhazX6Pt/2ajsa/ch3s8z5/7eIcFPlWx/C MOWeKPSNaJuZj3MEa/ylhc8WvrrCWXa7ixQJOG/VDxV78+nPe8zgNRxII3OrOTuCrU /DDELRdCisO+g== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/18] net: liquidio: fix mixed module-builtin object Message-ID: <20221119225650.1044591-8-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967703047068023?= X-GMAIL-MSGID: =?utf-8?q?1749967703047068023?= From: Masahiro Yamada With CONFIG_LIQUIDIO=m and CONFIG_LIQUIDIO_VF=y (or vice versa), $(common-objs) are linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Introduce the new module, liquidio-core, to provide the common functions to liquidio and liquidio-vf. [ alobakin: added export of lio_get_state_string() ] Signed-off-by: Masahiro Yamada Reviewed-and-tested-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- drivers/net/ethernet/cavium/Kconfig | 5 ++++ drivers/net/ethernet/cavium/liquidio/Makefile | 4 +++- .../cavium/liquidio/cn23xx_pf_device.c | 4 ++++ .../cavium/liquidio/cn23xx_vf_device.c | 3 +++ .../ethernet/cavium/liquidio/cn66xx_device.c | 1 + .../ethernet/cavium/liquidio/cn68xx_device.c | 1 + .../net/ethernet/cavium/liquidio/lio_core.c | 16 +++++++++++++ .../ethernet/cavium/liquidio/lio_ethtool.c | 1 + .../ethernet/cavium/liquidio/octeon_device.c | 24 +++++++++++++++++++ .../ethernet/cavium/liquidio/octeon_droq.c | 4 ++++ .../ethernet/cavium/liquidio/octeon_mem_ops.c | 5 ++++ .../net/ethernet/cavium/liquidio/octeon_nic.c | 3 +++ .../cavium/liquidio/request_manager.c | 14 +++++++++++ .../cavium/liquidio/response_manager.c | 3 +++ 14 files changed, 87 insertions(+), 1 deletion(-) -- 2.38.1 diff --git a/drivers/net/ethernet/cavium/Kconfig b/drivers/net/ethernet/cavium/Kconfig index 1c76c95b0b27..ca742cc146d7 100644 --- a/drivers/net/ethernet/cavium/Kconfig +++ b/drivers/net/ethernet/cavium/Kconfig @@ -62,6 +62,9 @@ config CAVIUM_PTP Precision Time Protocol or other purposes. Timestamps can be used in BGX, TNS, GTI, and NIC blocks. +config LIQUIDIO_CORE + tristate + config LIQUIDIO tristate "Cavium LiquidIO support" depends on 64BIT && PCI @@ -69,6 +72,7 @@ config LIQUIDIO depends on PTP_1588_CLOCK_OPTIONAL select FW_LOADER select LIBCRC32C + select LIQUIDIO_CORE select NET_DEVLINK help This driver supports Cavium LiquidIO Intelligent Server Adapters @@ -92,6 +96,7 @@ config LIQUIDIO_VF tristate "Cavium LiquidIO VF support" depends on 64BIT && PCI_MSI depends on PTP_1588_CLOCK_OPTIONAL + select LIQUIDIO_CORE help This driver supports Cavium LiquidIO Intelligent Server Adapter based on CN23XX chips. diff --git a/drivers/net/ethernet/cavium/liquidio/Makefile b/drivers/net/ethernet/cavium/liquidio/Makefile index bc9937502043..e5407f9c3912 100644 --- a/drivers/net/ethernet/cavium/liquidio/Makefile +++ b/drivers/net/ethernet/cavium/liquidio/Makefile @@ -3,7 +3,9 @@ # Cavium Liquidio ethernet device driver # -common-objs := lio_ethtool.o \ +obj-$(CONFIG_LIQUIDIO_CORE) += liquidio-core.o +liquidio-core-y := \ + lio_ethtool.o \ lio_core.o \ request_manager.o \ response_manager.o \ diff --git a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c index 9ed3d1ab2ca5..54b280114481 100644 --- a/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c +++ b/drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c @@ -1377,6 +1377,7 @@ int setup_cn23xx_octeon_pf_device(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(setup_cn23xx_octeon_pf_device); int validate_cn23xx_pf_config_info(struct octeon_device *oct, struct octeon_config *conf23xx) @@ -1435,6 +1436,7 @@ int cn23xx_fw_loaded(struct octeon_device *oct) val = octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2); return (val >> SCR2_BIT_FW_LOADED) & 1ULL; } +EXPORT_SYMBOL_GPL(cn23xx_fw_loaded); void cn23xx_tell_vf_its_macaddr_changed(struct octeon_device *oct, int vfidx, u8 *mac) @@ -1456,6 +1458,7 @@ void cn23xx_tell_vf_its_macaddr_changed(struct octeon_device *oct, int vfidx, octeon_mbox_write(oct, &mbox_cmd); } } +EXPORT_SYMBOL_GPL(cn23xx_tell_vf_its_macaddr_changed); static void cn23xx_get_vf_stats_callback(struct octeon_device *oct, @@ -1510,3 +1513,4 @@ int cn23xx_get_vf_stats(struct octeon_device *oct, int vfidx, return 0; } +EXPORT_SYMBOL_GPL(cn23xx_get_vf_stats); diff --git a/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c b/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c index fda49404968c..ef4667b7e17f 100644 --- a/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c +++ b/drivers/net/ethernet/cavium/liquidio/cn23xx_vf_device.c @@ -386,6 +386,7 @@ void cn23xx_vf_ask_pf_to_do_flr(struct octeon_device *oct) octeon_mbox_write(oct, &mbox_cmd); } +EXPORT_SYMBOL_GPL(cn23xx_vf_ask_pf_to_do_flr); static void octeon_pfvf_hs_callback(struct octeon_device *oct, struct octeon_mbox_cmd *cmd, @@ -468,6 +469,7 @@ int cn23xx_octeon_pfvf_handshake(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(cn23xx_octeon_pfvf_handshake); static void cn23xx_handle_vf_mbox_intr(struct octeon_ioq_vector *ioq_vector) { @@ -680,3 +682,4 @@ int cn23xx_setup_octeon_vf_device(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(cn23xx_setup_octeon_vf_device); diff --git a/drivers/net/ethernet/cavium/liquidio/cn66xx_device.c b/drivers/net/ethernet/cavium/liquidio/cn66xx_device.c index 39643be8c30a..93fccfec288d 100644 --- a/drivers/net/ethernet/cavium/liquidio/cn66xx_device.c +++ b/drivers/net/ethernet/cavium/liquidio/cn66xx_device.c @@ -697,6 +697,7 @@ int lio_setup_cn66xx_octeon_device(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(lio_setup_cn66xx_octeon_device); int lio_validate_cn6xxx_config_info(struct octeon_device *oct, struct octeon_config *conf6xxx) diff --git a/drivers/net/ethernet/cavium/liquidio/cn68xx_device.c b/drivers/net/ethernet/cavium/liquidio/cn68xx_device.c index 30254e4cf70f..b5103def3761 100644 --- a/drivers/net/ethernet/cavium/liquidio/cn68xx_device.c +++ b/drivers/net/ethernet/cavium/liquidio/cn68xx_device.c @@ -181,3 +181,4 @@ int lio_setup_cn68xx_octeon_device(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(lio_setup_cn68xx_octeon_device); diff --git a/drivers/net/ethernet/cavium/liquidio/lio_core.c b/drivers/net/ethernet/cavium/liquidio/lio_core.c index 882b2be06ea0..9cc6303c82ff 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_core.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_core.c @@ -26,6 +26,9 @@ #include "octeon_main.h" #include "octeon_network.h" +MODULE_AUTHOR("Cavium Networks, "); +MODULE_LICENSE("GPL"); + /* OOM task polling interval */ #define LIO_OOM_POLL_INTERVAL_MS 250 @@ -71,6 +74,7 @@ void lio_delete_glists(struct lio *lio) kfree(lio->glist); lio->glist = NULL; } +EXPORT_SYMBOL_GPL(lio_delete_glists); /** * lio_setup_glists - Setup gather lists @@ -154,6 +158,7 @@ int lio_setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs) return 0; } +EXPORT_SYMBOL_GPL(lio_setup_glists); int liquidio_set_feature(struct net_device *netdev, int cmd, u16 param1) { @@ -180,6 +185,7 @@ int liquidio_set_feature(struct net_device *netdev, int cmd, u16 param1) } return ret; } +EXPORT_SYMBOL_GPL(liquidio_set_feature); void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl, unsigned int bytes_compl) @@ -395,6 +401,7 @@ void liquidio_link_ctrl_cmd_completion(void *nctrl_ptr) nctrl->ncmd.s.cmd); } } +EXPORT_SYMBOL_GPL(liquidio_link_ctrl_cmd_completion); void octeon_pf_changed_vf_macaddr(struct octeon_device *oct, u8 *mac) { @@ -478,6 +485,7 @@ int setup_rx_oom_poll_fn(struct net_device *netdev) return 0; } +EXPORT_SYMBOL_GPL(setup_rx_oom_poll_fn); void cleanup_rx_oom_poll_fn(struct net_device *netdev) { @@ -495,6 +503,7 @@ void cleanup_rx_oom_poll_fn(struct net_device *netdev) } } } +EXPORT_SYMBOL_GPL(cleanup_rx_oom_poll_fn); /* Runs in interrupt context. */ static void lio_update_txq_status(struct octeon_device *oct, int iq_num) @@ -899,6 +908,7 @@ int liquidio_setup_io_queues(struct octeon_device *octeon_dev, int ifidx, return 0; } +EXPORT_SYMBOL_GPL(liquidio_setup_io_queues); static int liquidio_schedule_msix_droq_pkt_handler(struct octeon_droq *droq, u64 ret) @@ -1194,6 +1204,7 @@ int octeon_setup_interrupt(struct octeon_device *oct, u32 num_ioqs) } return 0; } +EXPORT_SYMBOL_GPL(octeon_setup_interrupt); /** * liquidio_change_mtu - Net device change_mtu @@ -1256,6 +1267,7 @@ int liquidio_change_mtu(struct net_device *netdev, int new_mtu) WRITE_ONCE(sc->caller_is_done, true); return 0; } +EXPORT_SYMBOL_GPL(liquidio_change_mtu); int lio_wait_for_clean_oq(struct octeon_device *oct) { @@ -1279,6 +1291,7 @@ int lio_wait_for_clean_oq(struct octeon_device *oct) return pending_pkts; } +EXPORT_SYMBOL_GPL(lio_wait_for_clean_oq); static void octnet_nic_stats_callback(struct octeon_device *oct_dev, @@ -1509,6 +1522,7 @@ void lio_fetch_stats(struct work_struct *work) return; } +EXPORT_SYMBOL_GPL(lio_fetch_stats); int liquidio_set_speed(struct lio *lio, int speed) { @@ -1659,6 +1673,7 @@ int liquidio_get_speed(struct lio *lio) return retval; } +EXPORT_SYMBOL_GPL(liquidio_get_speed); int liquidio_set_fec(struct lio *lio, int on_off) { @@ -1812,3 +1827,4 @@ int liquidio_get_fec(struct lio *lio) return retval; } +EXPORT_SYMBOL_GPL(liquidio_get_fec); diff --git a/drivers/net/ethernet/cavium/liquidio/lio_ethtool.c b/drivers/net/ethernet/cavium/liquidio/lio_ethtool.c index 2c10ae3f7fc1..9d56181a301f 100644 --- a/drivers/net/ethernet/cavium/liquidio/lio_ethtool.c +++ b/drivers/net/ethernet/cavium/liquidio/lio_ethtool.c @@ -3180,3 +3180,4 @@ void liquidio_set_ethtool_ops(struct net_device *netdev) else netdev->ethtool_ops = &lio_ethtool_ops; } +EXPORT_SYMBOL_GPL(liquidio_set_ethtool_ops); diff --git a/drivers/net/ethernet/cavium/liquidio/octeon_device.c b/drivers/net/ethernet/cavium/liquidio/octeon_device.c index e159194d0aef..364f4f912dc2 100644 --- a/drivers/net/ethernet/cavium/liquidio/octeon_device.c +++ b/drivers/net/ethernet/cavium/liquidio/octeon_device.c @@ -564,6 +564,7 @@ void octeon_init_device_list(int conf_type) for (i = 0; i < MAX_OCTEON_DEVICES; i++) oct_set_config_info(i, conf_type); } +EXPORT_SYMBOL_GPL(octeon_init_device_list); static void *__retrieve_octeon_config_info(struct octeon_device *oct, u16 card_type) @@ -633,6 +634,7 @@ char *lio_get_state_string(atomic_t *state_ptr) return oct_dev_state_str[OCT_DEV_STATE_INVALID]; return oct_dev_state_str[istate]; } +EXPORT_SYMBOL_GPL(lio_get_state_string); static char *get_oct_app_string(u32 app_mode) { @@ -661,6 +663,7 @@ void octeon_free_device_mem(struct octeon_device *oct) octeon_device[i] = NULL; octeon_device_count--; } +EXPORT_SYMBOL_GPL(octeon_free_device_mem); static struct octeon_device *octeon_allocate_device_mem(u32 pci_id, u32 priv_size) @@ -747,6 +750,7 @@ struct octeon_device *octeon_allocate_device(u32 pci_id, return oct; } +EXPORT_SYMBOL_GPL(octeon_allocate_device); /** Register a device's bus location at initialization time. * @param octeon_dev - pointer to the octeon device structure. @@ -804,6 +808,7 @@ int octeon_register_device(struct octeon_device *oct, return refcount; } +EXPORT_SYMBOL_GPL(octeon_register_device); /** Deregister a device at de-initialization time. * @param octeon_dev - pointer to the octeon device structure. @@ -821,6 +826,7 @@ int octeon_deregister_device(struct octeon_device *oct) return refcount; } +EXPORT_SYMBOL_GPL(octeon_deregister_device); int octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs) @@ -853,12 +859,14 @@ octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs) return 0; } +EXPORT_SYMBOL_GPL(octeon_allocate_ioq_vector); void octeon_free_ioq_vector(struct octeon_device *oct) { vfree(oct->ioq_vector); } +EXPORT_SYMBOL_GPL(octeon_free_ioq_vector); /* this function is only for setting up the first queue */ int octeon_setup_instr_queues(struct octeon_device *oct) @@ -904,6 +912,7 @@ int octeon_setup_instr_queues(struct octeon_device *oct) oct->num_iqs++; return 0; } +EXPORT_SYMBOL_GPL(octeon_setup_instr_queues); int octeon_setup_output_queues(struct octeon_device *oct) { @@ -940,6 +949,7 @@ int octeon_setup_output_queues(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(octeon_setup_output_queues); int octeon_set_io_queues_off(struct octeon_device *oct) { @@ -989,6 +999,7 @@ int octeon_set_io_queues_off(struct octeon_device *oct) } return 0; } +EXPORT_SYMBOL_GPL(octeon_set_io_queues_off); void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, @@ -1027,6 +1038,7 @@ int octeon_init_dispatch_list(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(octeon_init_dispatch_list); void octeon_delete_dispatch_list(struct octeon_device *oct) { @@ -1058,6 +1070,7 @@ void octeon_delete_dispatch_list(struct octeon_device *oct) kfree(temp); } } +EXPORT_SYMBOL_GPL(octeon_delete_dispatch_list); octeon_dispatch_fn_t octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, @@ -1180,6 +1193,7 @@ octeon_register_dispatch_fn(struct octeon_device *oct, return 0; } +EXPORT_SYMBOL_GPL(octeon_register_dispatch_fn); int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf) { @@ -1262,6 +1276,7 @@ int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf) octeon_free_recv_info(recv_info); return 0; } +EXPORT_SYMBOL_GPL(octeon_core_drv_init); int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no) @@ -1272,6 +1287,7 @@ int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no) return -1; } +EXPORT_SYMBOL_GPL(octeon_get_tx_qsize); int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no) { @@ -1280,6 +1296,7 @@ int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no) return oct->droq[q_no]->max_count; return -1; } +EXPORT_SYMBOL_GPL(octeon_get_rx_qsize); /* Retruns the host firmware handshake OCTEON specific configuration */ struct octeon_config *octeon_get_conf(struct octeon_device *oct) @@ -1302,6 +1319,7 @@ struct octeon_config *octeon_get_conf(struct octeon_device *oct) } return default_oct_conf; } +EXPORT_SYMBOL_GPL(octeon_get_conf); /* scratch register address is same in all the OCT-II and CN70XX models */ #define CNXX_SLI_SCRATCH1 0x3C0 @@ -1318,6 +1336,7 @@ struct octeon_device *lio_get_device(u32 octeon_id) else return octeon_device[octeon_id]; } +EXPORT_SYMBOL_GPL(lio_get_device); u64 lio_pci_readq(struct octeon_device *oct, u64 addr) { @@ -1349,6 +1368,7 @@ u64 lio_pci_readq(struct octeon_device *oct, u64 addr) return val64; } +EXPORT_SYMBOL_GPL(lio_pci_readq); void lio_pci_writeq(struct octeon_device *oct, u64 val, @@ -1369,6 +1389,7 @@ void lio_pci_writeq(struct octeon_device *oct, spin_unlock_irqrestore(&oct->pci_win_lock, flags); } +EXPORT_SYMBOL_GPL(lio_pci_writeq); int octeon_mem_access_ok(struct octeon_device *oct) { @@ -1388,6 +1409,7 @@ int octeon_mem_access_ok(struct octeon_device *oct) return access_okay ? 0 : 1; } +EXPORT_SYMBOL_GPL(octeon_mem_access_ok); int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout) { @@ -1408,6 +1430,7 @@ int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout) return ret; } +EXPORT_SYMBOL_GPL(octeon_wait_for_ddr_init); /* Get the octeon id assigned to the octeon device passed as argument. * This function is exported to other modules. @@ -1462,3 +1485,4 @@ void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq) } } } +EXPORT_SYMBOL_GPL(lio_enable_irq); diff --git a/drivers/net/ethernet/cavium/liquidio/octeon_droq.c b/drivers/net/ethernet/cavium/liquidio/octeon_droq.c index d4080bddcb6b..0d6ee30affb9 100644 --- a/drivers/net/ethernet/cavium/liquidio/octeon_droq.c +++ b/drivers/net/ethernet/cavium/liquidio/octeon_droq.c @@ -107,6 +107,7 @@ u32 octeon_droq_check_hw_for_pkts(struct octeon_droq *droq) return last_count; } +EXPORT_SYMBOL_GPL(octeon_droq_check_hw_for_pkts); static void octeon_droq_compute_max_packet_bufs(struct octeon_droq *droq) { @@ -216,6 +217,7 @@ int octeon_delete_droq(struct octeon_device *oct, u32 q_no) return 0; } +EXPORT_SYMBOL_GPL(octeon_delete_droq); int octeon_init_droq(struct octeon_device *oct, u32 q_no, @@ -773,6 +775,7 @@ octeon_droq_process_packets(struct octeon_device *oct, return 0; } +EXPORT_SYMBOL_GPL(octeon_droq_process_packets); /* * Utility function to poll for packets. check_hw_for_packets must be @@ -921,6 +924,7 @@ int octeon_unregister_droq_ops(struct octeon_device *oct, u32 q_no) return 0; } +EXPORT_SYMBOL_GPL(octeon_unregister_droq_ops); int octeon_create_droq(struct octeon_device *oct, u32 q_no, u32 num_descs, diff --git a/drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c b/drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c index 7ccab36143c1..d70132437af3 100644 --- a/drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c +++ b/drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.c @@ -164,6 +164,7 @@ octeon_pci_read_core_mem(struct octeon_device *oct, { __octeon_pci_rw_core_mem(oct, coreaddr, buf, len, 1); } +EXPORT_SYMBOL_GPL(octeon_pci_read_core_mem); void octeon_pci_write_core_mem(struct octeon_device *oct, @@ -173,6 +174,7 @@ octeon_pci_write_core_mem(struct octeon_device *oct, { __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)buf, len, 0); } +EXPORT_SYMBOL_GPL(octeon_pci_write_core_mem); u64 octeon_read_device_mem64(struct octeon_device *oct, u64 coreaddr) { @@ -182,6 +184,7 @@ u64 octeon_read_device_mem64(struct octeon_device *oct, u64 coreaddr) return be64_to_cpu(ret); } +EXPORT_SYMBOL_GPL(octeon_read_device_mem64); u32 octeon_read_device_mem32(struct octeon_device *oct, u64 coreaddr) { @@ -191,6 +194,7 @@ u32 octeon_read_device_mem32(struct octeon_device *oct, u64 coreaddr) return be32_to_cpu(ret); } +EXPORT_SYMBOL_GPL(octeon_read_device_mem32); void octeon_write_device_mem32(struct octeon_device *oct, u64 coreaddr, u32 val) @@ -199,3 +203,4 @@ void octeon_write_device_mem32(struct octeon_device *oct, u64 coreaddr, __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&t, 4, 0); } +EXPORT_SYMBOL_GPL(octeon_write_device_mem32); diff --git a/drivers/net/ethernet/cavium/liquidio/octeon_nic.c b/drivers/net/ethernet/cavium/liquidio/octeon_nic.c index 1a706f81bbb0..dee56ea740e7 100644 --- a/drivers/net/ethernet/cavium/liquidio/octeon_nic.c +++ b/drivers/net/ethernet/cavium/liquidio/octeon_nic.c @@ -79,6 +79,7 @@ octeon_alloc_soft_command_resp(struct octeon_device *oct, return sc; } +EXPORT_SYMBOL_GPL(octeon_alloc_soft_command_resp); int octnet_send_nic_data_pkt(struct octeon_device *oct, struct octnic_data_pkt *ndata, @@ -90,6 +91,7 @@ int octnet_send_nic_data_pkt(struct octeon_device *oct, ndata->buf, ndata->datasize, ndata->reqtype); } +EXPORT_SYMBOL_GPL(octnet_send_nic_data_pkt); static inline struct octeon_soft_command *octnic_alloc_ctrl_pkt_sc(struct octeon_device *oct, @@ -196,3 +198,4 @@ octnet_send_nic_ctrl_pkt(struct octeon_device *oct, return retval; } +EXPORT_SYMBOL_GPL(octnet_send_nic_ctrl_pkt); diff --git a/drivers/net/ethernet/cavium/liquidio/request_manager.c b/drivers/net/ethernet/cavium/liquidio/request_manager.c index 8e59c2825533..c2a10c7d6080 100644 --- a/drivers/net/ethernet/cavium/liquidio/request_manager.c +++ b/drivers/net/ethernet/cavium/liquidio/request_manager.c @@ -194,6 +194,7 @@ int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no) } return 1; } +EXPORT_SYMBOL_GPL(octeon_delete_instr_queue); /* Return 0 on success, 1 on failure */ int octeon_setup_iq(struct octeon_device *oct, @@ -267,6 +268,7 @@ int lio_wait_for_instr_fetch(struct octeon_device *oct) return instr_cnt; } +EXPORT_SYMBOL_GPL(lio_wait_for_instr_fetch); static inline void ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq) @@ -291,6 +293,7 @@ octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no) ring_doorbell(oct, iq); spin_unlock(&iq->post_lock); } +EXPORT_SYMBOL_GPL(octeon_ring_doorbell_locked); static inline void __copy_cmd_into_iq(struct octeon_instr_queue *iq, u8 *cmd) @@ -354,6 +357,7 @@ octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, return 0; } +EXPORT_SYMBOL_GPL(octeon_register_reqtype_free_fn); static inline void __add_to_request_list(struct octeon_instr_queue *iq, @@ -439,6 +443,7 @@ lio_process_iq_request_list(struct octeon_device *oct, return inst_count; } +EXPORT_SYMBOL_GPL(lio_process_iq_request_list); /* Can only be called from process context */ int @@ -575,6 +580,7 @@ octeon_send_command(struct octeon_device *oct, u32 iq_no, return st.status; } +EXPORT_SYMBOL_GPL(octeon_send_command); void octeon_prepare_soft_command(struct octeon_device *oct, @@ -682,6 +688,7 @@ octeon_prepare_soft_command(struct octeon_device *oct, } } } +EXPORT_SYMBOL_GPL(octeon_prepare_soft_command); int octeon_send_soft_command(struct octeon_device *oct, struct octeon_soft_command *sc) @@ -735,6 +742,7 @@ int octeon_send_soft_command(struct octeon_device *oct, return (octeon_send_command(oct, sc->iq_no, 1, &sc->cmd, sc, len, REQTYPE_SOFT_COMMAND)); } +EXPORT_SYMBOL_GPL(octeon_send_soft_command); int octeon_setup_sc_buffer_pool(struct octeon_device *oct) { @@ -764,6 +772,7 @@ int octeon_setup_sc_buffer_pool(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(octeon_setup_sc_buffer_pool); int octeon_free_sc_done_list(struct octeon_device *oct) { @@ -803,6 +812,7 @@ int octeon_free_sc_done_list(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(octeon_free_sc_done_list); int octeon_free_sc_zombie_list(struct octeon_device *oct) { @@ -827,6 +837,7 @@ int octeon_free_sc_zombie_list(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(octeon_free_sc_zombie_list); int octeon_free_sc_buffer_pool(struct octeon_device *oct) { @@ -851,6 +862,7 @@ int octeon_free_sc_buffer_pool(struct octeon_device *oct) return 0; } +EXPORT_SYMBOL_GPL(octeon_free_sc_buffer_pool); struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct, u32 datasize, @@ -922,6 +934,7 @@ struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct, return sc; } +EXPORT_SYMBOL_GPL(octeon_alloc_soft_command); void octeon_free_soft_command(struct octeon_device *oct, struct octeon_soft_command *sc) @@ -934,3 +947,4 @@ void octeon_free_soft_command(struct octeon_device *oct, spin_unlock_bh(&oct->sc_buf_pool.lock); } +EXPORT_SYMBOL_GPL(octeon_free_soft_command); diff --git a/drivers/net/ethernet/cavium/liquidio/response_manager.c b/drivers/net/ethernet/cavium/liquidio/response_manager.c index ac7747ccf56a..861050966e18 100644 --- a/drivers/net/ethernet/cavium/liquidio/response_manager.c +++ b/drivers/net/ethernet/cavium/liquidio/response_manager.c @@ -52,12 +52,14 @@ int octeon_setup_response_list(struct octeon_device *oct) return ret; } +EXPORT_SYMBOL_GPL(octeon_setup_response_list); void octeon_delete_response_list(struct octeon_device *oct) { cancel_delayed_work_sync(&oct->dma_comp_wq.wk.work); destroy_workqueue(oct->dma_comp_wq.wq); } +EXPORT_SYMBOL_GPL(octeon_delete_response_list); int lio_process_ordered_list(struct octeon_device *octeon_dev, u32 force_quit) @@ -219,6 +221,7 @@ int lio_process_ordered_list(struct octeon_device *octeon_dev, return 0; } +EXPORT_SYMBOL_GPL(lio_process_ordered_list); static void oct_poll_req_completion(struct work_struct *work) { From patchwork Sat Nov 19 23:06:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23346 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp897866wrr; Sat, 19 Nov 2022 15:07:52 -0800 (PST) X-Google-Smtp-Source: AA0mqf5+u2AIq7kP3QgsC1pM0qoOC7+PBZWC70BCdc05gYoUN/ekiR+Xytgm3bmVwlN68E5aBKRn X-Received: by 2002:a17:902:b283:b0:188:bc8e:9569 with SMTP id u3-20020a170902b28300b00188bc8e9569mr5723045plr.43.1668899272660; Sat, 19 Nov 2022 15:07:52 -0800 (PST) ARC-Seal: i=1; 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This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Introduce the new module, fsl-enetc-core, to provide the common functions to fsl-enetc and fsl-enetc-vf. [ alobakin: add exports to common functions ] Signed-off-by: Masahiro Yamada Reviewed-by: Alexander Lobakin Signed-off-by: Alexander Lobakin Reviewed-by: Masahiro Yamada --- drivers/net/ethernet/freescale/enetc/Kconfig | 5 +++++ drivers/net/ethernet/freescale/enetc/Makefile | 7 ++++--- drivers/net/ethernet/freescale/enetc/enetc.c | 21 +++++++++++++++++++ .../net/ethernet/freescale/enetc/enetc_cbdr.c | 7 +++++++ .../ethernet/freescale/enetc/enetc_ethtool.c | 2 ++ .../net/ethernet/freescale/enetc/enetc_pf.c | 2 ++ .../net/ethernet/freescale/enetc/enetc_vf.c | 2 ++ 7 files changed, 43 insertions(+), 3 deletions(-) -- 2.38.1 diff --git a/drivers/net/ethernet/freescale/enetc/Kconfig b/drivers/net/ethernet/freescale/enetc/Kconfig index cdc0ff89388a..a8a38df34760 100644 --- a/drivers/net/ethernet/freescale/enetc/Kconfig +++ b/drivers/net/ethernet/freescale/enetc/Kconfig @@ -1,7 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 +config FSL_ENETC_CORE + tristate + config FSL_ENETC tristate "ENETC PF driver" depends on PCI && PCI_MSI + select FSL_ENETC_CORE select FSL_ENETC_IERB select FSL_ENETC_MDIO select PHYLINK @@ -17,6 +21,7 @@ config FSL_ENETC config FSL_ENETC_VF tristate "ENETC VF driver" depends on PCI && PCI_MSI + select FSL_ENETC_CORE select FSL_ENETC_MDIO select PHYLINK select DIMLIB diff --git a/drivers/net/ethernet/freescale/enetc/Makefile b/drivers/net/ethernet/freescale/enetc/Makefile index e0e8dfd13793..d67319e09bad 100644 --- a/drivers/net/ethernet/freescale/enetc/Makefile +++ b/drivers/net/ethernet/freescale/enetc/Makefile @@ -1,14 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 -common-objs := enetc.o enetc_cbdr.o enetc_ethtool.o +obj-$(CONFIG_FSL_ENETC_CORE) += fsl-enetc-core.o +fsl-enetc-core-y += enetc.o enetc_cbdr.o enetc_ethtool.o obj-$(CONFIG_FSL_ENETC) += fsl-enetc.o -fsl-enetc-y := enetc_pf.o $(common-objs) +fsl-enetc-y := enetc_pf.o fsl-enetc-$(CONFIG_PCI_IOV) += enetc_msg.o fsl-enetc-$(CONFIG_FSL_ENETC_QOS) += enetc_qos.o obj-$(CONFIG_FSL_ENETC_VF) += fsl-enetc-vf.o -fsl-enetc-vf-y := enetc_vf.o $(common-objs) +fsl-enetc-vf-y := enetc_vf.o obj-$(CONFIG_FSL_ENETC_IERB) += fsl-enetc-ierb.o fsl-enetc-ierb-y := enetc_ierb.o diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c index f8c06c3f9464..f13bb6b1c026 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc.c +++ b/drivers/net/ethernet/freescale/enetc/enetc.c @@ -651,6 +651,7 @@ netdev_tx_t enetc_xmit(struct sk_buff *skb, struct net_device *ndev) return enetc_start_xmit(skb, ndev); } +EXPORT_SYMBOL_NS_GPL(enetc_xmit, FSL_ENETC_CORE); static irqreturn_t enetc_msix(int irq, void *data) { @@ -1384,6 +1385,7 @@ int enetc_xdp_xmit(struct net_device *ndev, int num_frames, return xdp_tx_frm_cnt; } +EXPORT_SYMBOL_NS_GPL(enetc_xdp_xmit, FSL_ENETC_CORE); static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i, struct xdp_buff *xdp_buff, u16 size) @@ -1735,6 +1737,7 @@ void enetc_get_si_caps(struct enetc_si *si) if (val & ENETC_SIPCAPR0_PSFP) si->hw_features |= ENETC_SI_F_PSFP; } +EXPORT_SYMBOL_NS_GPL(enetc_get_si_caps, FSL_ENETC_CORE); static int enetc_dma_alloc_bdr(struct enetc_bdr *r, size_t bd_size) { @@ -1999,6 +2002,7 @@ int enetc_configure_si(struct enetc_ndev_priv *priv) return 0; } +EXPORT_SYMBOL_NS_GPL(enetc_configure_si, FSL_ENETC_CORE); void enetc_init_si_rings_params(struct enetc_ndev_priv *priv) { @@ -2018,6 +2022,7 @@ void enetc_init_si_rings_params(struct enetc_ndev_priv *priv) priv->ic_mode = ENETC_IC_RX_ADAPTIVE | ENETC_IC_TX_MANUAL; priv->tx_ictt = ENETC_TXIC_TIMETHR; } +EXPORT_SYMBOL_NS_GPL(enetc_init_si_rings_params, FSL_ENETC_CORE); int enetc_alloc_si_resources(struct enetc_ndev_priv *priv) { @@ -2030,11 +2035,13 @@ int enetc_alloc_si_resources(struct enetc_ndev_priv *priv) return 0; } +EXPORT_SYMBOL_NS_GPL(enetc_alloc_si_resources, FSL_ENETC_CORE); void enetc_free_si_resources(struct enetc_ndev_priv *priv) { kfree(priv->cls_rules); } +EXPORT_SYMBOL_NS_GPL(enetc_free_si_resources, FSL_ENETC_CORE); static void enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) { @@ -2398,6 +2405,7 @@ int enetc_open(struct net_device *ndev) return err; } +EXPORT_SYMBOL_NS_GPL(enetc_open, FSL_ENETC_CORE); void enetc_stop(struct net_device *ndev) { @@ -2439,6 +2447,7 @@ int enetc_close(struct net_device *ndev) return 0; } +EXPORT_SYMBOL_NS_GPL(enetc_close, FSL_ENETC_CORE); int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data) { @@ -2494,6 +2503,7 @@ int enetc_setup_tc_mqprio(struct net_device *ndev, void *type_data) return 0; } +EXPORT_SYMBOL_NS_GPL(enetc_setup_tc_mqprio, FSL_ENETC_CORE); static int enetc_setup_xdp_prog(struct net_device *dev, struct bpf_prog *prog, struct netlink_ext_ack *extack) @@ -2542,6 +2552,7 @@ int enetc_setup_bpf(struct net_device *dev, struct netdev_bpf *xdp) return 0; } +EXPORT_SYMBOL_NS_GPL(enetc_setup_bpf, FSL_ENETC_CORE); struct net_device_stats *enetc_get_stats(struct net_device *ndev) { @@ -2573,6 +2584,7 @@ struct net_device_stats *enetc_get_stats(struct net_device *ndev) return stats; } +EXPORT_SYMBOL_NS_GPL(enetc_get_stats, FSL_ENETC_CORE); static int enetc_set_rss(struct net_device *ndev, int en) { @@ -2625,6 +2637,7 @@ void enetc_set_features(struct net_device *ndev, netdev_features_t features) enetc_enable_txvlan(ndev, !!(features & NETIF_F_HW_VLAN_CTAG_TX)); } +EXPORT_SYMBOL_NS_GPL(enetc_set_features, FSL_ENETC_CORE); #ifdef CONFIG_FSL_ENETC_PTP_CLOCK static int enetc_hwtstamp_set(struct net_device *ndev, struct ifreq *ifr) @@ -2708,6 +2721,7 @@ int enetc_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) return phylink_mii_ioctl(priv->phylink, rq, cmd); } +EXPORT_SYMBOL_NS_GPL(enetc_ioctl, FSL_ENETC_CORE); int enetc_alloc_msix(struct enetc_ndev_priv *priv) { @@ -2809,6 +2823,7 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv) return err; } +EXPORT_SYMBOL_NS_GPL(enetc_alloc_msix, FSL_ENETC_CORE); void enetc_free_msix(struct enetc_ndev_priv *priv) { @@ -2838,6 +2853,7 @@ void enetc_free_msix(struct enetc_ndev_priv *priv) /* disable all MSIX for this device */ pci_free_irq_vectors(priv->si->pdev); } +EXPORT_SYMBOL_NS_GPL(enetc_free_msix, FSL_ENETC_CORE); static void enetc_kfree_si(struct enetc_si *si) { @@ -2927,6 +2943,7 @@ int enetc_pci_probe(struct pci_dev *pdev, const char *name, int sizeof_priv) return err; } +EXPORT_SYMBOL_NS_GPL(enetc_pci_probe, FSL_ENETC_CORE); void enetc_pci_remove(struct pci_dev *pdev) { @@ -2938,3 +2955,7 @@ void enetc_pci_remove(struct pci_dev *pdev) pci_release_mem_regions(pdev); pci_disable_device(pdev); } +EXPORT_SYMBOL_NS_GPL(enetc_pci_remove, FSL_ENETC_CORE); + +MODULE_DESCRIPTION("ENETC Core"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c index af68dc46a795..acb48ceef760 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_cbdr.c @@ -44,6 +44,7 @@ int enetc_setup_cbdr(struct device *dev, struct enetc_hw *hw, int bd_count, return 0; } +EXPORT_SYMBOL_NS_GPL(enetc_setup_cbdr, FSL_ENETC_CORE); void enetc_teardown_cbdr(struct enetc_cbdr *cbdr) { @@ -57,6 +58,7 @@ void enetc_teardown_cbdr(struct enetc_cbdr *cbdr) cbdr->bd_base = NULL; cbdr->dma_dev = NULL; } +EXPORT_SYMBOL_NS_GPL(enetc_teardown_cbdr, FSL_ENETC_CORE); static void enetc_clean_cbdr(struct enetc_cbdr *ring) { @@ -127,6 +129,7 @@ int enetc_send_cmd(struct enetc_si *si, struct enetc_cbd *cbd) return 0; } +EXPORT_SYMBOL_NS_GPL(enetc_send_cmd, FSL_ENETC_CORE); int enetc_clear_mac_flt_entry(struct enetc_si *si, int index) { @@ -140,6 +143,7 @@ int enetc_clear_mac_flt_entry(struct enetc_si *si, int index) return enetc_send_cmd(si, &cbd); } +EXPORT_SYMBOL_NS_GPL(enetc_clear_mac_flt_entry, FSL_ENETC_CORE); int enetc_set_mac_flt_entry(struct enetc_si *si, int index, char *mac_addr, int si_map) @@ -165,6 +169,7 @@ int enetc_set_mac_flt_entry(struct enetc_si *si, int index, return enetc_send_cmd(si, &cbd); } +EXPORT_SYMBOL_NS_GPL(enetc_set_mac_flt_entry, FSL_ENETC_CORE); /* Set entry in RFS table */ int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse, @@ -197,6 +202,7 @@ int enetc_set_fs_entry(struct enetc_si *si, struct enetc_cmd_rfse *rfse, return err; } +EXPORT_SYMBOL_NS_GPL(enetc_set_fs_entry, FSL_ENETC_CORE); static int enetc_cmd_rss_table(struct enetc_si *si, u32 *table, int count, bool read) @@ -248,3 +254,4 @@ int enetc_set_rss_table(struct enetc_si *si, const u32 *table, int count) { return enetc_cmd_rss_table(si, (u32 *)table, count, false); } +EXPORT_SYMBOL_NS_GPL(enetc_set_rss_table, FSL_ENETC_CORE); diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c index c8369e3752b0..e3d3a34fc96b 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c @@ -651,6 +651,7 @@ void enetc_set_rss_key(struct enetc_hw *hw, const u8 *bytes) for (i = 0; i < ENETC_RSSHASH_KEY_SIZE / 4; i++) enetc_port_wr(hw, ENETC_PRSSK(i), ((u32 *)bytes)[i]); } +EXPORT_SYMBOL_NS_GPL(enetc_set_rss_key, FSL_ENETC_CORE); static int enetc_set_rxfh(struct net_device *ndev, const u32 *indir, const u8 *key, const u8 hfunc) @@ -926,3 +927,4 @@ void enetc_set_ethtool_ops(struct net_device *ndev) else ndev->ethtool_ops = &enetc_vf_ethtool_ops; } +EXPORT_SYMBOL_NS_GPL(enetc_set_ethtool_ops, FSL_ENETC_CORE); diff --git a/drivers/net/ethernet/freescale/enetc/enetc_pf.c b/drivers/net/ethernet/freescale/enetc/enetc_pf.c index bdf94335ee99..b767b6a28e8b 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c @@ -1410,5 +1410,7 @@ static struct pci_driver enetc_pf_driver = { }; module_pci_driver(enetc_pf_driver); +MODULE_IMPORT_NS(FSL_ENETC_CORE); + MODULE_DESCRIPTION(ENETC_DRV_NAME_STR); MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/net/ethernet/freescale/enetc/enetc_vf.c b/drivers/net/ethernet/freescale/enetc/enetc_vf.c index dfcaac302e24..ab53799618c7 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc_vf.c +++ b/drivers/net/ethernet/freescale/enetc/enetc_vf.c @@ -259,5 +259,7 @@ static struct pci_driver enetc_vf_driver = { }; module_pci_driver(enetc_vf_driver); +MODULE_IMPORT_NS(FSL_ENETC_CORE); + MODULE_DESCRIPTION(ENETC_DRV_NAME_STR); MODULE_LICENSE("Dual BSD/GPL"); From patchwork Sat Nov 19 23:07:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23347 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp898477wrr; Sat, 19 Nov 2022 15:10:01 -0800 (PST) X-Google-Smtp-Source: AA0mqf7myPpnI1ebWFObHxW/2gBag93RySMEqqCPYFTPAch07kJ/MLox3HqfRS3QQS8bSdIQ0DOl X-Received: by 2002:a63:530f:0:b0:476:bfca:38ad with SMTP id h15-20020a63530f000000b00476bfca38admr3139061pgb.576.1668899401692; Sat, 19 Nov 2022 15:10:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899401; cv=none; d=google.com; s=arc-20160816; b=yldf7r1ae4hdlEzzNe5AdUX+OQMGS/OnhXmY0FX2UTff3qZQg67K59lbMGxHkzzEli QMdhHM0T3nOZy8+6s0GH+v+rAKq1tThj993E6NpJ7fSsUzmfkXAOGlMGCWEQc/92LTlZ 247XrpE2GF8MGMIMlCyv3eoN5KPYdk1B75uTr6r6is/0WQGno2+9YNKQCs+cpVVddNLY Fk4dJNrjf+y/i0Cf0CRQmFZ1taDkur2pfIwgnMmkK86kzxTRhwwJ+ioE181PAMk4WSsc oyOGzxXs1r2AbKFLDlW/D6yzQBaX1PAAqUZkUtJEZE4S6gV1UFe0oZ+cF/U10FC6vG0s 9eTQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p6-20020a654906000000b00458ae7b0a24si7800032pgs.208.2022.11.19.15.09.48; Sat, 19 Nov 2022 15:10:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=nnoaEEKY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235051AbiKSXHi (ORCPT + 99 others); Sat, 19 Nov 2022 18:07:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235131AbiKSXHa (ORCPT ); Sat, 19 Nov 2022 18:07:30 -0500 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F61C1A20F; Sat, 19 Nov 2022 15:07:29 -0800 (PST) Date: Sat, 19 Nov 2022 23:07:20 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899247; x=1669158447; bh=z5EwErPNabx0KbW3NJbE+dQBJOp75EzBGrGloRwIuN0=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=nnoaEEKY5ft1oKGOfAZPj+LAEtg0D88SpRKM9wyLs+0hxhqbcdiGAJ7IelxQcG0/o WRoEXlQhmkqUKRIBTgjPvhSmZ26sZ28WmJRqLSmeR54HM93eIyAYzOvHVMt/tmvhUE Na6l/4wOhJcaYbFeUAqQefkYnqnrsxMCSkfx/8QVumIrmb733uScTHej9O/4XZIppO WpQNIxKne2gLnN0jKjRV0x8abu58slF+jRXfyFeBgbYNpngLaR+8gcpYCnU5BmJ5Pa HmZqd26dqKxgGmnxvRF/4Khd53dRj3SriuvET/oDK8OO/uUSLb+vvyE3Ph1RdFvZrH 6TDBq0AsAfPxQ== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/18] net: emac, cpsw: fix mixed module-builtin object (davinci_cpdma) Message-ID: <20221119225650.1044591-10-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967858545754396?= X-GMAIL-MSGID: =?utf-8?q?1749967858545754396?= From: Masahiro Yamada CONFIG_TI_DAVINCI_EMAC, CONFIG_TI_CPSW and CONFIG_TI_CPSW_SWITCHDEV are all tristate. This means that davinci_cpdma.o can be linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Introduce the new module, ti_davinci_cpdma, to provide the common functions to these three modules. [ alobakin: add exports ] Signed-off-by: Masahiro Yamada Reviewed-by: Alexander Lobakin Signed-off-by: Alexander Lobakin --- drivers/net/ethernet/ti/Kconfig | 6 +++++ drivers/net/ethernet/ti/Makefile | 8 +++--- drivers/net/ethernet/ti/cpsw.c | 2 ++ drivers/net/ethernet/ti/cpsw_new.c | 2 ++ drivers/net/ethernet/ti/davinci_cpdma.c | 33 +++++++++++++++++++++++++ drivers/net/ethernet/ti/davinci_emac.c | 2 ++ 6 files changed, 50 insertions(+), 3 deletions(-) -- 2.38.1 diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig index fce06663e1e1..2ac0adf0c07d 100644 --- a/drivers/net/ethernet/ti/Kconfig +++ b/drivers/net/ethernet/ti/Kconfig @@ -17,9 +17,13 @@ config NET_VENDOR_TI if NET_VENDOR_TI +config TI_DAVINCI_CPDMA + tristate + config TI_DAVINCI_EMAC tristate "TI DaVinci EMAC Support" depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 ) || COMPILE_TEST + select TI_DAVINCI_CPDMA select TI_DAVINCI_MDIO select PHYLIB select GENERIC_ALLOCATOR @@ -51,6 +55,7 @@ config TI_CPSW tristate "TI CPSW Switch Support" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST depends on TI_CPTS || !TI_CPTS + select TI_DAVINCI_CPDMA select TI_DAVINCI_MDIO select MFD_SYSCON select PAGE_POOL @@ -68,6 +73,7 @@ config TI_CPSW_SWITCHDEV depends on NET_SWITCHDEV depends on TI_CPTS || !TI_CPTS select PAGE_POOL + select TI_DAVINCI_CPDMA select TI_DAVINCI_MDIO select MFD_SYSCON select REGMAP diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile index 75f761efbea7..28a741ed0ac8 100644 --- a/drivers/net/ethernet/ti/Makefile +++ b/drivers/net/ethernet/ti/Makefile @@ -9,15 +9,17 @@ obj-$(CONFIG_TI_CPSW_SWITCHDEV) += cpsw-common.o obj-$(CONFIG_TLAN) += tlan.o obj-$(CONFIG_CPMAC) += cpmac.o +obj-$(CONFIG_TI_DAVINCI_CPDMA) += ti_davinci_cpdma.o +ti_davinci_cpdma-y := davinci_cpdma.o obj-$(CONFIG_TI_DAVINCI_EMAC) += ti_davinci_emac.o -ti_davinci_emac-y := davinci_emac.o davinci_cpdma.o +ti_davinci_emac-y := davinci_emac.o obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o obj-$(CONFIG_TI_CPTS) += cpts.o obj-$(CONFIG_TI_CPSW) += ti_cpsw.o -ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o cpsw_priv.o cpsw_sl.o cpsw_ethtool.o +ti_cpsw-y := cpsw.o cpsw_ale.o cpsw_priv.o cpsw_sl.o cpsw_ethtool.o obj-$(CONFIG_TI_CPSW_SWITCHDEV) += ti_cpsw_new.o -ti_cpsw_new-y := cpsw_switchdev.o cpsw_new.o davinci_cpdma.o cpsw_ale.o cpsw_sl.o cpsw_priv.o cpsw_ethtool.o +ti_cpsw_new-y := cpsw_switchdev.o cpsw_new.o cpsw_ale.o cpsw_sl.o cpsw_priv.o cpsw_ethtool.o obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o keystone_netcp-y := netcp_core.o cpsw_ale.o diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 13c9c2d6b79b..b7ac61329b20 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1796,6 +1796,8 @@ static struct platform_driver cpsw_driver = { module_platform_driver(cpsw_driver); +MODULE_IMPORT_NS(TI_DAVINCI_CPDMA); + MODULE_LICENSE("GPL"); MODULE_AUTHOR("Cyril Chemparathy "); MODULE_AUTHOR("Mugunthan V N "); diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 83596ec0c7cb..9ed398c04c04 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -2116,5 +2116,7 @@ static struct platform_driver cpsw_driver = { module_platform_driver(cpsw_driver); +MODULE_IMPORT_NS(TI_DAVINCI_CPDMA); + MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("TI CPSW switchdev Ethernet driver"); diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c index d2eab5cd1e0c..32ba94626cda 100644 --- a/drivers/net/ethernet/ti/davinci_cpdma.c +++ b/drivers/net/ethernet/ti/davinci_cpdma.c @@ -531,6 +531,7 @@ struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) ctlr->num_chan = CPDMA_MAX_CHANNELS; return ctlr; } +EXPORT_SYMBOL_NS_GPL(cpdma_ctlr_create, TI_DAVINCI_CPDMA); int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) { @@ -591,6 +592,7 @@ int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_ctlr_start, TI_DAVINCI_CPDMA); int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) { @@ -623,6 +625,7 @@ int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_ctlr_stop, TI_DAVINCI_CPDMA); int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) { @@ -640,6 +643,7 @@ int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) cpdma_desc_pool_destroy(ctlr); return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_ctlr_destroy, TI_DAVINCI_CPDMA); int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) { @@ -660,21 +664,25 @@ int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_ctlr_int_ctrl, TI_DAVINCI_CPDMA); void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value) { dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value); } +EXPORT_SYMBOL_NS_GPL(cpdma_ctlr_eoi, TI_DAVINCI_CPDMA); u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr) { return dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED); } +EXPORT_SYMBOL_NS_GPL(cpdma_ctrl_rxchs_state, TI_DAVINCI_CPDMA); u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr) { return dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED); } +EXPORT_SYMBOL_NS_GPL(cpdma_ctrl_txchs_state, TI_DAVINCI_CPDMA); static void cpdma_chan_set_descs(struct cpdma_ctlr *ctlr, int rx, int desc_num, @@ -802,6 +810,7 @@ int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight) spin_unlock_irqrestore(&ctlr->lock, flags); return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_set_weight, TI_DAVINCI_CPDMA); /* cpdma_chan_get_min_rate - get minimum allowed rate for channel * Should be called before cpdma_chan_set_rate. @@ -816,6 +825,7 @@ u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr) return DIV_ROUND_UP(divident, divisor); } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_get_min_rate, TI_DAVINCI_CPDMA); /* cpdma_chan_set_rate - limits bandwidth for transmit channel. * The bandwidth * limited channels have to be in order beginning from lowest. @@ -860,6 +870,7 @@ int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate) spin_unlock_irqrestore(&ctlr->lock, flags); return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_set_rate, TI_DAVINCI_CPDMA); u32 cpdma_chan_get_rate(struct cpdma_chan *ch) { @@ -872,6 +883,7 @@ u32 cpdma_chan_get_rate(struct cpdma_chan *ch) return rate; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_get_rate, TI_DAVINCI_CPDMA); struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, cpdma_handler_fn handler, int rx_type) @@ -931,6 +943,7 @@ struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, spin_unlock_irqrestore(&ctlr->lock, flags); return chan; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_create, TI_DAVINCI_CPDMA); int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) { @@ -943,6 +956,7 @@ int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) return desc_num; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_get_rx_buf_num, TI_DAVINCI_CPDMA); int cpdma_chan_destroy(struct cpdma_chan *chan) { @@ -964,6 +978,7 @@ int cpdma_chan_destroy(struct cpdma_chan *chan) spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_destroy, TI_DAVINCI_CPDMA); int cpdma_chan_get_stats(struct cpdma_chan *chan, struct cpdma_chan_stats *stats) @@ -976,6 +991,7 @@ int cpdma_chan_get_stats(struct cpdma_chan *chan, spin_unlock_irqrestore(&chan->lock, flags); return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_get_stats, TI_DAVINCI_CPDMA); static void __cpdma_chan_submit(struct cpdma_chan *chan, struct cpdma_desc __iomem *desc) @@ -1100,6 +1116,7 @@ int cpdma_chan_idle_submit(struct cpdma_chan *chan, void *token, void *data, spin_unlock_irqrestore(&chan->lock, flags); return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_idle_submit, TI_DAVINCI_CPDMA); int cpdma_chan_idle_submit_mapped(struct cpdma_chan *chan, void *token, dma_addr_t data, int len, int directed) @@ -1125,6 +1142,7 @@ int cpdma_chan_idle_submit_mapped(struct cpdma_chan *chan, void *token, spin_unlock_irqrestore(&chan->lock, flags); return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_idle_submit_mapped, TI_DAVINCI_CPDMA); int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, int len, int directed) @@ -1150,6 +1168,7 @@ int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, spin_unlock_irqrestore(&chan->lock, flags); return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_submit, TI_DAVINCI_CPDMA); int cpdma_chan_submit_mapped(struct cpdma_chan *chan, void *token, dma_addr_t data, int len, int directed) @@ -1175,6 +1194,7 @@ int cpdma_chan_submit_mapped(struct cpdma_chan *chan, void *token, spin_unlock_irqrestore(&chan->lock, flags); return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_submit_mapped, TI_DAVINCI_CPDMA); bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) { @@ -1189,6 +1209,7 @@ bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) spin_unlock_irqrestore(&chan->lock, flags); return free_tx_desc; } +EXPORT_SYMBOL_NS_GPL(cpdma_check_free_tx_desc, TI_DAVINCI_CPDMA); static void __cpdma_chan_free(struct cpdma_chan *chan, struct cpdma_desc __iomem *desc, @@ -1289,6 +1310,7 @@ int cpdma_chan_process(struct cpdma_chan *chan, int quota) } return used; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_process, TI_DAVINCI_CPDMA); int cpdma_chan_start(struct cpdma_chan *chan) { @@ -1308,6 +1330,7 @@ int cpdma_chan_start(struct cpdma_chan *chan) return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_start, TI_DAVINCI_CPDMA); int cpdma_chan_stop(struct cpdma_chan *chan) { @@ -1370,6 +1393,7 @@ int cpdma_chan_stop(struct cpdma_chan *chan) spin_unlock_irqrestore(&chan->lock, flags); return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_stop, TI_DAVINCI_CPDMA); int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) { @@ -1387,6 +1411,7 @@ int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) return 0; } +EXPORT_SYMBOL_NS_GPL(cpdma_chan_int_ctrl, TI_DAVINCI_CPDMA); int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) { @@ -1399,6 +1424,7 @@ int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_control_get, TI_DAVINCI_CPDMA); int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) { @@ -1411,16 +1437,19 @@ int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_control_set, TI_DAVINCI_CPDMA); int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr) { return ctlr->num_rx_desc; } +EXPORT_SYMBOL_NS_GPL(cpdma_get_num_rx_descs, TI_DAVINCI_CPDMA); int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr) { return ctlr->num_tx_desc; } +EXPORT_SYMBOL_NS_GPL(cpdma_get_num_tx_descs, TI_DAVINCI_CPDMA); int cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc) { @@ -1442,3 +1471,7 @@ int cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc) return ret; } +EXPORT_SYMBOL_NS_GPL(cpdma_set_num_rx_descs, TI_DAVINCI_CPDMA); + +MODULE_DESCRIPTION("TI CPDMA driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c index 2eb9d5a32588..897def12e6ec 100644 --- a/drivers/net/ethernet/ti/davinci_emac.c +++ b/drivers/net/ethernet/ti/davinci_emac.c @@ -2103,6 +2103,8 @@ static void __exit davinci_emac_exit(void) } module_exit(davinci_emac_exit); +MODULE_IMPORT_NS(TI_DAVINCI_CPDMA); + MODULE_LICENSE("GPL"); MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole "); MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S "); 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id oc17-20020a17090b1c1100b00217b50ee7b6si8590439pjb.1.2022.11.19.15.10.24; Sat, 19 Nov 2022 15:10:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=MNkyYydh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235222AbiKSXIG (ORCPT + 99 others); Sat, 19 Nov 2022 18:08:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234973AbiKSXIC (ORCPT ); Sat, 19 Nov 2022 18:08:02 -0500 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 596351A07F for ; Sat, 19 Nov 2022 15:08:01 -0800 (PST) Date: Sat, 19 Nov 2022 23:07:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899279; x=1669158479; bh=Fcan82p+ax2WlxRBhBg1kgUsi97y6iC8yqz1mQgRMSY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=MNkyYydhsrau86fX56V/ZK0IxXawrURgWy6h6DRdkKSpYLJwCK1YZL/9DAmJTM+lO IQXWEf2g+c4kQF71tJLMSO5LgZyl/xlqiATVfCsasAlVzcCh+dTLm41PCJPcGxdseh jWCi3MnVIb6v9R0v8CVq4fNwngDa7ooqiwKXCN5LPwN7Q3eTSgVd7ey+MJeljrvm0W vqjDmjmuQYhSKdl/mmOGDadnPOiPiYYJZE1XaBZMp6ARxL5Zmy4dWZV2CxUFra7ytO aK0P4FOhW7fvZDKpw040ciFjvH5WX2pSU66dGl6EiVD0d0TwC8eMqgz5qFDGi7g9TG rlEXU+EYqwu5w== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/18] EDAC: i10nm, skx: fix mixed module-builtin object Message-ID: <20221119225650.1044591-11-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967895881699688?= X-GMAIL-MSGID: =?utf-8?q?1749967895881699688?= With CONFIG_EDAC_SKX=m and CONFIG_EDAC_I10NM=y (or vice versa), skx_common.o are linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules: > scripts/Makefile.build:252: ./drivers/edac/Makefile: skx_common.o > is added to multiple modules: i10nm_edac skx_edac This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Introduce the new module, skx_edac_common, to provide the common functions to skx_edac and i10nm_edac. skx_adxl_{get,put}() loose their __init/__exit annotations in order to become exportable. Fixes: d4dc89d069aa ("EDAC, i10nm: Add a driver for Intel 10nm server processors") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin Reviewed-by: Masahiro Yamada --- drivers/edac/Kconfig | 11 +++++++---- drivers/edac/Makefile | 7 +++++-- drivers/edac/i10nm_base.c | 2 ++ drivers/edac/skx_base.c | 2 ++ drivers/edac/skx_common.c | 21 +++++++++++++++++++-- drivers/edac/skx_common.h | 4 ++-- 6 files changed, 37 insertions(+), 10 deletions(-) -- 2.38.1 diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 456602d373b7..c3d96d2a814b 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -236,12 +236,16 @@ config EDAC_SBRIDGE Support for error detection and correction the Intel Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. +config EDAC_SKX_COMMON + tristate + select ACPI_ADXL + select DMI + config EDAC_SKX tristate "Intel Skylake server Integrated MC" depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y - select DMI - select ACPI_ADXL + select EDAC_SKX_COMMON help Support for error detection and correction the Intel Skylake server Integrated Memory Controllers. If your @@ -252,8 +256,7 @@ config EDAC_I10NM tristate "Intel 10nm server Integrated MC" depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y - select DMI - select ACPI_ADXL + select EDAC_SKX_COMMON help Support for error detection and correction the Intel 10nm server Integrated Memory Controllers. If your diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 2d1641a27a28..36e6e07d4048 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -54,10 +54,13 @@ obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o -skx_edac-y := skx_common.o skx_base.o +skx_edac_common-y := skx_common.o +obj-$(CONFIG_EDAC_SKX_COMMON) += skx_edac_common.o + +skx_edac-y := skx_base.o obj-$(CONFIG_EDAC_SKX) += skx_edac.o -i10nm_edac-y := skx_common.o i10nm_base.o +i10nm_edac-y := i10nm_base.o obj-$(CONFIG_EDAC_I10NM) += i10nm_edac.o obj-$(CONFIG_EDAC_CELL) += cell_edac.o diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c index a22ea053f8e1..949f665fd94c 100644 --- a/drivers/edac/i10nm_base.c +++ b/drivers/edac/i10nm_base.c @@ -900,5 +900,7 @@ MODULE_PARM_DESC(decoding_via_mca, "decoding_via_mca: 0=off(default), 1=enable") module_param(retry_rd_err_log, int, 0444); MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)"); +MODULE_IMPORT_NS(EDAC_SKX_COMMON); + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors"); diff --git a/drivers/edac/skx_base.c b/drivers/edac/skx_base.c index 7e2762f62eec..1656cd4cd0ed 100644 --- a/drivers/edac/skx_base.c +++ b/drivers/edac/skx_base.c @@ -751,6 +751,8 @@ module_exit(skx_exit); module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); +MODULE_IMPORT_NS(EDAC_SKX_COMMON); + MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Tony Luck"); MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors"); diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index f0f8e98f6efb..15a3fb1224ae 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -48,7 +48,7 @@ static u64 skx_tolm, skx_tohm; static LIST_HEAD(dev_edac_list); static bool skx_mem_cfg_2lm; -int __init skx_adxl_get(void) +int skx_adxl_get(void) { const char * const *names; int i, j; @@ -110,12 +110,14 @@ int __init skx_adxl_get(void) return -ENODEV; } +EXPORT_SYMBOL_NS_GPL(skx_adxl_get, EDAC_SKX_COMMON); -void __exit skx_adxl_put(void) +void skx_adxl_put(void) { kfree(adxl_values); kfree(adxl_msg); } +EXPORT_SYMBOL_NS_GPL(skx_adxl_put, EDAC_SKX_COMMON); static bool skx_adxl_decode(struct decoded_addr *res, bool error_in_1st_level_mem) { @@ -187,12 +189,14 @@ void skx_set_mem_cfg(bool mem_cfg_2lm) { skx_mem_cfg_2lm = mem_cfg_2lm; } +EXPORT_SYMBOL_NS_GPL(skx_set_mem_cfg, EDAC_SKX_COMMON); void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log) { driver_decode = decode; skx_show_retry_rd_err_log = show_retry_log; } +EXPORT_SYMBOL_NS_GPL(skx_set_decode, EDAC_SKX_COMMON); int skx_get_src_id(struct skx_dev *d, int off, u8 *id) { @@ -206,6 +210,7 @@ int skx_get_src_id(struct skx_dev *d, int off, u8 *id) *id = GET_BITFIELD(reg, 12, 14); return 0; } +EXPORT_SYMBOL_NS_GPL(skx_get_src_id, EDAC_SKX_COMMON); int skx_get_node_id(struct skx_dev *d, u8 *id) { @@ -219,6 +224,7 @@ int skx_get_node_id(struct skx_dev *d, u8 *id) *id = GET_BITFIELD(reg, 0, 2); return 0; } +EXPORT_SYMBOL_NS_GPL(skx_get_node_id, EDAC_SKX_COMMON); static int get_width(u32 mtr) { @@ -284,6 +290,7 @@ int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list) *list = &dev_edac_list; return ndev; } +EXPORT_SYMBOL_NS_GPL(skx_get_all_bus_mappings, EDAC_SKX_COMMON); int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm) { @@ -323,6 +330,7 @@ int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm) pci_dev_put(pdev); return -ENODEV; } +EXPORT_SYMBOL_NS_GPL(skx_get_hi_lo, EDAC_SKX_COMMON); static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add, int minval, int maxval, const char *name) @@ -394,6 +402,7 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm, return 1; } +EXPORT_SYMBOL_NS_GPL(skx_get_dimm_info, EDAC_SKX_COMMON); int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, int chan, int dimmno, const char *mod_str) @@ -442,6 +451,7 @@ int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc, return (size == 0 || size == ~0ull) ? 0 : 1; } +EXPORT_SYMBOL_NS_GPL(skx_get_nvdimm_info, EDAC_SKX_COMMON); int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, const char *ctl_name, const char *mod_str, @@ -512,6 +522,7 @@ int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev, imc->mci = NULL; return rc; } +EXPORT_SYMBOL_NS_GPL(skx_register_mci, EDAC_SKX_COMMON); static void skx_unregister_mci(struct skx_imc *imc) { @@ -694,6 +705,7 @@ int skx_mce_check_error(struct notifier_block *nb, unsigned long val, mce->kflags |= MCE_HANDLED_EDAC; return NOTIFY_DONE; } +EXPORT_SYMBOL_NS_GPL(skx_mce_check_error, EDAC_SKX_COMMON); void skx_remove(void) { @@ -731,3 +743,8 @@ void skx_remove(void) kfree(d); } } +EXPORT_SYMBOL_NS_GPL(skx_remove, EDAC_SKX_COMMON); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tony Luck"); +MODULE_DESCRIPTION("MC Common Library for Intel server processors"); diff --git a/drivers/edac/skx_common.h b/drivers/edac/skx_common.h index 0cbadd3d2cd3..c0c174c101d2 100644 --- a/drivers/edac/skx_common.h +++ b/drivers/edac/skx_common.h @@ -178,8 +178,8 @@ typedef int (*get_dimm_config_f)(struct mem_ctl_info *mci, typedef bool (*skx_decode_f)(struct decoded_addr *res); typedef void (*skx_show_retry_log_f)(struct decoded_addr *res, char *msg, int len, bool scrub_err); -int __init skx_adxl_get(void); -void __exit skx_adxl_put(void); +int skx_adxl_get(void); +void skx_adxl_put(void); void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log); void skx_set_mem_cfg(bool mem_cfg_2lm); From patchwork Sat Nov 19 23:08:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23349 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp898762wrr; Sat, 19 Nov 2022 15:11:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf5CPyb9wdewm5yOwJ2ackeO8xcCQCtOie4aM+vi5vOpQrkAqZoq457q7JC+4I6rXAYe3aUq X-Received: by 2002:a63:595d:0:b0:476:f2b0:b318 with SMTP id j29-20020a63595d000000b00476f2b0b318mr12318774pgm.598.1668899462333; Sat, 19 Nov 2022 15:11:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899462; cv=none; d=google.com; s=arc-20160816; b=Qv2sRBIbMPbOXiV6JZGcTmIF/0QvhaGMEPalVpOKnQHXMh6PeVsvQlNSRnaGBSegzI s5fWZGF4ioNXkUJyYjRbRk336I5s9+HU4yMu8dIlXZAL52eTEUI7RSdJOykoCgii7E1A 2TQW0FtrdgqrEDI/swLKHdGbxZyyN+y/etSlDXjaU/LgHkk/kOeb5DkzPziDlt+RmPRY hgMRhq8Mey/E6x4uEK1JWkJE2SoR+WiRODz5WxSyEHFCXLiYDCQJpYnfC4WsU/wIyzwe G74q4qT4c3Q3ya8Typodxd7CoF6J6jDsIpk/YmNCygcjmu3yT0s2L03nw4J7i+mkP1gn iFAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :feedback-id:references:in-reply-to:message-id:subject:cc:from:to :dkim-signature:date; bh=zn0V2DT6W2z01KImfq/5Gwy2BxeJtWHzr6gc3StE15M=; b=E5b/TJfbMryV4IVN0euGhfvB90CtipwJTBueUbBUSQEV/YUSUCTQMpMKXgwdmVGqKF 7AzTpr4lsy4PUSYLlQAgbYjkIfeh+f+cic5dNiq/ZO0a+TrTsAl6pHoE3lEJ2XFhFbpf m5ss99+40zvJVXu4XJsRxwCYmnP12SOWZE5i4d1Gya5/iK2Ro+jt2ASECBV92B3LvqMI E2pjBzvvZBsM5XAfeYSrlnYkdhBbtBy7u0V9rIOHcCT3SvMLpZviGF4VvvM51bySDtVe 5+glFWHLfixtzoecEcQnQPRyZxtPVNz3T4oDXxDlJ6NW2rLNYvbz7IBTuXLkjt1n2agh IVVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=jYf7O9jF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ju17-20020a170903429100b001890f5957c4si2283746plb.353.2022.11.19.15.10.49; Sat, 19 Nov 2022 15:11:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=jYf7O9jF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234334AbiKSXIj (ORCPT + 99 others); Sat, 19 Nov 2022 18:08:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234794AbiKSXId (ORCPT ); Sat, 19 Nov 2022 18:08:33 -0500 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BE982ADB for ; Sat, 19 Nov 2022 15:08:31 -0800 (PST) Date: Sat, 19 Nov 2022 23:08:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899309; x=1669158509; bh=zn0V2DT6W2z01KImfq/5Gwy2BxeJtWHzr6gc3StE15M=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=jYf7O9jFrMZeXW86EsQISked7sIdxcuiotjHFn14vuvXN15oH9ckmhTKoHHHrGKQS WvAioU9V+6jK57z4Mq64rCtQ+K9Wdh825pM/BqnKeUL0ICnc/hkml1iTi4Ux8d3Odr zNmoiTTy8aQX2/6G6LXG71gUrts2nho+vGldh9kYWzDltOUnPeM4FR4YCjT0VqzdK6 0C68EUsI+/R45aOf+9HngV+zK7iGVzA+0C2Ya/ybkXF0neyLY1Ma+2lTbEPUJXEYBM efAguDDev0xXZs+X+cuV2DBj1TjV7AWM805c3JOyqvWvA9U7zH9rupP/pjtFj5XhKL lWeStGsiIStAw== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/18] platform/x86: int3472: fix object shared between several modules Message-ID: <20221119225650.1044591-12-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967922528962265?= X-GMAIL-MSGID: =?utf-8?q?1749967922528962265?= common.o is linked to both intel_skl_int3472_{discrete,tps68470}: > scripts/Makefile.build:252: ./drivers/platform/x86/intel/int3472/Makefile: > common.o is added to multiple modules: intel_skl_int3472_discrete > intel_skl_int3472_tps68470 Although both drivers share one Kconfig option (CONFIG_INTEL_SKL_INT3472), it's better to not link one object file into several modules (and/or vmlinux). Under certain circumstances, such can lead to the situation fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Introduce the new module, intel_skl_int3472_common, to provide the functions from common.o to both discrete and tps68470 drivers. This adds only 3 exports and doesn't provide any changes to the actual code. Fixes: a2f9fbc247ee ("platform/x86: int3472: Split into 2 drivers") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin --- drivers/platform/x86/intel/int3472/Makefile | 8 +++++--- drivers/platform/x86/intel/int3472/common.c | 8 ++++++++ drivers/platform/x86/intel/int3472/discrete.c | 2 ++ drivers/platform/x86/intel/int3472/tps68470.c | 2 ++ 4 files changed, 17 insertions(+), 3 deletions(-) -- 2.38.1 diff --git a/drivers/platform/x86/intel/int3472/Makefile b/drivers/platform/x86/intel/int3472/Makefile index cfec7784c5c9..53cc0e7db749 100644 --- a/drivers/platform/x86/intel/int3472/Makefile +++ b/drivers/platform/x86/intel/int3472/Makefile @@ -1,4 +1,6 @@ -obj-$(CONFIG_INTEL_SKL_INT3472) += intel_skl_int3472_discrete.o \ +obj-$(CONFIG_INTEL_SKL_INT3472) += intel_skl_int3472_common.o \ + intel_skl_int3472_discrete.o \ intel_skl_int3472_tps68470.o -intel_skl_int3472_discrete-y := discrete.o clk_and_regulator.o common.o -intel_skl_int3472_tps68470-y := tps68470.o tps68470_board_data.o common.o +intel_skl_int3472_common-y := common.o +intel_skl_int3472_discrete-y := discrete.o clk_and_regulator.o +intel_skl_int3472_tps68470-y := tps68470.o tps68470_board_data.o diff --git a/drivers/platform/x86/intel/int3472/common.c b/drivers/platform/x86/intel/int3472/common.c index 9db2bb0bbba4..bd573ff46610 100644 --- a/drivers/platform/x86/intel/int3472/common.c +++ b/drivers/platform/x86/intel/int3472/common.c @@ -2,6 +2,7 @@ /* Author: Dan Scally */ #include +#include #include #include "common.h" @@ -29,6 +30,7 @@ union acpi_object *skl_int3472_get_acpi_buffer(struct acpi_device *adev, char *i return obj; } +EXPORT_SYMBOL_NS_GPL(skl_int3472_get_acpi_buffer, INTEL_SKL_INT3472); int skl_int3472_fill_cldb(struct acpi_device *adev, struct int3472_cldb *cldb) { @@ -52,6 +54,7 @@ int skl_int3472_fill_cldb(struct acpi_device *adev, struct int3472_cldb *cldb) kfree(obj); return ret; } +EXPORT_SYMBOL_NS_GPL(skl_int3472_fill_cldb, INTEL_SKL_INT3472); /* sensor_adev_ret may be NULL, name_ret must not be NULL */ int skl_int3472_get_sensor_adev_and_name(struct device *dev, @@ -80,3 +83,8 @@ int skl_int3472_get_sensor_adev_and_name(struct device *dev, return ret; } +EXPORT_SYMBOL_NS_GPL(skl_int3472_get_sensor_adev_and_name, INTEL_SKL_INT3472); + +MODULE_DESCRIPTION("Intel SkyLake INT3472 Common Module"); +MODULE_AUTHOR("Daniel Scally "); +MODULE_LICENSE("GPL"); diff --git a/drivers/platform/x86/intel/int3472/discrete.c b/drivers/platform/x86/intel/int3472/discrete.c index 974a132db651..a1f3b593cea6 100644 --- a/drivers/platform/x86/intel/int3472/discrete.c +++ b/drivers/platform/x86/intel/int3472/discrete.c @@ -414,6 +414,8 @@ static struct platform_driver int3472_discrete = { }; module_platform_driver(int3472_discrete); +MODULE_IMPORT_NS(INTEL_SKL_INT3472); + MODULE_DESCRIPTION("Intel SkyLake INT3472 ACPI Discrete Device Driver"); MODULE_AUTHOR("Daniel Scally "); MODULE_LICENSE("GPL v2"); diff --git a/drivers/platform/x86/intel/int3472/tps68470.c b/drivers/platform/x86/intel/int3472/tps68470.c index 5b8d1a9620a5..3c983aa7731f 100644 --- a/drivers/platform/x86/intel/int3472/tps68470.c +++ b/drivers/platform/x86/intel/int3472/tps68470.c @@ -255,6 +255,8 @@ static struct i2c_driver int3472_tps68470 = { }; module_i2c_driver(int3472_tps68470); +MODULE_IMPORT_NS(INTEL_SKL_INT3472); + MODULE_DESCRIPTION("Intel SkyLake INT3472 ACPI TPS68470 Device Driver"); MODULE_AUTHOR("Daniel Scally "); MODULE_LICENSE("GPL v2"); From patchwork Sat Nov 19 23:08:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23350 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp898768wrr; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g13-20020a63520d000000b00476898c6c27si7023519pgb.524.2022.11.19.15.10.50; Sat, 19 Nov 2022 15:11:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=INXKOGkR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235298AbiKSXIy (ORCPT + 99 others); Sat, 19 Nov 2022 18:08:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235257AbiKSXIt (ORCPT ); Sat, 19 Nov 2022 18:08:49 -0500 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D01151A229; Sat, 19 Nov 2022 15:08:44 -0800 (PST) Date: Sat, 19 Nov 2022 23:08:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899323; x=1669158523; bh=6VdnaXou6NR0qAZ4WE3kmJZHL9lSgizWaAZ3d9S6Fq0=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=INXKOGkRr2fEvjSVnH7n1ELGTYSOahKgcJ1OEsqxDE12WVvYIATZ1d9ka42M9pldj vlkF9bLkDrDpSVKsRgceOF9oregCmZmEgKdy02ovi9AJLizJjDjrV4PXbXh2KjRZeB GxZKdTv7/ZNCfyKKWy2ynBIoTDaki2bxc3FGoE5b4R7DiuTQcG7dIwgbeD+NHp7ZV3 8bBbypXTZ45UqlAPmE59QGuLxOFpIIclsEbniBv4dRGCwbc7kwmt1BVNN+fFpTUCav kGv+SbOKmyeJffXLU9ZxCaIzB+TmnZH/djqrpQVTNcnx79SZuj5dJIMv6OjmG08g/u sqy8nmjZNGQVA== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/18] mtd: tests: fix object shared between several modules Message-ID: <20221119225650.1044591-13-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967923936807287?= X-GMAIL-MSGID: =?utf-8?q?1749967923936807287?= mtd_test.o is linked to 8(!) different test modules: > scripts/Makefile.build:252: ./drivers/mtd/tests/Makefile: mtd_test.o > is added to multiple modules: mtd_nandbiterrs mtd_oobtest mtd_pagetest > mtd_readtest mtd_speedtest mtd_stresstest mtd_subpagetest mtd_torturetest Although all of them share one Kconfig option (CONFIG_MTD_TESTS), it's better to not link one object file into several modules (and/or vmlinux). Under certain circumstances, such can lead to the situation fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). In this particular case, there's also no need to duplicate the very same object code 8 times. Convert mtd_test.o to a standalone module which will export its functions to the rest. Fixes: a995c792280d ("mtd: tests: rename sources in order to link a helper object") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin --- drivers/mtd/tests/Makefile | 17 +++++++++-------- drivers/mtd/tests/mtd_test.c | 9 +++++++++ drivers/mtd/tests/nandbiterrs.c | 2 ++ drivers/mtd/tests/oobtest.c | 2 ++ drivers/mtd/tests/pagetest.c | 2 ++ drivers/mtd/tests/readtest.c | 2 ++ drivers/mtd/tests/speedtest.c | 2 ++ drivers/mtd/tests/stresstest.c | 2 ++ drivers/mtd/tests/subpagetest.c | 2 ++ drivers/mtd/tests/torturetest.c | 2 ++ 10 files changed, 34 insertions(+), 8 deletions(-) -- 2.38.1 diff --git a/drivers/mtd/tests/Makefile b/drivers/mtd/tests/Makefile index 5de0378f90db..e3f86ed123ca 100644 --- a/drivers/mtd/tests/Makefile +++ b/drivers/mtd/tests/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_MTD_TESTS) += mtd_test.o obj-$(CONFIG_MTD_TESTS) += mtd_oobtest.o obj-$(CONFIG_MTD_TESTS) += mtd_pagetest.o obj-$(CONFIG_MTD_TESTS) += mtd_readtest.o @@ -9,11 +10,11 @@ obj-$(CONFIG_MTD_TESTS) += mtd_torturetest.o obj-$(CONFIG_MTD_TESTS) += mtd_nandecctest.o obj-$(CONFIG_MTD_TESTS) += mtd_nandbiterrs.o -mtd_oobtest-objs := oobtest.o mtd_test.o -mtd_pagetest-objs := pagetest.o mtd_test.o -mtd_readtest-objs := readtest.o mtd_test.o -mtd_speedtest-objs := speedtest.o mtd_test.o -mtd_stresstest-objs := stresstest.o mtd_test.o -mtd_subpagetest-objs := subpagetest.o mtd_test.o -mtd_torturetest-objs := torturetest.o mtd_test.o -mtd_nandbiterrs-objs := nandbiterrs.o mtd_test.o +mtd_oobtest-objs := oobtest.o +mtd_pagetest-objs := pagetest.o +mtd_readtest-objs := readtest.o +mtd_speedtest-objs := speedtest.o +mtd_stresstest-objs := stresstest.o +mtd_subpagetest-objs := subpagetest.o +mtd_torturetest-objs := torturetest.o +mtd_nandbiterrs-objs := nandbiterrs.o diff --git a/drivers/mtd/tests/mtd_test.c b/drivers/mtd/tests/mtd_test.c index c84250beffdc..93920a714315 100644 --- a/drivers/mtd/tests/mtd_test.c +++ b/drivers/mtd/tests/mtd_test.c @@ -25,6 +25,7 @@ int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum) return 0; } +EXPORT_SYMBOL_NS_GPL(mtdtest_erase_eraseblock, MTD_TESTS); static int is_block_bad(struct mtd_info *mtd, unsigned int ebnum) { @@ -57,6 +58,7 @@ int mtdtest_scan_for_bad_eraseblocks(struct mtd_info *mtd, unsigned char *bbt, return 0; } +EXPORT_SYMBOL_NS_GPL(mtdtest_scan_for_bad_eraseblocks, MTD_TESTS); int mtdtest_erase_good_eraseblocks(struct mtd_info *mtd, unsigned char *bbt, unsigned int eb, int ebcnt) @@ -75,6 +77,7 @@ int mtdtest_erase_good_eraseblocks(struct mtd_info *mtd, unsigned char *bbt, return 0; } +EXPORT_SYMBOL_NS_GPL(mtdtest_erase_good_eraseblocks, MTD_TESTS); int mtdtest_read(struct mtd_info *mtd, loff_t addr, size_t size, void *buf) { @@ -92,6 +95,7 @@ int mtdtest_read(struct mtd_info *mtd, loff_t addr, size_t size, void *buf) return err; } +EXPORT_SYMBOL_NS_GPL(mtdtest_read, MTD_TESTS); int mtdtest_write(struct mtd_info *mtd, loff_t addr, size_t size, const void *buf) @@ -107,3 +111,8 @@ int mtdtest_write(struct mtd_info *mtd, loff_t addr, size_t size, return err; } +EXPORT_SYMBOL_NS_GPL(mtdtest_write, MTD_TESTS); + +MODULE_DESCRIPTION("MTD test common module"); +MODULE_AUTHOR("Adrian Hunter"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/nandbiterrs.c b/drivers/mtd/tests/nandbiterrs.c index 98d7508f95b1..acf44edfca53 100644 --- a/drivers/mtd/tests/nandbiterrs.c +++ b/drivers/mtd/tests/nandbiterrs.c @@ -414,6 +414,8 @@ static void __exit mtd_nandbiterrs_exit(void) module_init(mtd_nandbiterrs_init); module_exit(mtd_nandbiterrs_exit); +MODULE_IMPORT_NS(MTD_TESTS); + MODULE_DESCRIPTION("NAND bit error recovery test"); MODULE_AUTHOR("Iwo Mergler"); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/oobtest.c b/drivers/mtd/tests/oobtest.c index 13fed398937e..da4efcdd59b2 100644 --- a/drivers/mtd/tests/oobtest.c +++ b/drivers/mtd/tests/oobtest.c @@ -728,6 +728,8 @@ static void __exit mtd_oobtest_exit(void) } module_exit(mtd_oobtest_exit); +MODULE_IMPORT_NS(MTD_TESTS); + MODULE_DESCRIPTION("Out-of-band test module"); MODULE_AUTHOR("Adrian Hunter"); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/pagetest.c b/drivers/mtd/tests/pagetest.c index 8eb40b6e6dfa..ac2bcc76b402 100644 --- a/drivers/mtd/tests/pagetest.c +++ b/drivers/mtd/tests/pagetest.c @@ -456,6 +456,8 @@ static void __exit mtd_pagetest_exit(void) } module_exit(mtd_pagetest_exit); +MODULE_IMPORT_NS(MTD_TESTS); + MODULE_DESCRIPTION("NAND page test"); MODULE_AUTHOR("Adrian Hunter"); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/readtest.c b/drivers/mtd/tests/readtest.c index 99670ef91f2b..7e01dbc1e8ca 100644 --- a/drivers/mtd/tests/readtest.c +++ b/drivers/mtd/tests/readtest.c @@ -210,6 +210,8 @@ static void __exit mtd_readtest_exit(void) } module_exit(mtd_readtest_exit); +MODULE_IMPORT_NS(MTD_TESTS); + MODULE_DESCRIPTION("Read test module"); MODULE_AUTHOR("Adrian Hunter"); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/speedtest.c b/drivers/mtd/tests/speedtest.c index 075bce32caa5..58f3701d65f2 100644 --- a/drivers/mtd/tests/speedtest.c +++ b/drivers/mtd/tests/speedtest.c @@ -413,6 +413,8 @@ static void __exit mtd_speedtest_exit(void) } module_exit(mtd_speedtest_exit); +MODULE_IMPORT_NS(MTD_TESTS); + MODULE_DESCRIPTION("Speed test module"); MODULE_AUTHOR("Adrian Hunter"); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/stresstest.c b/drivers/mtd/tests/stresstest.c index 75b6ddc5dc4d..341d7cc86d89 100644 --- a/drivers/mtd/tests/stresstest.c +++ b/drivers/mtd/tests/stresstest.c @@ -227,6 +227,8 @@ static void __exit mtd_stresstest_exit(void) } module_exit(mtd_stresstest_exit); +MODULE_IMPORT_NS(MTD_TESTS); + MODULE_DESCRIPTION("Stress test module"); MODULE_AUTHOR("Adrian Hunter"); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/subpagetest.c b/drivers/mtd/tests/subpagetest.c index 05250a080139..87ee2a5c518a 100644 --- a/drivers/mtd/tests/subpagetest.c +++ b/drivers/mtd/tests/subpagetest.c @@ -432,6 +432,8 @@ static void __exit mtd_subpagetest_exit(void) } module_exit(mtd_subpagetest_exit); +MODULE_IMPORT_NS(MTD_TESTS); + MODULE_DESCRIPTION("Subpage test module"); MODULE_AUTHOR("Adrian Hunter"); MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/tests/torturetest.c b/drivers/mtd/tests/torturetest.c index 841689b4d86d..2de770f18724 100644 --- a/drivers/mtd/tests/torturetest.c +++ b/drivers/mtd/tests/torturetest.c @@ -475,6 +475,8 @@ static int countdiffs(unsigned char *buf, unsigned char *check_buf, return first; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i12-20020a639d0c000000b0043c1cb75c22si7528196pgd.333.2022.11.19.15.11.27; Sat, 19 Nov 2022 15:11:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=WCecC2ln; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235271AbiKSXJ2 (ORCPT + 99 others); Sat, 19 Nov 2022 18:09:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235369AbiKSXJL (ORCPT ); Sat, 19 Nov 2022 18:09:11 -0500 Received: from mail-4316.protonmail.ch (mail-4316.protonmail.ch [185.70.43.16]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8575A1A387; Sat, 19 Nov 2022 15:09:07 -0800 (PST) Date: Sat, 19 Nov 2022 23:09:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899345; x=1669158545; bh=9qGKLVCjbHAnH91XpqmRTavbfWbbwNUr7AChPSqtfkk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=WCecC2ln5RP+48I8SIV0O0Fq3LMH3WSUI03jOJLR+06GIB7qPmWjWYfLY26fBM/CW Gk0cN2crtbQiGm180ZtSKFFNEsOUuyhsIKee05mLt2p63kIkNJEjxYWcZ6LLy3fFO5 AOuH2sEbAYhqfjRzPMzyxOeBQwqXtWKmNRJF13iXV1/2d8norveB12DLtdbi0WIrft 6Gw1Bb3OXdgE7CIUrrK6AARwh3IcRQ6fbPFMLnWqhpjRvEMUe5YyzRFngc8gmLsPN+ RC+gHksfZXJCNyBRPXj7Hu3QC1o4n+j+KbjlOPepCKVERJ6uxcpdiep1BW8i3R10zP WwiZ4OYmWxhkQ== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/18] crypto: octeontx2: fix objects shared between several modules Message-ID: <20221119225650.1044591-14-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967961778276857?= X-GMAIL-MSGID: =?utf-8?q?1749967961778276857?= cn10k_cpt.o, otx2_cptlf.o and otx2_cpt_mbox_common.o are linked into both rvu_cptpf and rvu_cptvf modules: > scripts/Makefile.build:252: ./drivers/crypto/marvell/octeontx2/Makefile: > cn10k_cpt.o is added to multiple modules: rvu_cptpf rvu_cptvf > scripts/Makefile.build:252: ./drivers/crypto/marvell/octeontx2/Makefile: > otx2_cptlf.o is added to multiple modules: rvu_cptpf rvu_cptvf > scripts/Makefile.build:252: ./drivers/crypto/marvell/octeontx2/Makefile: > otx2_cpt_mbox_common.o is added to multiple modules: rvu_cptpf rvu_cptvf Despite they're build under the same Kconfig option (CONFIG_CRYPTO_DEV_OCTEONTX2_CPT), it's better do link the common code into a standalone module and export the shared functions. Under certain circumstances, this can lead to the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). Plus, those three common object files are relatively big to duplicate them several times. Introduce the new module, rvu_cptcommon, to provide the common functions to both modules. Fixes: 19d8e8c7be15 ("crypto: octeontx2 - add virtual function driver support") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin Reviewed-by: Masahiro Yamada --- drivers/crypto/marvell/octeontx2/Makefile | 11 +++++------ drivers/crypto/marvell/octeontx2/cn10k_cpt.c | 9 +++++++-- drivers/crypto/marvell/octeontx2/cn10k_cpt.h | 2 -- drivers/crypto/marvell/octeontx2/otx2_cpt_common.h | 2 -- .../marvell/octeontx2/otx2_cpt_mbox_common.c | 14 ++++++++++++-- drivers/crypto/marvell/octeontx2/otx2_cptlf.c | 11 +++++++++++ drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c | 2 ++ drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c | 2 ++ 8 files changed, 39 insertions(+), 14 deletions(-) -- 2.38.1 diff --git a/drivers/crypto/marvell/octeontx2/Makefile b/drivers/crypto/marvell/octeontx2/Makefile index 965297e96954..f0f2942c1d27 100644 --- a/drivers/crypto/marvell/octeontx2/Makefile +++ b/drivers/crypto/marvell/octeontx2/Makefile @@ -1,11 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += rvu_cptpf.o rvu_cptvf.o +obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += rvu_cptcommon.o rvu_cptpf.o rvu_cptvf.o +rvu_cptcommon-objs := cn10k_cpt.o otx2_cptlf.o otx2_cpt_mbox_common.o rvu_cptpf-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \ - otx2_cpt_mbox_common.o otx2_cptpf_ucode.o otx2_cptlf.o \ - cn10k_cpt.o otx2_cpt_devlink.o -rvu_cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o otx2_cptlf.o \ - otx2_cpt_mbox_common.o otx2_cptvf_reqmgr.o \ - otx2_cptvf_algs.o cn10k_cpt.o + otx2_cptpf_ucode.o otx2_cpt_devlink.o +rvu_cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o \ + otx2_cptvf_reqmgr.o otx2_cptvf_algs.o ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c index 1499ef75b5c2..93d22b328991 100644 --- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.c +++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.c @@ -7,6 +7,9 @@ #include "otx2_cptlf.h" #include "cn10k_cpt.h" +static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num, + struct otx2_cptlf_info *lf); + static struct cpt_hw_ops otx2_hw_ops = { .send_cmd = otx2_cpt_send_cmd, .cpt_get_compcode = otx2_cpt_get_compcode, @@ -19,8 +22,8 @@ static struct cpt_hw_ops cn10k_hw_ops = { .cpt_get_uc_compcode = cn10k_cpt_get_uc_compcode, }; -void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num, - struct otx2_cptlf_info *lf) +static void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num, + struct otx2_cptlf_info *lf) { void __iomem *lmtline = lf->lmtline; u64 val = (lf->slot & 0x7FF); @@ -68,6 +71,7 @@ int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf) return 0; } +EXPORT_SYMBOL_NS_GPL(cn10k_cptpf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT); int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf) { @@ -91,3 +95,4 @@ int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf) return 0; } +EXPORT_SYMBOL_NS_GPL(cn10k_cptvf_lmtst_init, CRYPTO_DEV_OCTEONTX2_CPT); diff --git a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h index c091392b47e0..aaefc7e38e06 100644 --- a/drivers/crypto/marvell/octeontx2/cn10k_cpt.h +++ b/drivers/crypto/marvell/octeontx2/cn10k_cpt.h @@ -28,8 +28,6 @@ static inline u8 otx2_cpt_get_uc_compcode(union otx2_cpt_res_s *result) return ((struct cn9k_cpt_res_s *)result)->uc_compcode; } -void cn10k_cpt_send_cmd(union otx2_cpt_inst_s *cptinst, u32 insts_num, - struct otx2_cptlf_info *lf); int cn10k_cptpf_lmtst_init(struct otx2_cptpf_dev *cptpf); int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf); diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h index 5012b7e669f0..6019066a6451 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_common.h @@ -145,8 +145,6 @@ int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev); int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev); -int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, - u64 reg, u64 *val, int blkaddr); int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, u64 reg, u64 val, int blkaddr); int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c b/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c index a317319696ef..115997475beb 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_mbox_common.c @@ -19,6 +19,7 @@ int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) } return ret; } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_send_mbox_msg, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) { @@ -36,14 +37,17 @@ int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev) return otx2_cpt_send_mbox_msg(mbox, pdev); } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_send_ready_msg, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev) { return otx2_cpt_send_mbox_msg(mbox, pdev); } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_send_af_reg_requests, CRYPTO_DEV_OCTEONTX2_CPT); -int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, - u64 reg, u64 *val, int blkaddr) +static int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, + struct pci_dev *pdev, u64 reg, + u64 *val, int blkaddr) { struct cpt_rd_wr_reg_msg *reg_msg; @@ -91,6 +95,7 @@ int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, return 0; } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_add_write_af_reg, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, u64 reg, u64 *val, int blkaddr) @@ -103,6 +108,7 @@ int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, return otx2_cpt_send_mbox_msg(mbox, pdev); } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_read_af_reg, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, u64 reg, u64 val, int blkaddr) @@ -115,6 +121,7 @@ int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev, return otx2_cpt_send_mbox_msg(mbox, pdev); } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_write_af_reg, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs) { @@ -170,6 +177,7 @@ int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs) return ret; } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_detach_rsrcs_msg, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs) { @@ -202,6 +210,7 @@ int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs) } return ret; } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_msix_offset_msg, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox) { @@ -216,3 +225,4 @@ int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox) return otx2_mbox_check_rsp_msgs(mbox, 0); } +EXPORT_SYMBOL_NS_GPL(otx2_cpt_sync_mbox_msg, CRYPTO_DEV_OCTEONTX2_CPT); diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.c b/drivers/crypto/marvell/octeontx2/otx2_cptlf.c index c8350fcd60fa..fc484cb05c0f 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.c @@ -274,6 +274,8 @@ void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs) } cptlf_disable_intrs(lfs); } +EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_interrupts, + CRYPTO_DEV_OCTEONTX2_CPT); static int cptlf_do_register_interrrupts(struct otx2_cptlfs_info *lfs, int lf_num, int irq_offset, @@ -321,6 +323,7 @@ int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs) otx2_cptlf_unregister_interrupts(lfs); return ret; } +EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_interrupts, CRYPTO_DEV_OCTEONTX2_CPT); void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs) { @@ -334,6 +337,7 @@ void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs) free_cpumask_var(lfs->lf[slot].affinity_mask); } } +EXPORT_SYMBOL_NS_GPL(otx2_cptlf_free_irqs_affinity, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs) { @@ -366,6 +370,7 @@ int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs) otx2_cptlf_free_irqs_affinity(lfs); return ret; } +EXPORT_SYMBOL_NS_GPL(otx2_cptlf_set_irqs_affinity, CRYPTO_DEV_OCTEONTX2_CPT); int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri, int lfs_num) @@ -422,6 +427,7 @@ int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri, lfs->lfs_num = 0; return ret; } +EXPORT_SYMBOL_NS_GPL(otx2_cptlf_init, CRYPTO_DEV_OCTEONTX2_CPT); void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs) { @@ -431,3 +437,8 @@ void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs) /* Send request to detach LFs */ otx2_cpt_detach_rsrcs_msg(lfs); } +EXPORT_SYMBOL_NS_GPL(otx2_cptlf_shutdown, CRYPTO_DEV_OCTEONTX2_CPT); + +MODULE_AUTHOR("Marvell"); +MODULE_DESCRIPTION("Marvell RVU CPT Common module"); +MODULE_LICENSE("GPL"); diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c index a402ccfac557..ddf6e913c1c4 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c @@ -831,6 +831,8 @@ static struct pci_driver otx2_cpt_pci_driver = { module_pci_driver(otx2_cpt_pci_driver); +MODULE_IMPORT_NS(CRYPTO_DEV_OCTEONTX2_CPT); + MODULE_AUTHOR("Marvell"); MODULE_DESCRIPTION(OTX2_CPT_DRV_STRING); MODULE_LICENSE("GPL v2"); diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c index 3411e664cf50..392e9fee05e8 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c @@ -429,6 +429,8 @@ static struct pci_driver otx2_cptvf_pci_driver = { module_pci_driver(otx2_cptvf_pci_driver); +MODULE_IMPORT_NS(CRYPTO_DEV_OCTEONTX2_CPT); + MODULE_AUTHOR("Marvell"); MODULE_DESCRIPTION("Marvell RVU CPT Virtual Function Driver"); MODULE_LICENSE("GPL v2"); From patchwork Sat Nov 19 23:09:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23351 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp898889wrr; Sat, 19 Nov 2022 15:11:26 -0800 (PST) X-Google-Smtp-Source: AA0mqf6wk+TVTwfP1sSJQv2rdlXj5P7ycPHwNXbxCgxk9rMeBmOGp/OOj6LpAVGQ4mVtQfFCHzIe X-Received: by 2002:a63:1618:0:b0:476:e4fd:94b8 with SMTP id w24-20020a631618000000b00476e4fd94b8mr12399209pgl.191.1668899486407; Sat, 19 Nov 2022 15:11:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668899486; cv=none; d=google.com; s=arc-20160816; b=jADG/nhgNfxamfrZXQQkCvyGmnfvoOlLZ20xq4eXbWmyzUdF87muBlzCTyEovysfsS V/AcKTLct7ETkq12pE7T3lFBnFs/QTQGEFULc6MOgrYwMuDHEytO1CJ7IpkmlHrOgZp7 RFLD8IZu+Q8QdAWHWDNeZ1ORno8ECG6AR1kt2DFnfbK74PlngyLy1p3Na2AkYWBemHSR AWzxMup0BR7VNZjgMx2Jr6dn9OxyAf6TE6r7PcyfwosYrsxCOFim6MAls97kgRgZTWtN Xc6HblPMzQhpHx+n6R0OkOKrKw3DWQFqB/06AzGHBtfZcs0jt8y8C1MOVC6TRb44DEDq ZBNg== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m3-20020a170902db0300b001872cd80411si8329977plx.193.2022.11.19.15.11.13; Sat, 19 Nov 2022 15:11:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=iZy0jG6A; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233670AbiKSXJr (ORCPT + 99 others); Sat, 19 Nov 2022 18:09:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235311AbiKSXJf (ORCPT ); Sat, 19 Nov 2022 18:09:35 -0500 Received: from mail-40134.protonmail.ch (mail-40134.protonmail.ch [185.70.40.134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5EE91A239 for ; Sat, 19 Nov 2022 15:09:34 -0800 (PST) Date: Sat, 19 Nov 2022 23:09:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899373; x=1669158573; bh=MAgRAh4SDfMEPc3zacP7lfPCdvWAEe3d5ZwVSRUvOuA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=iZy0jG6AkPETIeHEmKHqgjE6t1Q+kVlflbMPgugjFGCbpEBsYs6e7T8XI0dLJ6kJV xS89AcZITBR2RDXUo0/sxT1ekJ8nna+ZChqg5QgMQPF88+VHZ+NrhXK1ZJP0vU+QwR 8oWyoEYw3BZJe/K3GNY6Tlpa2mMheAfUboSTYGtaAKuXvEGmLg0ZHLOemddovtvEF0 VA9KZ9tkSxzGlSwjWBAQNFTfhpNuywVhJvvqwObruB/CRB1M+FqXZ5kSGW67syu/cO 7dH5364Wb2/svC+oBdNlfh7UkQWEZd6pceCI3Mit/GSOfuk0oPlEBzNRbS29S4wEOn 8y8zXZokmhmaw== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/18] dsa: ocelot: fix mixed module-builtin object Message-ID: <20221119225650.1044591-15-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967947650096102?= X-GMAIL-MSGID: =?utf-8?q?1749967947650096102?= With CONFIG_NET_DSA_MSCC_FELIX=m and CONFIG_NET_DSA_MSCC_SEVILLE=y (or vice versa), felix.o are linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). There's also no need to duplicate relatively big piece of object code into two modules. Introduce the new module, mscc_core, to provide the common functions to both mscc_felix and mscc_seville. Fixes: d60bc62de4ae ("net: dsa: seville: build as separate module") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin --- drivers/net/dsa/ocelot/Kconfig | 18 ++++++++++-------- drivers/net/dsa/ocelot/Makefile | 12 +++++------- drivers/net/dsa/ocelot/felix.c | 6 ++++++ drivers/net/dsa/ocelot/felix_vsc9959.c | 2 ++ drivers/net/dsa/ocelot/seville_vsc9953.c | 2 ++ 5 files changed, 25 insertions(+), 15 deletions(-) -- 2.38.1 diff --git a/drivers/net/dsa/ocelot/Kconfig b/drivers/net/dsa/ocelot/Kconfig index 08db9cf76818..59845274e374 100644 --- a/drivers/net/dsa/ocelot/Kconfig +++ b/drivers/net/dsa/ocelot/Kconfig @@ -1,4 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only + +config NET_DSA_MSCC_CORE + tristate + select MSCC_OCELOT_SWITCH_LIB + select NET_DSA_TAG_OCELOT_8021Q + select NET_DSA_TAG_OCELOT + select PCS_LYNX + config NET_DSA_MSCC_FELIX tristate "Ocelot / Felix Ethernet switch support" depends on NET_DSA && PCI @@ -7,11 +15,8 @@ config NET_DSA_MSCC_FELIX depends on HAS_IOMEM depends on PTP_1588_CLOCK_OPTIONAL depends on NET_SCH_TAPRIO || NET_SCH_TAPRIO=n - select MSCC_OCELOT_SWITCH_LIB - select NET_DSA_TAG_OCELOT_8021Q - select NET_DSA_TAG_OCELOT + select NET_DSA_MSCC_CORE select FSL_ENETC_MDIO - select PCS_LYNX help This driver supports the VSC9959 (Felix) switch, which is embedded as a PCIe function of the NXP LS1028A ENETC RCiEP. @@ -22,11 +27,8 @@ config NET_DSA_MSCC_SEVILLE depends on NET_VENDOR_MICROSEMI depends on HAS_IOMEM depends on PTP_1588_CLOCK_OPTIONAL + select NET_DSA_MSCC_CORE select MDIO_MSCC_MIIM - select MSCC_OCELOT_SWITCH_LIB - select NET_DSA_TAG_OCELOT_8021Q - select NET_DSA_TAG_OCELOT - select PCS_LYNX help This driver supports the VSC9953 (Seville) switch, which is embedded as a platform device on the NXP T1040 SoC. diff --git a/drivers/net/dsa/ocelot/Makefile b/drivers/net/dsa/ocelot/Makefile index f6dd131e7491..f8c74b59b996 100644 --- a/drivers/net/dsa/ocelot/Makefile +++ b/drivers/net/dsa/ocelot/Makefile @@ -1,11 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_NET_DSA_MSCC_CORE) += mscc_core.o obj-$(CONFIG_NET_DSA_MSCC_FELIX) += mscc_felix.o obj-$(CONFIG_NET_DSA_MSCC_SEVILLE) += mscc_seville.o -mscc_felix-objs := \ - felix.o \ - felix_vsc9959.o - -mscc_seville-objs := \ - felix.o \ - seville_vsc9953.o +mscc_core-objs := felix.o +mscc_felix-objs := felix_vsc9959.o +mscc_seville-objs := seville_vsc9953.o diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index dd3a18cc89dd..f9d0a24ebc3a 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -2112,6 +2112,7 @@ const struct dsa_switch_ops felix_switch_ops = { .port_set_host_flood = felix_port_set_host_flood, .port_change_master = felix_port_change_master, }; +EXPORT_SYMBOL_NS_GPL(felix_switch_ops, NET_DSA_MSCC_CORE); struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) { @@ -2123,6 +2124,7 @@ struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) return dsa_to_port(ds, port)->slave; } +EXPORT_SYMBOL_NS_GPL(felix_port_to_netdev, NET_DSA_MSCC_CORE); int felix_netdev_to_port(struct net_device *dev) { @@ -2134,3 +2136,7 @@ int felix_netdev_to_port(struct net_device *dev) return dp->index; } +EXPORT_SYMBOL_NS_GPL(felix_netdev_to_port, NET_DSA_MSCC_CORE); + +MODULE_DESCRIPTION("MSCC Switch driver core"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c index 26a35ae322d1..52c8bff79fa3 100644 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c @@ -2736,5 +2736,7 @@ static struct pci_driver felix_vsc9959_pci_driver = { }; module_pci_driver(felix_vsc9959_pci_driver); +MODULE_IMPORT_NS(NET_DSA_MSCC_CORE); + MODULE_DESCRIPTION("Felix Switch driver"); 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z9-20020a170902ccc900b00178386d88c6si7527482ple.186.2022.11.19.15.11.24; Sat, 19 Nov 2022 15:11:37 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=TdhooLtY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235305AbiKSXKO (ORCPT + 99 others); Sat, 19 Nov 2022 18:10:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235377AbiKSXJ6 (ORCPT ); Sat, 19 Nov 2022 18:09:58 -0500 Received: from mail-40134.protonmail.ch (mail-40134.protonmail.ch [185.70.40.134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47528101FC; Sat, 19 Nov 2022 15:09:57 -0800 (PST) Date: Sat, 19 Nov 2022 23:09:51 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899395; x=1669158595; bh=wNP0UQpU7yrDZr4V2xlMMmH7hWXhkAKdC5HFrg14b2U=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=TdhooLtYMTOiXSgX6a8vur7U8YSfc54R+aNkyLrZOxGhW9ZmtfU2kNxaQOmVntH5M RaFWicXh4WLlwJG9nmjBzB2F0cFaqn8BIIKyCUGv/leCqern8weFAm0prQk5TEMji/ qpwLjthLgEeDPTus9GXPDGf+Mz2eE4Q32y5S6KxXvsSHmjn2i34UjgegVmBRo5B7mu V9IvBd9WD/RDTR7XV8B121h4KfQI/Zqlx1h6izDtKhhhgoO6NH6aEgbxDLUQt0kEOB 7fuYsxpgTk8poLjQMJnSY0wit5xC1Lc+taQrCH6InXHhoJocSMB4GKTeMAbUZSAozo jTSk3B04DZlXg== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/18] net: dpaa2: fix mixed module-builtin object Message-ID: <20221119225650.1044591-16-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749967958964456547?= X-GMAIL-MSGID: =?utf-8?q?1749967958964456547?= With CONFIG_FSL_DPAA2_ETH=m and CONFIG_FSL_DPAA2_SWITCH=y (or vice versa), dpaa2-mac.o and dpmac.o are linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). There's also no need to duplicate relatively big piece of object code into two modules. Introduce the new module, fsl-dpaa2-mac, to provide the common functions to both fsl-dpaa2-eth and fsl-dpaa2-switch. Misc: constify and shrink @dpaa2_mac_ethtool_stats while at it. Fixes: 84cba72956fd ("dpaa2-switch: integrate the MAC endpoint support") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin Reviewed-by: Masahiro Yamada --- drivers/net/ethernet/freescale/dpaa2/Kconfig | 6 ++++++ drivers/net/ethernet/freescale/dpaa2/Makefile | 6 ++++-- drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c | 2 ++ drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 15 ++++++++++++++- .../net/ethernet/freescale/dpaa2/dpaa2-switch.c | 2 ++ 5 files changed, 28 insertions(+), 3 deletions(-) -- 2.38.1 diff --git a/drivers/net/ethernet/freescale/dpaa2/Kconfig b/drivers/net/ethernet/freescale/dpaa2/Kconfig index d029b69c3f18..54c388f25c43 100644 --- a/drivers/net/ethernet/freescale/dpaa2/Kconfig +++ b/drivers/net/ethernet/freescale/dpaa2/Kconfig @@ -1,7 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only + +config FSL_DPAA2_MAC + tristate + config FSL_DPAA2_ETH tristate "Freescale DPAA2 Ethernet" depends on FSL_MC_BUS && FSL_MC_DPIO + select FSL_DPAA2_MAC select PHYLINK select PCS_LYNX select FSL_XGMAC_MDIO @@ -34,6 +39,7 @@ config FSL_DPAA2_SWITCH tristate "Freescale DPAA2 Ethernet Switch" depends on BRIDGE || BRIDGE=n depends on NET_SWITCHDEV + select FSL_DPAA2_MAC help Driver for Freescale DPAA2 Ethernet Switch. This driver manages switch objects discovered on the Freeescale MC bus. diff --git a/drivers/net/ethernet/freescale/dpaa2/Makefile b/drivers/net/ethernet/freescale/dpaa2/Makefile index 3d9842af7f10..9dbe2273c9a1 100644 --- a/drivers/net/ethernet/freescale/dpaa2/Makefile +++ b/drivers/net/ethernet/freescale/dpaa2/Makefile @@ -4,14 +4,16 @@ # obj-$(CONFIG_FSL_DPAA2_ETH) += fsl-dpaa2-eth.o +obj-$(CONFIG_FSL_DPAA2_MAC) += fsl-dpaa2-mac.o obj-$(CONFIG_FSL_DPAA2_PTP_CLOCK) += fsl-dpaa2-ptp.o obj-$(CONFIG_FSL_DPAA2_SWITCH) += fsl-dpaa2-switch.o -fsl-dpaa2-eth-objs := dpaa2-eth.o dpaa2-ethtool.o dpni.o dpaa2-mac.o dpmac.o dpaa2-eth-devlink.o +fsl-dpaa2-eth-objs := dpaa2-eth.o dpaa2-ethtool.o dpni.o dpaa2-eth-devlink.o fsl-dpaa2-eth-${CONFIG_FSL_DPAA2_ETH_DCB} += dpaa2-eth-dcb.o fsl-dpaa2-eth-${CONFIG_DEBUG_FS} += dpaa2-eth-debugfs.o +fsl-dpaa2-mac-objs := dpaa2-mac.o dpmac.o fsl-dpaa2-ptp-objs := dpaa2-ptp.o dprtc.o -fsl-dpaa2-switch-objs := dpaa2-switch.o dpaa2-switch-ethtool.o dpsw.o dpaa2-switch-flower.o dpaa2-mac.o dpmac.o +fsl-dpaa2-switch-objs := dpaa2-switch.o dpaa2-switch-ethtool.o dpsw.o dpaa2-switch-flower.o # Needed by the tracing framework CFLAGS_dpaa2-eth.o := -I$(src) diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c index 8d029addddad..876c3ed6e2c5 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c @@ -28,6 +28,8 @@ #define CREATE_TRACE_POINTS #include "dpaa2-eth-trace.h" +MODULE_IMPORT_NS(FSL_DPAA2_MAC); + MODULE_LICENSE("Dual BSD/GPL"); MODULE_AUTHOR("Freescale Semiconductor, Inc"); MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver"); diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c index 49ff85633783..dc2c7cde5435 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c @@ -339,12 +339,14 @@ void dpaa2_mac_start(struct dpaa2_mac *mac) if (mac->serdes_phy) phy_power_on(mac->serdes_phy); } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_start, FSL_DPAA2_MAC); void dpaa2_mac_stop(struct dpaa2_mac *mac) { if (mac->serdes_phy) phy_power_off(mac->serdes_phy); } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_stop, FSL_DPAA2_MAC); int dpaa2_mac_connect(struct dpaa2_mac *mac) { @@ -435,6 +437,7 @@ int dpaa2_mac_connect(struct dpaa2_mac *mac) return err; } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_connect, FSL_DPAA2_MAC); void dpaa2_mac_disconnect(struct dpaa2_mac *mac) { @@ -447,6 +450,7 @@ void dpaa2_mac_disconnect(struct dpaa2_mac *mac) of_phy_put(mac->serdes_phy); mac->serdes_phy = NULL; } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_disconnect, FSL_DPAA2_MAC); int dpaa2_mac_open(struct dpaa2_mac *mac) { @@ -495,6 +499,7 @@ int dpaa2_mac_open(struct dpaa2_mac *mac) dpmac_close(mac->mc_io, 0, dpmac_dev->mc_handle); return err; } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_open, FSL_DPAA2_MAC); void dpaa2_mac_close(struct dpaa2_mac *mac) { @@ -504,8 +509,9 @@ void dpaa2_mac_close(struct dpaa2_mac *mac) if (mac->fw_node) fwnode_handle_put(mac->fw_node); } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_close, FSL_DPAA2_MAC); -static char dpaa2_mac_ethtool_stats[][ETH_GSTRING_LEN] = { +static const char * const dpaa2_mac_ethtool_stats[] = { [DPMAC_CNT_ING_ALL_FRAME] = "[mac] rx all frames", [DPMAC_CNT_ING_GOOD_FRAME] = "[mac] rx frames ok", [DPMAC_CNT_ING_ERR_FRAME] = "[mac] rx frame errors", @@ -542,6 +548,7 @@ int dpaa2_mac_get_sset_count(void) { return DPAA2_MAC_NUM_STATS; } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_get_sset_count, FSL_DPAA2_MAC); void dpaa2_mac_get_strings(u8 *data) { @@ -553,6 +560,7 @@ void dpaa2_mac_get_strings(u8 *data) p += ETH_GSTRING_LEN; } } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_get_strings, FSL_DPAA2_MAC); void dpaa2_mac_get_ethtool_stats(struct dpaa2_mac *mac, u64 *data) { @@ -572,3 +580,8 @@ void dpaa2_mac_get_ethtool_stats(struct dpaa2_mac *mac, u64 *data) *(data + i) = value; } } +EXPORT_SYMBOL_NS_GPL(dpaa2_mac_get_ethtool_stats, FSL_DPAA2_MAC); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("Freescale Semiconductor, Inc"); +MODULE_DESCRIPTION("Freescale DPAA2 MAC Driver"); diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c index 2b5909fa93cf..fccbaf75b512 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-switch.c @@ -3534,5 +3534,7 @@ static void __exit dpaa2_switch_driver_exit(void) module_init(dpaa2_switch_driver_init); module_exit(dpaa2_switch_driver_exit); +MODULE_IMPORT_NS(FSL_DPAA2_MAC); + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("DPAA2 Ethernet Switch Driver"); From patchwork Sat Nov 19 23:10:12 2022 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d62-20020a633641000000b00476de006c16si7548926pga.723.2022.11.19.15.12.22; Sat, 19 Nov 2022 15:12:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=CLfIVcEN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235369AbiKSXKt (ORCPT + 99 others); Sat, 19 Nov 2022 18:10:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235351AbiKSXKb (ORCPT ); Sat, 19 Nov 2022 18:10:31 -0500 Received: from mail-40134.protonmail.ch (mail-40134.protonmail.ch [185.70.40.134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F1A71A215 for ; Sat, 19 Nov 2022 15:10:27 -0800 (PST) Date: Sat, 19 Nov 2022 23:10:12 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899426; x=1669158626; bh=dLpVCSQ868jTQI0UEQak6Ixr4hg4QGS4MH1h5Bp37Lo=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=CLfIVcENLVIOE6aagoAfxqzXNsAY/G0/si5BoaVMxMlPKMHrLyYq5ht21MAj0YUn/ pLshkIokAYzyq5LpJBJgD2BI134jO05uXsBPglcnfzlM7QGdleh9ChEJK1RB4qadn+ Rnvhtyg7wB+KDZ23EE86AmWhvEs41O29Zul1Asja7tEEAtdvLFr5OGyApfnyH8rsWS DTkZfnPiwlIvkSYb3zYjn7ZA3nS9aCUsoAH13rOzMc9gtVICNastFpb21M8DW78TFM vIBoyZr1BVh8yUgZOkgIjZWEEZ4eHGz4KtMhSN1SBhL9sQbUwKA5XzzZSD/xr/Jm1z 8qlb5S1rFJMtA== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/18] net: hns3: fix mixed module-builtin object Message-ID: <20221119225650.1044591-17-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749968019707356308?= X-GMAIL-MSGID: =?utf-8?q?1749968019707356308?= With CONFIG_HNS3_HCLGE=y and CONFIG_HNS3_HCLGEVF=m, objects from hns3/hns3_common are linked into a module and into vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). There's also no need to duplicate such big piece of object code into two modules. Introduce the new module, hclge_common, to provide the common functions to both hclge and hclgevf. Fixes: eaa5607db377 ("net: hns3: refactor hclge_cmd_send with new hclge_comm_cmd_send API") Fixes: 1bfd6682e9b5 ("net: hns3: create new set of common rss get APIs for PF and VF rss module") Fixes: 287db5c40d15 ("net: hns3: create new set of common tqp stats APIs for PF and VF reuse") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin --- drivers/net/ethernet/hisilicon/Kconfig | 5 ++++ drivers/net/ethernet/hisilicon/hns3/Makefile | 13 +++++---- .../hns3/hns3_common/hclge_comm_cmd.c | 27 +++++++++++++------ .../hns3/hns3_common/hclge_comm_cmd.h | 8 ------ .../hns3/hns3_common/hclge_comm_rss.c | 17 ++++++++++++ .../hns3/hns3_common/hclge_comm_tqp_stats.c | 5 ++++ .../hisilicon/hns3/hns3pf/hclge_main.c | 2 ++ .../hisilicon/hns3/hns3vf/hclgevf_main.c | 2 ++ 8 files changed, 58 insertions(+), 21 deletions(-) -- 2.38.1 diff --git a/drivers/net/ethernet/hisilicon/Kconfig b/drivers/net/ethernet/hisilicon/Kconfig index 3312e1d93c3b..9d2be93d0378 100644 --- a/drivers/net/ethernet/hisilicon/Kconfig +++ b/drivers/net/ethernet/hisilicon/Kconfig @@ -100,11 +100,15 @@ config HNS3 if HNS3 +config HNS3_HCLGE_COMMON + tristate + config HNS3_HCLGE tristate "Hisilicon HNS3 HCLGE Acceleration Engine & Compatibility Layer Support" default m depends on PCI_MSI depends on PTP_1588_CLOCK_OPTIONAL + select HNS3_HCLGE_COMMON help This selects the HNS3_HCLGE network acceleration engine & its hardware compatibility layer. The engine would be used in Hisilicon hip08 family of @@ -123,6 +127,7 @@ config HNS3_HCLGEVF tristate "Hisilicon HNS3VF Acceleration Engine & Compatibility Layer Support" depends on PCI_MSI depends on HNS3_HCLGE + select HNS3_HCLGE_COMMON help This selects the HNS3 VF drivers network acceleration engine & its hardware compatibility layer. The engine would be used in Hisilicon hip08 family of diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile index 6efea4662858..09d0e442b7fb 100644 --- a/drivers/net/ethernet/hisilicon/hns3/Makefile +++ b/drivers/net/ethernet/hisilicon/hns3/Makefile @@ -13,17 +13,20 @@ obj-$(CONFIG_HNS3) += hnae3.o obj-$(CONFIG_HNS3_ENET) += hns3.o hns3-objs = hns3_enet.o hns3_ethtool.o hns3_debugfs.o +obj-$(CONFIG_HNS3_HCLGE_COMMON) += hclge_common.o +hclge_common-objs := \ + hns3_common/hclge_comm_cmd.o \ + hns3_common/hclge_comm_rss.o \ + hns3_common/hclge_comm_tqp_stats.o + hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o -hclgevf-objs = hns3vf/hclgevf_main.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o \ - hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o +hclgevf-objs = hns3vf/hclgevf_main.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o obj-$(CONFIG_HNS3_HCLGE) += hclge.o hclge-objs = hns3pf/hclge_main.o hns3pf/hclge_mdio.o hns3pf/hclge_tm.o \ - hns3pf/hclge_mbx.o hns3pf/hclge_err.o hns3pf/hclge_debugfs.o hns3pf/hclge_ptp.o hns3pf/hclge_devlink.o \ - hns3_common/hclge_comm_cmd.o hns3_common/hclge_comm_rss.o hns3_common/hclge_comm_tqp_stats.o - + hns3pf/hclge_mbx.o hns3pf/hclge_err.o hns3pf/hclge_debugfs.o hns3pf/hclge_ptp.o hns3pf/hclge_devlink.o hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c index f671a63cecde..ff76ae425829 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c @@ -33,7 +33,7 @@ static void hclge_comm_cmd_config_regs(struct hclge_comm_hw *hw, } } -void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw) +static void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw) { hclge_comm_cmd_config_regs(hw, &hw->cmq.csq); hclge_comm_cmd_config_regs(hw, &hw->cmq.crq); @@ -48,6 +48,7 @@ void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read) else desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR); } +EXPORT_SYMBOL_NS_GPL(hclge_comm_cmd_reuse_desc, HNS3_HCLGE_COMMON); static void hclge_comm_set_default_capability(struct hnae3_ae_dev *ae_dev, bool is_pf) @@ -72,9 +73,10 @@ void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc, if (is_read) desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR); } +EXPORT_SYMBOL_NS_GPL(hclge_comm_cmd_setup_basic_desc, HNS3_HCLGE_COMMON); -int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, - struct hclge_comm_hw *hw, bool en) +static int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, + struct hclge_comm_hw *hw, bool en) { struct hclge_comm_firmware_compat_cmd *req; struct hclge_desc desc; @@ -99,7 +101,7 @@ int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, return hclge_comm_cmd_send(hw, &desc, 1); } -void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring) +static void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring) { int size = ring->desc_num * sizeof(struct hclge_desc); @@ -186,7 +188,7 @@ hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf, set_bit(caps_map[i].local_bit, ae_dev->caps); } -int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type) +static int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type) { struct hclge_comm_cmq_ring *ring = (ring_type == HCLGE_COMM_TYPE_CSQ) ? &hw->cmq.csq : @@ -204,9 +206,10 @@ int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type) return ret; } -int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev, - struct hclge_comm_hw *hw, - u32 *fw_version, bool is_pf) +static int +hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev, + struct hclge_comm_hw *hw, + u32 *fw_version, bool is_pf) { struct hclge_comm_query_version_cmd *resp; struct hclge_desc desc; @@ -474,6 +477,7 @@ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, return ret; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_cmd_send, HNS3_HCLGE_COMMON); static void hclge_comm_cmd_uninit_regs(struct hclge_comm_hw *hw) { @@ -510,6 +514,7 @@ void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev, hclge_comm_free_cmd_desc(&cmdq->csq); hclge_comm_free_cmd_desc(&cmdq->crq); } +EXPORT_SYMBOL_NS_GPL(hclge_comm_cmd_uninit, HNS3_HCLGE_COMMON); int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw) { @@ -548,6 +553,7 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw) hclge_comm_free_cmd_desc(&hw->cmq.csq); return ret; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_cmd_queue_init, HNS3_HCLGE_COMMON); int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, u32 *fw_version, bool is_pf, @@ -618,3 +624,8 @@ int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, return ret; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_cmd_init, HNS3_HCLGE_COMMON); + +MODULE_AUTHOR("Huawei Tech. Co., Ltd."); +MODULE_DESCRIPTION("HCLGE Common module"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h index b1f9383b418f..b16438d3885b 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h @@ -441,17 +441,9 @@ static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg) #define hclge_comm_read_dev(a, reg) \ hclge_comm_read_reg((a)->io_base, reg) -void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw); -int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev, - struct hclge_comm_hw *hw, - u32 *fw_version, bool is_pf); -int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type); int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, int num); void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read); -int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, - struct hclge_comm_hw *hw, bool en); -void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring); void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc, enum hclge_opcode_type opcode, bool is_read); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c index e23729ac3bb8..b266e69b3675 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_rss.c @@ -62,6 +62,7 @@ int hclge_comm_rss_init_cfg(struct hnae3_handle *nic, return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_rss_init_cfg, HNS3_HCLGE_COMMON); void hclge_comm_get_rss_tc_info(u16 rss_size, u8 hw_tc_map, u16 *tc_offset, u16 *tc_valid, u16 *tc_size) @@ -78,6 +79,7 @@ void hclge_comm_get_rss_tc_info(u16 rss_size, u8 hw_tc_map, u16 *tc_offset, tc_offset[i] = (hw_tc_map & BIT(i)) ? rss_size * i : 0; } } +EXPORT_SYMBOL_NS_GPL(hclge_comm_get_rss_tc_info, HNS3_HCLGE_COMMON); int hclge_comm_set_rss_tc_mode(struct hclge_comm_hw *hw, u16 *tc_offset, u16 *tc_valid, u16 *tc_size) @@ -113,6 +115,7 @@ int hclge_comm_set_rss_tc_mode(struct hclge_comm_hw *hw, u16 *tc_offset, return ret; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_set_rss_tc_mode, HNS3_HCLGE_COMMON); int hclge_comm_set_rss_hash_key(struct hclge_comm_rss_cfg *rss_cfg, struct hclge_comm_hw *hw, const u8 *key, @@ -143,6 +146,7 @@ int hclge_comm_set_rss_hash_key(struct hclge_comm_rss_cfg *rss_cfg, return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_set_rss_hash_key, HNS3_HCLGE_COMMON); int hclge_comm_set_rss_tuple(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw, @@ -185,11 +189,13 @@ int hclge_comm_set_rss_tuple(struct hnae3_ae_dev *ae_dev, rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_set_rss_tuple, HNS3_HCLGE_COMMON); u32 hclge_comm_get_rss_key_size(struct hnae3_handle *handle) { return HCLGE_COMM_RSS_KEY_SIZE; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_get_rss_key_size, HNS3_HCLGE_COMMON); void hclge_comm_get_rss_type(struct hnae3_handle *nic, struct hclge_comm_rss_tuple_cfg *rss_tuple_sets) @@ -207,6 +213,7 @@ void hclge_comm_get_rss_type(struct hnae3_handle *nic, else nic->kinfo.rss_type = PKT_HASH_TYPE_NONE; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_get_rss_type, HNS3_HCLGE_COMMON); int hclge_comm_parse_rss_hfunc(struct hclge_comm_rss_cfg *rss_cfg, const u8 hfunc, u8 *hash_algo) @@ -225,6 +232,7 @@ int hclge_comm_parse_rss_hfunc(struct hclge_comm_rss_cfg *rss_cfg, return -EINVAL; } } +EXPORT_SYMBOL_NS_GPL(hclge_comm_parse_rss_hfunc, HNS3_HCLGE_COMMON); void hclge_comm_rss_indir_init_cfg(struct hnae3_ae_dev *ae_dev, struct hclge_comm_rss_cfg *rss_cfg) @@ -234,6 +242,7 @@ void hclge_comm_rss_indir_init_cfg(struct hnae3_ae_dev *ae_dev, for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++) rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_rss_indir_init_cfg, HNS3_HCLGE_COMMON); int hclge_comm_get_rss_tuple(struct hclge_comm_rss_cfg *rss_cfg, int flow_type, u8 *tuple_sets) @@ -267,6 +276,7 @@ int hclge_comm_get_rss_tuple(struct hclge_comm_rss_cfg *rss_cfg, int flow_type, return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_get_rss_tuple, HNS3_HCLGE_COMMON); static void hclge_comm_append_rss_msb_info(struct hclge_comm_rss_ind_tbl_cmd *req, @@ -321,6 +331,7 @@ int hclge_comm_set_rss_indir_table(struct hnae3_ae_dev *ae_dev, } return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_set_rss_indir_table, HNS3_HCLGE_COMMON); int hclge_comm_set_rss_input_tuple(struct hnae3_handle *nic, struct hclge_comm_hw *hw, bool is_pf, @@ -353,6 +364,7 @@ int hclge_comm_set_rss_input_tuple(struct hnae3_handle *nic, "failed to configure rss input, ret = %d.\n", ret); return ret; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_set_rss_input_tuple, HNS3_HCLGE_COMMON); void hclge_comm_get_rss_hash_info(struct hclge_comm_rss_cfg *rss_cfg, u8 *key, u8 *hfunc) @@ -376,6 +388,7 @@ void hclge_comm_get_rss_hash_info(struct hclge_comm_rss_cfg *rss_cfg, u8 *key, if (key) memcpy(key, rss_cfg->rss_hash_key, HCLGE_COMM_RSS_KEY_SIZE); } +EXPORT_SYMBOL_NS_GPL(hclge_comm_get_rss_hash_info, HNS3_HCLGE_COMMON); void hclge_comm_get_rss_indir_tbl(struct hclge_comm_rss_cfg *rss_cfg, u32 *indir, u16 rss_ind_tbl_size) @@ -388,6 +401,7 @@ void hclge_comm_get_rss_indir_tbl(struct hclge_comm_rss_cfg *rss_cfg, for (i = 0; i < rss_ind_tbl_size; i++) indir[i] = rss_cfg->rss_indirection_tbl[i]; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_get_rss_indir_tbl, HNS3_HCLGE_COMMON); int hclge_comm_set_rss_algo_key(struct hclge_comm_hw *hw, const u8 hfunc, const u8 *key) @@ -429,6 +443,7 @@ int hclge_comm_set_rss_algo_key(struct hclge_comm_hw *hw, const u8 hfunc, return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_set_rss_algo_key, HNS3_HCLGE_COMMON); static u8 hclge_comm_get_rss_hash_bits(struct ethtool_rxnfc *nfc) { @@ -507,6 +522,7 @@ int hclge_comm_init_rss_tuple_cmd(struct hclge_comm_rss_cfg *rss_cfg, return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_init_rss_tuple_cmd, HNS3_HCLGE_COMMON); u64 hclge_comm_convert_rss_tuple(u8 tuple_sets) { @@ -523,3 +539,4 @@ u64 hclge_comm_convert_rss_tuple(u8 tuple_sets) return tuple_data; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_convert_rss_tuple, HNS3_HCLGE_COMMON); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c index f3c9395d8351..6f1ba82f83e7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_tqp_stats.c @@ -26,6 +26,7 @@ u64 *hclge_comm_tqps_get_stats(struct hnae3_handle *handle, u64 *data) return buff; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_tqps_get_stats, HNS3_HCLGE_COMMON); int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle) { @@ -33,6 +34,7 @@ int hclge_comm_tqps_get_sset_count(struct hnae3_handle *handle) return kinfo->num_tqps * HCLGE_COMM_QUEUE_PAIR_SIZE; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_tqps_get_sset_count, HNS3_HCLGE_COMMON); u8 *hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 *data) { @@ -56,6 +58,7 @@ u8 *hclge_comm_tqps_get_strings(struct hnae3_handle *handle, u8 *data) return buff; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_tqps_get_strings, HNS3_HCLGE_COMMON); int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, struct hclge_comm_hw *hw) @@ -99,6 +102,7 @@ int hclge_comm_tqps_update_stats(struct hnae3_handle *handle, return 0; } +EXPORT_SYMBOL_NS_GPL(hclge_comm_tqps_update_stats, HNS3_HCLGE_COMMON); void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle) { @@ -113,3 +117,4 @@ void hclge_comm_reset_tqp_stats(struct hnae3_handle *handle) memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); } } +EXPORT_SYMBOL_NS_GPL(hclge_comm_reset_tqp_stats, HNS3_HCLGE_COMMON); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 987271da6e9b..39a7ab51be31 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -13133,6 +13133,8 @@ static void __exit hclge_exit(void) module_init(hclge_init); module_exit(hclge_exit); +MODULE_IMPORT_NS(HNS3_HCLGE_COMMON); + MODULE_LICENSE("GPL"); MODULE_AUTHOR("Huawei Tech. Co., Ltd."); MODULE_DESCRIPTION("HCLGE Driver"); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c index db6f7cdba958..5d0a8801a375 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c @@ -3452,6 +3452,8 @@ static void __exit hclgevf_exit(void) module_init(hclgevf_init); module_exit(hclgevf_exit); +MODULE_IMPORT_NS(HNS3_HCLGE_COMMON); + MODULE_LICENSE("GPL"); MODULE_AUTHOR("Huawei Tech. Co., Ltd."); MODULE_DESCRIPTION("HCLGEVF Driver"); From patchwork Sat Nov 19 23:10:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Lobakin X-Patchwork-Id: 23355 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp904791wrr; Sat, 19 Nov 2022 15:35:48 -0800 (PST) X-Google-Smtp-Source: AA0mqf7J2qYGCpqkPkeB3MCpaO3s4zwmJf7qOsuFOhXPfZlLYouKRdJEyz+TO5SlsvJ4ix2VBTrg X-Received: by 2002:a17:906:6dd7:b0:7a1:1c24:e564 with SMTP id j23-20020a1709066dd700b007a11c24e564mr10525828ejt.629.1668900947933; Sat, 19 Nov 2022 15:35:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668900947; cv=none; d=google.com; s=arc-20160816; b=YOr5B6YJo6C53KiF4ZbJlR8YTiw7ODfSSYidVzUYDQNKt6oAZ+d7VutmVmTE3bhmqM VjIoXZU4GIuNflJB5sKWgpe8oeauZpbtUPSh5D6/AMRjqmThfq8d22kizimT8NPAn07/ TuD99txmmCnI3oaG2dvd4M4ZdFrQQf1qT+3Gwj522M12kQdXwM+doUWn/H/zOtX/DVGM KPDP+WpBwEFfzQ7BMhipHfqO8MPrkTJ4t9+LXfd7qFboLXqnwCJ47VaizdaccDhf9AV9 cBannMqYE2DV1PLUZMOm+077ctBJPWiITLB2SqfUQwhEq0Y/1rdJkoyVIsldxZ+Bl3jf KGyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :feedback-id:references:in-reply-to:message-id:subject:cc:from:to :dkim-signature:date; bh=lZ7Rs/ZnddACw1jvzs/PqLsltYLTGpkimYjbYKt//JU=; b=GXtfzLs+DSJ3/sGQ59S+gtFQapXQGKlfdziuYi0YYEIa77vpeAdklZZmcazj+5Fc3F CHAYjsPF3E44tWQ+RnyyESWUH59gizwgzeSurEwmyd1jM8rLohNE9iRlGbUKsPb54AZ4 y6RXvow12KEAzES/nTdIYaOQhTMzeWkxMn6W4tQIQcge14Lc9Uc1TyBj6WRCtqdQpLtA q6FdFFiSrtNhp1gT+aqrJAaRXOU/O+ZzFHw+RTtYjnlANzJOJ5pgXH/rYTlz/Ywu/bhA rWfz6/q7KBmPxxbpnLJ2aMyxz9dCBP2vBzZheIxdD9A9aBBBexFBcNhZz+8N4GhCEjGx uImA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=MwkzEn1Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ds15-20020a0564021ccf00b00459b51c2b25si6467616edb.438.2022.11.19.15.35.19; Sat, 19 Nov 2022 15:35:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=MwkzEn1Z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235376AbiKSXLO (ORCPT + 99 others); Sat, 19 Nov 2022 18:11:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234216AbiKSXKu (ORCPT ); Sat, 19 Nov 2022 18:10:50 -0500 Received: from mail-40133.protonmail.ch (mail-40133.protonmail.ch [185.70.40.133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 552451A237; Sat, 19 Nov 2022 15:10:47 -0800 (PST) Date: Sat, 19 Nov 2022 23:10:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899445; x=1669158645; bh=lZ7Rs/ZnddACw1jvzs/PqLsltYLTGpkimYjbYKt//JU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=MwkzEn1Z43pI6k3ysRRUAd78NdgilKCbiURPSU97ud6PlYDuD3r4wX6kynsud2BDV FTgz0dIEhO0vqk69Q9ajklQkuUJTQUtv5Kfke1xyFpEpF9rgACfyhr4daSrfsx3B1J NwVytXSux8c4DY7dTJbFnBZ/5qoUCO+b5JS9y9tdhpIdlnUzDdVB481RrUoLPXyFop 7beDz4m4lmYWIDUYmcAC+eEZKejYBokFJWi6hPnMt+kecxCZ+rwCuKqGUI83jvEfX6 Np0bActEFWr2aY6rHGeA31YLT/OZPm6Ym/XQ2GGyRphcbaJSkCAUykj1kUORpfvI1G tMIri4Tqm44TQ== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 17/18] net: octeontx2: fix mixed module-builtin object Message-ID: <20221119225650.1044591-18-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749969480312927976?= X-GMAIL-MSGID: =?utf-8?q?1749969480312927976?= With CONFIG_OCTEONTX2_PF=y and CONFIG_OCTEONTX2_VF=m, several object files are linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). There's also no need to duplicate relatively big piece of object code into two modules. Introduce the new module, rvu_niccommon, to provide the common functions to both rvu_nicpf and rvu_nicvf. Also, otx2_ptp.o was not shared, but built as a standalone module (it was fixed already a year ago the same way this commit does due to link issues). As it's used by both PF and VF modules in the same way, just link it into that new common one. Fixes: 2da489432747 ("octeontx2-pf: devlink params support to set mcam entry count") Fixes: 8e67558177f8 ("octeontx2-pf: PFC config support with DCBx") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin Reviewed-by: Masahiro Yamada --- drivers/net/ethernet/marvell/octeontx2/Kconfig | 5 +++++ .../net/ethernet/marvell/octeontx2/nic/Makefile | 14 +++++++------- .../ethernet/marvell/octeontx2/nic/otx2_common.h | 1 - .../ethernet/marvell/octeontx2/nic/otx2_dcbnl.c | 8 +++++++- .../ethernet/marvell/octeontx2/nic/otx2_devlink.c | 2 ++ .../net/ethernet/marvell/octeontx2/nic/otx2_pf.c | 2 ++ .../net/ethernet/marvell/octeontx2/nic/otx2_ptp.c | 2 +- .../net/ethernet/marvell/octeontx2/nic/otx2_vf.c | 2 ++ 8 files changed, 26 insertions(+), 10 deletions(-) -- 2.38.1 diff --git a/drivers/net/ethernet/marvell/octeontx2/Kconfig b/drivers/net/ethernet/marvell/octeontx2/Kconfig index 6b4f640163f7..eb03bdcaf606 100644 --- a/drivers/net/ethernet/marvell/octeontx2/Kconfig +++ b/drivers/net/ethernet/marvell/octeontx2/Kconfig @@ -28,8 +28,12 @@ config NDC_DIS_DYNAMIC_CACHING , NPA stack pages etc in NDC. Also locks down NIX SQ/CQ/RQ/RSS and NPA Aura/Pool contexts. +config OCTEONTX2_NIC_COMMON + tristate + config OCTEONTX2_PF tristate "Marvell OcteonTX2 NIC Physical Function driver" + select OCTEONTX2_NIC_COMMON select OCTEONTX2_MBOX select NET_DEVLINK depends on MACSEC || !MACSEC @@ -44,5 +48,6 @@ config OCTEONTX2_PF config OCTEONTX2_VF tristate "Marvell OcteonTX2 NIC Virtual Function driver" depends on OCTEONTX2_PF + select OCTEONTX2_NIC_COMMON help This driver supports Marvell's OcteonTX2 NIC virtual function. diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile index 73fdb8798614..040c841645bd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile @@ -3,16 +3,16 @@ # Makefile for Marvell's RVU Ethernet device drivers # -obj-$(CONFIG_OCTEONTX2_PF) += rvu_nicpf.o otx2_ptp.o -obj-$(CONFIG_OCTEONTX2_VF) += rvu_nicvf.o otx2_ptp.o +obj-$(CONFIG_OCTEONTX2_NIC_COMMON) += rvu_niccommon.o +obj-$(CONFIG_OCTEONTX2_PF) += rvu_nicpf.o +obj-$(CONFIG_OCTEONTX2_VF) += rvu_nicvf.o +rvu_niccommon-y := otx2_devlink.o otx2_ptp.o rvu_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \ - otx2_flows.o otx2_tc.o cn10k.o otx2_dmac_flt.o \ - otx2_devlink.o -rvu_nicvf-y := otx2_vf.o otx2_devlink.o + otx2_flows.o otx2_tc.o cn10k.o otx2_dmac_flt.o +rvu_nicvf-y := otx2_vf.o -rvu_nicpf-$(CONFIG_DCB) += otx2_dcbnl.o -rvu_nicvf-$(CONFIG_DCB) += otx2_dcbnl.o +rvu_niccommon-$(CONFIG_DCB) += otx2_dcbnl.o rvu_nicpf-$(CONFIG_MACSEC) += cn10k_macsec.o ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 282db6fe3b08..06307000cfd1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -1018,7 +1018,6 @@ int otx2_dcbnl_set_ops(struct net_device *dev); /* PFC support */ int otx2_pfc_txschq_config(struct otx2_nic *pfvf); int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf); -int otx2_pfc_txschq_update(struct otx2_nic *pfvf); int otx2_pfc_txschq_stop(struct otx2_nic *pfvf); #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c index ccaf97bb1ce0..8e862785325d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_dcbnl.c @@ -54,6 +54,7 @@ int otx2_pfc_txschq_config(struct otx2_nic *pfvf) return 0; } +EXPORT_SYMBOL_NS_GPL(otx2_pfc_txschq_config, OCTEONTX2_NIC_COMMON); static int otx2_pfc_txschq_alloc_one(struct otx2_nic *pfvf, u8 prio) { @@ -122,6 +123,7 @@ int otx2_pfc_txschq_alloc(struct otx2_nic *pfvf) return 0; } +EXPORT_SYMBOL_NS_GPL(otx2_pfc_txschq_alloc, OCTEONTX2_NIC_COMMON); static int otx2_pfc_txschq_stop_one(struct otx2_nic *pfvf, u8 prio) { @@ -201,7 +203,7 @@ static int otx2_pfc_update_sq_smq_mapping(struct otx2_nic *pfvf, int prio) return 0; } -int otx2_pfc_txschq_update(struct otx2_nic *pfvf) +static int otx2_pfc_txschq_update(struct otx2_nic *pfvf) { bool if_up = netif_running(pfvf->netdev); u8 pfc_en = pfvf->pfc_en, pfc_bit_set; @@ -289,6 +291,7 @@ int otx2_pfc_txschq_stop(struct otx2_nic *pfvf) return 0; } +EXPORT_SYMBOL_NS_GPL(otx2_pfc_txschq_stop, OCTEONTX2_NIC_COMMON); int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf) { @@ -328,6 +331,7 @@ int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf) mutex_unlock(&pfvf->mbox.lock); return err; } +EXPORT_SYMBOL_NS_GPL(otx2_config_priority_flow_ctrl, OCTEONTX2_NIC_COMMON); void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable) @@ -392,6 +396,7 @@ void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, "Updating BPIDs in CQ and Aura contexts of RQ%d failed with err %d\n", qidx, err); } +EXPORT_SYMBOL_NS_GPL(otx2_update_bpid_in_rqctx, OCTEONTX2_NIC_COMMON); static int otx2_dcbnl_ieee_getpfc(struct net_device *dev, struct ieee_pfc *pfc) { @@ -468,3 +473,4 @@ int otx2_dcbnl_set_ops(struct net_device *dev) return 0; } +EXPORT_SYMBOL_NS_GPL(otx2_dcbnl_set_ops, OCTEONTX2_NIC_COMMON); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c index 777a27047c8e..73cbedb861f3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_devlink.c @@ -128,6 +128,7 @@ int otx2_register_dl(struct otx2_nic *pfvf) devlink_free(dl); return err; } +EXPORT_SYMBOL_NS_GPL(otx2_register_dl, OCTEONTX2_NIC_COMMON); void otx2_unregister_dl(struct otx2_nic *pfvf) { @@ -139,3 +140,4 @@ void otx2_unregister_dl(struct otx2_nic *pfvf) ARRAY_SIZE(otx2_dl_params)); devlink_free(dl); } +EXPORT_SYMBOL_NS_GPL(otx2_unregister_dl, OCTEONTX2_NIC_COMMON); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c index 303930499a4c..11e3ccee61c1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c @@ -34,6 +34,8 @@ static const struct pci_device_id otx2_pf_id_table[] = { { 0, } /* end of table */ }; +MODULE_IMPORT_NS(OCTEONTX2_NIC_COMMON); + MODULE_AUTHOR("Sunil Goutham "); MODULE_DESCRIPTION(DRV_STRING); MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c index 896b2f9bac34..ef48f50d3771 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ptp.c @@ -394,5 +394,5 @@ int otx2_ptp_tstamp2time(struct otx2_nic *pfvf, u64 tstamp, u64 *tsns) EXPORT_SYMBOL_GPL(otx2_ptp_tstamp2time); MODULE_AUTHOR("Sunil Goutham "); -MODULE_DESCRIPTION("Marvell RVU NIC PTP Driver"); +MODULE_DESCRIPTION("Marvell RVU NIC Common Module"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c index 86653bb8e403..59ec45e16637 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c @@ -24,6 +24,8 @@ static const struct pci_device_id otx2_vf_id_table[] = { { } }; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id h19-20020a05640250d300b0045c9f2adb6bsi5777729edb.606.2022.11.19.15.35.19; Sat, 19 Nov 2022 15:35:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@pm.me header.s=protonmail3 header.b=OCVRh6lF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=pm.me Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234908AbiKSXMV (ORCPT + 99 others); Sat, 19 Nov 2022 18:12:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235015AbiKSXLK (ORCPT ); Sat, 19 Nov 2022 18:11:10 -0500 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 622511AD8D; Sat, 19 Nov 2022 15:11:02 -0800 (PST) Date: Sat, 19 Nov 2022 23:10:52 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1668899460; x=1669158660; bh=qXAp3jTp36nfEd23id/Uz1+YLwDKQcbtNcZf8i0ukoE=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=OCVRh6lFR514A7UNG4ZC1uUXfW4M0cl1VhaJhCzABa22zisKoi3bUW5GatsAFOQU6 kuQMssFZPsYXGEfQjqkIfSKczcPrE5i7um4nDh/SpLYIj0kJ7V/NFuvL01QSpwRsYF UcxP9tdGM2g8FYXpqrBaJmxwDbZdBgJJhOaeYwJIDJnvFedFS0cABGgDMcNLswFpxA ZfC+F6L9sJyEr9vTQ0mJ3e/UDZ8QCLbyFQRwrsEXtcI6cOjUZr9aXz56+30VyFKld5 2Qja8UiVSq5Q4FbrP0Ge6YX7QdN178bhHaXxi6f3rjNBriOZ69FeymO94Z9L4wp/1F lcgH23xIbnYYQ== To: linux-kbuild@vger.kernel.org From: Alexander Lobakin Cc: Alexander Lobakin , Masahiro Yamada , Nicolas Schier , Jens Axboe , Boris Brezillon , Borislav Petkov , Tony Luck , Miquel Raynal , Vladimir Oltean , Alexandre Belloni , Derek Chickles , Ioana Ciornei , Salil Mehta , Sunil Goutham , Grygorii Strashko , Daniel Scally , Hans de Goede , Mark Brown , Andy Shevchenko , NXP Linux Team , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 18/18] net: cpsw: fix mixed module-builtin object Message-ID: <20221119225650.1044591-19-alobakin@pm.me> In-Reply-To: <20221119225650.1044591-1-alobakin@pm.me> References: <20221119225650.1044591-1-alobakin@pm.me> Feedback-ID: 22809121:user:proton MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749969480780670593?= X-GMAIL-MSGID: =?utf-8?q?1749969480780670593?= Apart from cpdma, there are 4 object files shared in one way or another by 5 modules: > scripts/Makefile.build:252: ./drivers/net/ethernet/ti/Makefile: > cpsw_ale.o is added to multiple modules: keystone_netcp > keystone_netcp_ethss ti_cpsw ti_cpsw_new > scripts/Makefile.build:252: ./drivers/net/ethernet/ti/Makefile: > cpsw_ethtool.o is added to multiple modules: ti_cpsw ti_cpsw_new > scripts/Makefile.build:252: ./drivers/net/ethernet/ti/Makefile: > cpsw_priv.o is added to multiple modules: ti_cpsw ti_cpsw_new > scripts/Makefile.build:252: ./drivers/net/ethernet/ti/Makefile: > cpsw_sl.o is added to multiple modules: ti_cpsw ti_cpsw_new All of those five are tristate, that means with some of the corresponding Kconfig options set to `m` and some to `y`, the same objects are linked to a module and also to vmlinux even though the expected CFLAGS are different between builtins and modules. This is the same situation as fixed by commit 637a642f5ca5 ("zstd: Fixing mixed module-builtin objects"). There's also no need to duplicate the same code 4 x 5 = roughly 20 times. Introduce the new module, ti_cpsw_core, to provide the common functions used by all those modules. Fixes: 16f54164828b ("net: ethernet: ti: cpsw: drop CONFIG_TI_CPSW_ALE config option") Fixes: a8577e131266 ("net: ethernet: ti: netcp_ethss: fix build") Fixes: ed3525eda4c4 ("net: ethernet: ti: introduce cpsw switchdev based driver part 1 - dual-emac") Fixes: 93a76530316a ("net: ethernet: ti: introduce am65x/j721e gigabit eth subsystem driver") Suggested-by: Masahiro Yamada Signed-off-by: Alexander Lobakin --- drivers/net/ethernet/ti/Kconfig | 11 ++++++-- drivers/net/ethernet/ti/Makefile | 12 ++++---- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 2 ++ drivers/net/ethernet/ti/cpsw.c | 1 + drivers/net/ethernet/ti/cpsw_ale.c | 20 +++++++++++++ drivers/net/ethernet/ti/cpsw_ethtool.c | 24 ++++++++++++++++ drivers/net/ethernet/ti/cpsw_new.c | 1 + drivers/net/ethernet/ti/cpsw_priv.c | 36 ++++++++++++++++++++++++ drivers/net/ethernet/ti/cpsw_sl.c | 8 ++++++ drivers/net/ethernet/ti/netcp_core.c | 2 ++ drivers/net/ethernet/ti/netcp_ethss.c | 2 ++ 11 files changed, 112 insertions(+), 7 deletions(-) -- 2.38.1 diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig index 2ac0adf0c07d..407943735dd9 100644 --- a/drivers/net/ethernet/ti/Kconfig +++ b/drivers/net/ethernet/ti/Kconfig @@ -51,11 +51,15 @@ config TI_CPSW_PHY_SEL This driver supports configuring of the phy mode connected to the CPSW. DEPRECATED: use PHY_TI_GMII_SEL. +config TI_CPSW_CORE + tristate + select TI_DAVINCI_CPDMA + config TI_CPSW tristate "TI CPSW Switch Support" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST depends on TI_CPTS || !TI_CPTS - select TI_DAVINCI_CPDMA + select TI_CPSW_CORE select TI_DAVINCI_MDIO select MFD_SYSCON select PAGE_POOL @@ -73,7 +77,7 @@ config TI_CPSW_SWITCHDEV depends on NET_SWITCHDEV depends on TI_CPTS || !TI_CPTS select PAGE_POOL - select TI_DAVINCI_CPDMA + select TI_CPSW_CORE select TI_DAVINCI_MDIO select MFD_SYSCON select REGMAP @@ -100,6 +104,7 @@ config TI_K3_AM65_CPSW_NUSS tristate "TI K3 AM654x/J721E CPSW Ethernet driver" depends on ARCH_K3 && OF && TI_K3_UDMA_GLUE_LAYER select NET_DEVLINK + select TI_CPSW_CORE select TI_DAVINCI_MDIO select PHYLINK imply PHY_TI_GMII_SEL @@ -147,6 +152,7 @@ config TI_AM65_CPSW_TAS config TI_KEYSTONE_NETCP tristate "TI Keystone NETCP Core Support" + select TI_CPSW_CORE select TI_DAVINCI_MDIO depends on OF depends on KEYSTONE_NAVIGATOR_DMA && KEYSTONE_NAVIGATOR_QMSS @@ -160,6 +166,7 @@ config TI_KEYSTONE_NETCP config TI_KEYSTONE_NETCP_ETHSS depends on TI_KEYSTONE_NETCP tristate "TI Keystone NETCP Ethernet subsystem Support" + select TI_CPSW_CORE help To compile this driver as a module, choose M here: the module diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile index 28a741ed0ac8..5cda66c4b958 100644 --- a/drivers/net/ethernet/ti/Makefile +++ b/drivers/net/ethernet/ti/Makefile @@ -16,17 +16,19 @@ ti_davinci_emac-y := davinci_emac.o obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o obj-$(CONFIG_TI_CPTS) += cpts.o +obj-$(CONFIG_TI_CPSW_CORE) += ti_cpsw_core.o +ti_cpsw_core-objs := cpsw_ale.o cpsw_ethtool.o cpsw_priv.o cpsw_sl.o obj-$(CONFIG_TI_CPSW) += ti_cpsw.o -ti_cpsw-y := cpsw.o cpsw_ale.o cpsw_priv.o cpsw_sl.o cpsw_ethtool.o +ti_cpsw-y := cpsw.o obj-$(CONFIG_TI_CPSW_SWITCHDEV) += ti_cpsw_new.o -ti_cpsw_new-y := cpsw_switchdev.o cpsw_new.o cpsw_ale.o cpsw_sl.o cpsw_priv.o cpsw_ethtool.o +ti_cpsw_new-y := cpsw_switchdev.o cpsw_new.o obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o -keystone_netcp-y := netcp_core.o cpsw_ale.o +keystone_netcp-y := netcp_core.o obj-$(CONFIG_TI_KEYSTONE_NETCP_ETHSS) += keystone_netcp_ethss.o -keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o cpsw_ale.o +keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o obj-$(CONFIG_TI_K3_AM65_CPSW_NUSS) += ti-am65-cpsw-nuss.o -ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o k3-cppi-desc-pool.o am65-cpsw-qos.o +ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o am65-cpsw-ethtool.o k3-cppi-desc-pool.o am65-cpsw-qos.o ti-am65-cpsw-nuss-$(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV) += am65-cpsw-switchdev.o obj-$(CONFIG_TI_K3_AM65_CPTS) += am65-cpts.o diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index c50b137f92d7..e58a9b1b6690 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -2850,6 +2850,8 @@ static struct platform_driver am65_cpsw_nuss_driver = { module_platform_driver(am65_cpsw_nuss_driver); +MODULE_IMPORT_NS(TI_CPSW_CORE); + MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Grygorii Strashko "); MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index b7ac61329b20..a21648dd26fe 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1796,6 +1796,7 @@ static struct platform_driver cpsw_driver = { module_platform_driver(cpsw_driver); +MODULE_IMPORT_NS(TI_CPSW_CORE); MODULE_IMPORT_NS(TI_DAVINCI_CPDMA); MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index 231370e9a801..75ad7649b12e 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -452,6 +452,7 @@ int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) } return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_flush_multicast, TI_CPSW_CORE); static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, int flags, u16 vid) @@ -489,6 +490,7 @@ int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, cpsw_ale_write(ale, idx, ale_entry); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_add_ucast, TI_CPSW_CORE); int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, int flags, u16 vid) @@ -504,6 +506,7 @@ int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, cpsw_ale_write(ale, idx, ale_entry); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_del_ucast, TI_CPSW_CORE); int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, int flags, u16 vid, int mcast_state) @@ -537,6 +540,7 @@ int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, cpsw_ale_write(ale, idx, ale_entry); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_add_mcast, TI_CPSW_CORE); int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, int flags, u16 vid) @@ -566,6 +570,7 @@ int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, cpsw_ale_write(ale, idx, ale_entry); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_del_mcast, TI_CPSW_CORE); /* ALE NetCP NU switch specific vlan functions */ static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, @@ -635,6 +640,7 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, cpsw_ale_write(ale, idx, ale_entry); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_add_vlan, TI_CPSW_CORE); static void cpsw_ale_vlan_del_modify_int(struct cpsw_ale *ale, u32 *ale_entry, u16 vid, int port_mask) @@ -692,6 +698,7 @@ int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask) return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_vlan_del_modify, TI_CPSW_CORE); int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) { @@ -726,6 +733,7 @@ int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_del_vlan, TI_CPSW_CORE); int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, int untag_mask, int reg_mask, int unreg_mask) @@ -765,6 +773,7 @@ int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_vlan_add_modify, TI_CPSW_CORE); void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, bool add) @@ -792,6 +801,7 @@ void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, cpsw_ale_write(ale, idx, ale_entry); } } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_set_unreg_mcast, TI_CPSW_CORE); static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry, int allmulti) @@ -857,6 +867,7 @@ void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) cpsw_ale_write(ale, idx, ale_entry); } } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_set_allmulti, TI_CPSW_CORE); struct ale_control_info { const char *name; @@ -1114,6 +1125,7 @@ int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_control_set, TI_CPSW_CORE); int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) { @@ -1137,6 +1149,7 @@ int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; return tmp & BITMASK(info->bits); } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_control_get, TI_CPSW_CORE); int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps) @@ -1159,6 +1172,7 @@ int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int rateli port, val * ALE_RATE_LIMIT_MIN_PPS); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_rx_ratelimit_mc, TI_CPSW_CORE); int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps) @@ -1181,6 +1195,7 @@ int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int rateli port, val * ALE_RATE_LIMIT_MIN_PPS); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_rx_ratelimit_bc, TI_CPSW_CORE); static void cpsw_ale_timer(struct timer_list *t) { @@ -1270,6 +1285,7 @@ void cpsw_ale_start(struct cpsw_ale *ale) cpsw_ale_aging_start(ale); } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_start, TI_CPSW_CORE); void cpsw_ale_stop(struct cpsw_ale *ale) { @@ -1277,6 +1293,7 @@ void cpsw_ale_stop(struct cpsw_ale *ale) cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_stop, TI_CPSW_CORE); static const struct cpsw_ale_dev_id cpsw_ale_id_match[] = { { @@ -1441,6 +1458,7 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); return ale; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_create, TI_CPSW_CORE); void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) { @@ -1451,8 +1469,10 @@ void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) data += ALE_ENTRY_WORDS; } } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_dump, TI_CPSW_CORE); u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale) { return ale ? ale->params.ale_entries : 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_ale_get_num_entries, TI_CPSW_CORE); diff --git a/drivers/net/ethernet/ti/cpsw_ethtool.c b/drivers/net/ethernet/ti/cpsw_ethtool.c index a557a477d039..78396f84e42d 100644 --- a/drivers/net/ethernet/ti/cpsw_ethtool.c +++ b/drivers/net/ethernet/ti/cpsw_ethtool.c @@ -144,6 +144,7 @@ u32 cpsw_get_msglevel(struct net_device *ndev) return priv->msg_enable; } +EXPORT_SYMBOL_NS_GPL(cpsw_get_msglevel, TI_CPSW_CORE); void cpsw_set_msglevel(struct net_device *ndev, u32 value) { @@ -151,6 +152,7 @@ void cpsw_set_msglevel(struct net_device *ndev, u32 value) priv->msg_enable = value; } +EXPORT_SYMBOL_NS_GPL(cpsw_set_msglevel, TI_CPSW_CORE); int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, struct kernel_ethtool_coalesce *kernel_coal, @@ -161,6 +163,7 @@ int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, coal->rx_coalesce_usecs = cpsw->coal_intvl; return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_get_coalesce, TI_CPSW_CORE); int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, struct kernel_ethtool_coalesce *kernel_coal, @@ -220,6 +223,7 @@ int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_set_coalesce, TI_CPSW_CORE); int cpsw_get_sset_count(struct net_device *ndev, int sset) { @@ -234,6 +238,7 @@ int cpsw_get_sset_count(struct net_device *ndev, int sset) return -EOPNOTSUPP; } } +EXPORT_SYMBOL_NS_GPL(cpsw_get_sset_count, TI_CPSW_CORE); static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) { @@ -271,6 +276,7 @@ void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) break; } } +EXPORT_SYMBOL_NS_GPL(cpsw_get_strings, TI_CPSW_CORE); void cpsw_get_ethtool_stats(struct net_device *ndev, struct ethtool_stats *stats, u64 *data) @@ -303,6 +309,7 @@ void cpsw_get_ethtool_stats(struct net_device *ndev, } } } +EXPORT_SYMBOL_NS_GPL(cpsw_get_ethtool_stats, TI_CPSW_CORE); void cpsw_get_pauseparam(struct net_device *ndev, struct ethtool_pauseparam *pause) @@ -313,6 +320,7 @@ void cpsw_get_pauseparam(struct net_device *ndev, pause->rx_pause = priv->rx_pause ? true : false; pause->tx_pause = priv->tx_pause ? true : false; } +EXPORT_SYMBOL_NS_GPL(cpsw_get_pauseparam, TI_CPSW_CORE); void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) { @@ -326,6 +334,7 @@ void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) if (cpsw->slaves[slave_no].phy) phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); } +EXPORT_SYMBOL_NS_GPL(cpsw_get_wol, TI_CPSW_CORE); int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) { @@ -338,6 +347,7 @@ int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) else return -EOPNOTSUPP; } +EXPORT_SYMBOL_NS_GPL(cpsw_set_wol, TI_CPSW_CORE); int cpsw_get_regs_len(struct net_device *ndev) { @@ -346,6 +356,7 @@ int cpsw_get_regs_len(struct net_device *ndev) return cpsw_ale_get_num_entries(cpsw->ale) * ALE_ENTRY_WORDS * sizeof(u32); } +EXPORT_SYMBOL_NS_GPL(cpsw_get_regs_len, TI_CPSW_CORE); void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p) { @@ -357,6 +368,7 @@ void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p) cpsw_ale_dump(cpsw->ale, reg); } +EXPORT_SYMBOL_NS_GPL(cpsw_get_regs, TI_CPSW_CORE); int cpsw_ethtool_op_begin(struct net_device *ndev) { @@ -370,6 +382,7 @@ int cpsw_ethtool_op_begin(struct net_device *ndev) return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_ethtool_op_begin, TI_CPSW_CORE); void cpsw_ethtool_op_complete(struct net_device *ndev) { @@ -380,6 +393,7 @@ void cpsw_ethtool_op_complete(struct net_device *ndev) if (ret < 0) cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); } +EXPORT_SYMBOL_NS_GPL(cpsw_ethtool_op_complete, TI_CPSW_CORE); void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch) { @@ -394,6 +408,7 @@ void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch) ch->tx_count = cpsw->tx_ch_num; ch->combined_count = 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_get_channels, TI_CPSW_CORE); int cpsw_get_link_ksettings(struct net_device *ndev, struct ethtool_link_ksettings *ecmd) @@ -408,6 +423,7 @@ int cpsw_get_link_ksettings(struct net_device *ndev, phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd); return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_get_link_ksettings, TI_CPSW_CORE); int cpsw_set_link_ksettings(struct net_device *ndev, const struct ethtool_link_ksettings *ecmd) @@ -421,6 +437,7 @@ int cpsw_set_link_ksettings(struct net_device *ndev, return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, ecmd); } +EXPORT_SYMBOL_NS_GPL(cpsw_set_link_ksettings, TI_CPSW_CORE); int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) { @@ -433,6 +450,7 @@ int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) else return -EOPNOTSUPP; } +EXPORT_SYMBOL_NS_GPL(cpsw_get_eee, TI_CPSW_CORE); int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) { @@ -445,6 +463,7 @@ int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) else return -EOPNOTSUPP; } +EXPORT_SYMBOL_NS_GPL(cpsw_set_eee, TI_CPSW_CORE); int cpsw_nway_reset(struct net_device *ndev) { @@ -457,6 +476,7 @@ int cpsw_nway_reset(struct net_device *ndev) else return -EOPNOTSUPP; } +EXPORT_SYMBOL_NS_GPL(cpsw_nway_reset, TI_CPSW_CORE); static void cpsw_suspend_data_pass(struct net_device *ndev) { @@ -654,6 +674,7 @@ int cpsw_set_channels_common(struct net_device *ndev, cpsw_fail(cpsw); return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_set_channels_common, TI_CPSW_CORE); void cpsw_get_ringparam(struct net_device *ndev, struct ethtool_ringparam *ering, @@ -669,6 +690,7 @@ void cpsw_get_ringparam(struct net_device *ndev, ering->rx_max_pending = cpsw->descs_pool_size - CPSW_MAX_QUEUES; ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma); } +EXPORT_SYMBOL_NS_GPL(cpsw_get_ringparam, TI_CPSW_CORE); int cpsw_set_ringparam(struct net_device *ndev, struct ethtool_ringparam *ering, @@ -715,6 +737,7 @@ int cpsw_set_ringparam(struct net_device *ndev, cpsw_fail(cpsw); return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_set_ringparam, TI_CPSW_CORE); #if IS_ENABLED(CONFIG_TI_CPTS) int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) @@ -750,3 +773,4 @@ int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) return 0; } #endif +EXPORT_SYMBOL_NS_GPL(cpsw_get_ts_info, TI_CPSW_CORE); diff --git a/drivers/net/ethernet/ti/cpsw_new.c b/drivers/net/ethernet/ti/cpsw_new.c index 9ed398c04c04..d56b6c995252 100644 --- a/drivers/net/ethernet/ti/cpsw_new.c +++ b/drivers/net/ethernet/ti/cpsw_new.c @@ -2116,6 +2116,7 @@ static struct platform_driver cpsw_driver = { module_platform_driver(cpsw_driver); +MODULE_IMPORT_NS(TI_CPSW_CORE); MODULE_IMPORT_NS(TI_DAVINCI_CPDMA); MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/ti/cpsw_priv.c b/drivers/net/ethernet/ti/cpsw_priv.c index 758295c898ac..fb2c7785a71e 100644 --- a/drivers/net/ethernet/ti/cpsw_priv.c +++ b/drivers/net/ethernet/ti/cpsw_priv.c @@ -31,6 +31,7 @@ #define CPTS_N_ETX_TS 4 int (*cpsw_slave_index)(struct cpsw_common *cpsw, struct cpsw_priv *priv); +EXPORT_SYMBOL_NS_GPL(cpsw_slave_index, TI_CPSW_CORE); void cpsw_intr_enable(struct cpsw_common *cpsw) { @@ -39,6 +40,7 @@ void cpsw_intr_enable(struct cpsw_common *cpsw) cpdma_ctlr_int_ctrl(cpsw->dma, true); } +EXPORT_SYMBOL_NS_GPL(cpsw_intr_enable, TI_CPSW_CORE); void cpsw_intr_disable(struct cpsw_common *cpsw) { @@ -47,6 +49,7 @@ void cpsw_intr_disable(struct cpsw_common *cpsw) cpdma_ctlr_int_ctrl(cpsw->dma, false); } +EXPORT_SYMBOL_NS_GPL(cpsw_intr_disable, TI_CPSW_CORE); void cpsw_tx_handler(void *token, int len, int status) { @@ -81,6 +84,7 @@ void cpsw_tx_handler(void *token, int len, int status) ndev->stats.tx_packets++; ndev->stats.tx_bytes += len; } +EXPORT_SYMBOL_NS_GPL(cpsw_tx_handler, TI_CPSW_CORE); irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) { @@ -97,6 +101,7 @@ irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id) napi_schedule(&cpsw->napi_tx); return IRQ_HANDLED; } +EXPORT_SYMBOL_NS_GPL(cpsw_tx_interrupt, TI_CPSW_CORE); irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) { @@ -113,6 +118,7 @@ irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id) napi_schedule(&cpsw->napi_rx); return IRQ_HANDLED; } +EXPORT_SYMBOL_NS_GPL(cpsw_rx_interrupt, TI_CPSW_CORE); irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id) { @@ -125,6 +131,7 @@ irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } +EXPORT_SYMBOL_NS_GPL(cpsw_misc_interrupt, TI_CPSW_CORE); int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget) { @@ -157,6 +164,7 @@ int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget) return num_tx; } +EXPORT_SYMBOL_NS_GPL(cpsw_tx_mq_poll, TI_CPSW_CORE); int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) { @@ -175,6 +183,7 @@ int cpsw_tx_poll(struct napi_struct *napi_tx, int budget) return num_tx; } +EXPORT_SYMBOL_NS_GPL(cpsw_tx_poll, TI_CPSW_CORE); int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget) { @@ -207,6 +216,7 @@ int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget) return num_rx; } +EXPORT_SYMBOL_NS_GPL(cpsw_rx_mq_poll, TI_CPSW_CORE); int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) { @@ -225,6 +235,7 @@ int cpsw_rx_poll(struct napi_struct *napi_rx, int budget) return num_rx; } +EXPORT_SYMBOL_NS_GPL(cpsw_rx_poll, TI_CPSW_CORE); void cpsw_rx_vlan_encap(struct sk_buff *skb) { @@ -267,12 +278,14 @@ void cpsw_rx_vlan_encap(struct sk_buff *skb) skb_pull(skb, VLAN_HLEN); } } +EXPORT_SYMBOL_NS_GPL(cpsw_rx_vlan_encap, TI_CPSW_CORE); void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv) { slave_write(slave, mac_hi(priv->mac_addr), SA_HI); slave_write(slave, mac_lo(priv->mac_addr), SA_LO); } +EXPORT_SYMBOL_NS_GPL(cpsw_set_slave_mac, TI_CPSW_CORE); void soft_reset(const char *module, void __iomem *reg) { @@ -285,6 +298,7 @@ void soft_reset(const char *module, void __iomem *reg) WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module); } +EXPORT_SYMBOL_NS_GPL(soft_reset, TI_CPSW_CORE); void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) { @@ -304,6 +318,7 @@ void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) netif_trans_update(ndev); netif_tx_wake_all_queues(ndev); } +EXPORT_SYMBOL_NS_GPL(cpsw_ndo_tx_timeout, TI_CPSW_CORE); static int cpsw_get_common_speed(struct cpsw_common *cpsw) { @@ -342,6 +357,7 @@ int cpsw_need_resplit(struct cpsw_common *cpsw) return 1; } +EXPORT_SYMBOL_NS_GPL(cpsw_need_resplit, TI_CPSW_CORE); void cpsw_split_res(struct cpsw_common *cpsw) { @@ -427,6 +443,7 @@ void cpsw_split_res(struct cpsw_common *cpsw) if (budget) cpsw->rxv[0].budget += budget; } +EXPORT_SYMBOL_NS_GPL(cpsw_split_res, TI_CPSW_CORE); int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, int ale_ageout, phys_addr_t desc_mem_phys, @@ -547,6 +564,7 @@ int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs, return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_init_common, TI_CPSW_CORE); #if IS_ENABLED(CONFIG_TI_CPTS) @@ -728,6 +746,7 @@ int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) return -EOPNOTSUPP; } +EXPORT_SYMBOL_NS_GPL(cpsw_ndo_ioctl, TI_CPSW_CORE); int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) { @@ -777,6 +796,7 @@ int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate) cpsw_split_res(cpsw); return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_ndo_set_tx_maxrate, TI_CPSW_CORE); static int cpsw_tc_to_fifo(int tc, int num_tc) { @@ -801,6 +821,7 @@ bool cpsw_shp_is_off(struct cpsw_priv *priv) return !val; } +EXPORT_SYMBOL_NS_GPL(cpsw_shp_is_off, TI_CPSW_CORE); static void cpsw_fifo_shp_on(struct cpsw_priv *priv, int fifo, int on) { @@ -1062,6 +1083,7 @@ int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type, return -EOPNOTSUPP; } } +EXPORT_SYMBOL_NS_GPL(cpsw_ndo_setup_tc, TI_CPSW_CORE); void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) { @@ -1075,6 +1097,7 @@ void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) cpsw_set_fifo_rlimit(priv, fifo, bw); } } +EXPORT_SYMBOL_NS_GPL(cpsw_cbs_resume, TI_CPSW_CORE); void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) { @@ -1097,6 +1120,7 @@ void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv) slave_write(slave, tx_prio_map, tx_prio_rg); } +EXPORT_SYMBOL_NS_GPL(cpsw_mqprio_resume, TI_CPSW_CORE); int cpsw_fill_rx_channels(struct cpsw_priv *priv) { @@ -1142,6 +1166,7 @@ int cpsw_fill_rx_channels(struct cpsw_priv *priv) return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_fill_rx_channels, TI_CPSW_CORE); static struct page_pool *cpsw_create_page_pool(struct cpsw_common *cpsw, int size) @@ -1227,6 +1252,7 @@ void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw) cpsw->page_pool[ch] = NULL; } } +EXPORT_SYMBOL_NS_GPL(cpsw_destroy_xdp_rxqs, TI_CPSW_CORE); int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw) { @@ -1259,6 +1285,7 @@ int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw) return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_create_xdp_rxqs, TI_CPSW_CORE); static int cpsw_xdp_prog_setup(struct cpsw_priv *priv, struct netdev_bpf *bpf) { @@ -1286,6 +1313,7 @@ int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) return -EINVAL; } } +EXPORT_SYMBOL_NS_GPL(cpsw_ndo_bpf, TI_CPSW_CORE); int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf, struct page *page, int port) @@ -1319,6 +1347,7 @@ int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf, return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_xdp_tx_frame, TI_CPSW_CORE); int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp, struct page *page, int port, int *len) @@ -1381,6 +1410,7 @@ int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp, page_pool_recycle_direct(cpsw->page_pool[ch], page); return ret; } +EXPORT_SYMBOL_NS_GPL(cpsw_run_xdp, TI_CPSW_CORE); static int cpsw_qos_clsflower_add_policer(struct cpsw_priv *priv, struct netlink_ext_ack *extack, @@ -1580,3 +1610,9 @@ void cpsw_qos_clsflower_resume(struct cpsw_priv *priv) cpsw_ale_rx_ratelimit_mc(priv->cpsw->ale, port_id, priv->ale_mc_ratelimit.rate_packet_ps); } +EXPORT_SYMBOL_NS_GPL(cpsw_qos_clsflower_resume, TI_CPSW_CORE); + +MODULE_IMPORT_NS(TI_DAVINCI_CPDMA); + +MODULE_DESCRIPTION("TI CPSW Core Module"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/ti/cpsw_sl.c b/drivers/net/ethernet/ti/cpsw_sl.c index 0c7531cb0f39..893e29d72213 100644 --- a/drivers/net/ethernet/ti/cpsw_sl.c +++ b/drivers/net/ethernet/ti/cpsw_sl.c @@ -200,6 +200,7 @@ u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg) dev_dbg(sl->dev, "cpsw_sl: reg: %04X r 0x%08X\n", sl->regs[reg], val); return val; } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_reg_read, TI_CPSW_CORE); void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val) { @@ -212,6 +213,7 @@ void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val) dev_dbg(sl->dev, "cpsw_sl: reg: %04X w 0x%08X\n", sl->regs[reg], val); writel(val, sl->sl_base + sl->regs[reg]); } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_reg_write, TI_CPSW_CORE); static const struct cpsw_sl_dev_id *cpsw_sl_match_id( const struct cpsw_sl_dev_id *id, @@ -252,6 +254,7 @@ struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev, return sl; } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_get, TI_CPSW_CORE); void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo) { @@ -270,6 +273,7 @@ void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo) if (cpsw_sl_reg_read(sl, CPSW_SL_SOFT_RESET) & CPSW_SL_SOFT_RESET_BIT) dev_err(sl->dev, "cpsw_sl failed to soft-reset.\n"); } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_reset, TI_CPSW_CORE); u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs) { @@ -287,6 +291,7 @@ u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs) return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_ctl_set, TI_CPSW_CORE); u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs) { @@ -304,11 +309,13 @@ u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs) return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_ctl_clr, TI_CPSW_CORE); void cpsw_sl_ctl_reset(struct cpsw_sl *sl) { cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, 0); } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_ctl_reset, TI_CPSW_CORE); int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo) { @@ -326,3 +333,4 @@ int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo) return 0; } +EXPORT_SYMBOL_NS_GPL(cpsw_sl_wait_for_idle, TI_CPSW_CORE); diff --git a/drivers/net/ethernet/ti/netcp_core.c b/drivers/net/ethernet/ti/netcp_core.c index aba70bef4894..7fe79626aa19 100644 --- a/drivers/net/ethernet/ti/netcp_core.c +++ b/drivers/net/ethernet/ti/netcp_core.c @@ -2275,6 +2275,8 @@ static struct platform_driver netcp_driver = { }; module_platform_driver(netcp_driver); +MODULE_IMPORT_NS(TI_CPSW_CORE); + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("TI NETCP driver for Keystone SOCs"); MODULE_AUTHOR("Sandeep Nair