From patchwork Fri Nov 18 10:06:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 22247 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp104018wrr; Fri, 18 Nov 2022 02:14:46 -0800 (PST) X-Google-Smtp-Source: AA0mqf43ElVPHJ762uDN3MXuHAhk/gsIPxAmcFFqDc768IAGt4nTC8Ts2n9dy2XeGSKpKcbdHyiW X-Received: by 2002:a17:906:cd09:b0:7ad:d11e:a2c2 with SMTP id oz9-20020a170906cd0900b007add11ea2c2mr5452581ejb.473.1668766486473; Fri, 18 Nov 2022 02:14:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668766486; cv=none; d=google.com; s=arc-20160816; b=JvD2OL6ReHOeD05RupkpS6GNJCJy0897bte1C+TAfGDGSw33vxFoqGdIJqLjP34Jh1 w9M8uZCOoiBvDeB3OQnYCOuQxNyhGI08eD49u+3QlyQg3xAQDlFVOKqJuGv9haC33epD 1ZzYJ/sPQg8Ec4kkA6h6iTkS9ftFqmBg1nxelKk3vhz+olvB7MuYl/CvrFfUjcMjXjm7 bSA/xO0HO0Zm6GoM85Fu+mntnOzwng7kn2n/XAjy/62gV+RKB2vA/e1rZr6MWfSgWG1x bZTrZMUnafg3I7qfJKtbzvDlkturfUsE62Zt1zaa8d/wBtk0HN8Vr9Z59NQWxGOtGccu evog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=htrBdDCEQaxufGYr+N24jOf/fMdNFnyilMLIKZ1f6r8=; b=ZaJUo87xCiG2+4q6ZRC/2tr+ixh+6NNfJydHpcZjKyKnxaw+ylt6+f10ZeJnnlO2Ba I4k6FUQcZdzKnpMVb02l8Rx1s6w1IrVnFr4lGeIC2ehMzwpIXzCN+Qqw8YXuKPsx/H/b wpzdWAjSGAm2YRwQ9arCB+r1tN29WCvJfVBbxqIPk6EXg8b90nTXuzm6vcD5pDa9EeAh woORcVwDAJ3pDhI7zwNzfP4YPDs13z4DlxD4jZSE4SVbvBemQ4eWM0vlfL46MDDpy6vN +53MKV9uRdcR71JRnb6Y9UbO4WaGT2YhA2wtPeBZGMvHvuIoXvTwQtF+6GGYQ0cm8Yxv zl1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=OYfuN31W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ss28-20020a170907c01c00b0078d4c9d77adsi2560288ejc.94.2022.11.18.02.14.21; Fri, 18 Nov 2022 02:14:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=OYfuN31W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241756AbiKRKHG (ORCPT + 99 others); Fri, 18 Nov 2022 05:07:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241442AbiKRKGx (ORCPT ); Fri, 18 Nov 2022 05:06:53 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9177F8FB19; Fri, 18 Nov 2022 02:06:50 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 91E446602AA5; Fri, 18 Nov 2022 10:06:48 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668766009; bh=wPHPCMj7i9crbfMFAZjYN9WOVm5VI57WehML5RuHHc0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OYfuN31W0XwJvdc1KoLUb+YljXaVIfui1PA7A/tGgliaJRcB+ZuRjkkGytNmeMBRw ptXG85699/bAYmu7oOC+LqxIGNBQ4kpGaFKGaZwIqqCRcbaPSYN2u6earinQy1XkXw EExQd1VA69ZDpMxRixic+qUkKUIyN0Pyr2FQYDBlqCh7g7fpVkgUubooJtTno4v/vw lCY2nUbFFaIFzJv4JDuwJfT8FGcSzvhTTIdbLj7yohXBtfHd3MyLKm8naQnN2rgogN KDiCeb4UlV71s5CeZbR8vUW7Q6NpUN3BXuxpcV+sS0tISAK3ohuNNQUssWVvJBDkNE dkJgrO7jrc3Fg== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v1 1/4] dt-bindings: interrupt-controller: mediatek,cirq: Migrate to dt schema Date: Fri, 18 Nov 2022 11:06:36 +0100 Message-Id: <20221118100639.33704-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221118100639.33704-1-angelogioacchino.delregno@collabora.com> References: <20221118100639.33704-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749828487229129767?= X-GMAIL-MSGID: =?utf-8?q?1749828487229129767?= Migrate mediatek,cirq.txt to dt schema as mediatek,mtk-cirq.yaml. While at it, I've also fixed some typos that were present in the original txt binding, as it was suggesting that the compatible string would have "mediatek,cirq" as compatible but, in reality, that's supposed to be "mediatek,mtk-cirq" instead. Little rewording on property descriptions also happened for them to be more concise. Signed-off-by: AngeloGioacchino Del Regno --- .../interrupt-controller/mediatek,cirq.txt | 33 --------- .../mediatek,mtk-cirq.yaml | 70 +++++++++++++++++++ 2 files changed, 70 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt deleted file mode 100644 index 5865f4f2c69d..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Mediatek 27xx cirq - -In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to -work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC. -The external interrupts (outside MCUSYS) will feed through CIRQ and connect -to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive -interrupts and generate a pulse signal to parent interrupt controller when -flush command is executed. With CIRQ, MCUSYS can be completely turned off -to improve the system power consumption without losing interrupts. - -Required properties: -- compatible: should be one of - - "mediatek,mt2701-cirq" for mt2701 CIRQ - - "mediatek,mt8135-cirq" for mt8135 CIRQ - - "mediatek,mt8173-cirq" for mt8173 CIRQ - and "mediatek,cirq" as a fallback. -- interrupt-controller : Identifies the node as an interrupt controller. -- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- reg: Physical base address of the cirq registers and length of memory - mapped region. -- mediatek,ext-irq-range: Identifies external irq number range in different - SOCs. - -Example: - cirq: interrupt-controller@10204000 { - compatible = "mediatek,mt2701-cirq", - "mediatek,mtk-cirq"; - interrupt-controller; - #interrupt-cells = <3>; - interrupt-parent = <&sysirq>; - reg = <0 0x10204000 0 0x400>; - mediatek,ext-irq-start = <32 200>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml new file mode 100644 index 000000000000..21e709169907 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mediatek,mtk-cirq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Interrupt Controller + +maintainers: + - Youlin Pei + +description: + In MediaTek SoCs, the CIRQ is a low power interrupt controller designed to + work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC. + The external interrupts (outside MCUSYS) will feed through CIRQ and connect + to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive + interrupts and generate a pulse signal to parent interrupt controller when + flush command is executed. With CIRQ, MCUSYS can be completely turned off + to improve the system power consumption without losing interrupts. + + +properties: + compatible: + items: + - enum: + - mediatek,mt2701-cirq + - mediatek,mt8135-cirq + - mediatek,mt8173-cirq + - const: mediatek,mtk-cirq + + reg: + maxItems: 1 + description: Address and size of the CIRQ registers + + '#interrupt-cells': + const: 3 + + interrupt-controller: true + + mediatek,ext-irq-range: + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 1 + items: + items: + - description: First CIRQ interrupt + - description: Last CIRQ interrupt + description: + Identifies the range of external interrupts in different SoCs + +required: + - compatible + - reg + - '#interrupt-cells' + - interrupt-controller + - mediatek,ext-irq-range + +additionalProperties: false + +examples: + - | + #include + + cirq: interrupt-controller@10204000 { + compatible = "mediatek,mt2701-cirq", "mediatek,mtk-cirq"; + reg = <0x10204000 0x400>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&sysirq>; + mediatek,ext-irq-range = <32 200>; + }; From patchwork Fri Nov 18 10:06:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 22246 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp103980wrr; Fri, 18 Nov 2022 02:14:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf7iGFPvRyLJetMN/g4tBuS2xqxNz23N1x7Y4/shUtrE6dm6Kk1rcnpnlnA99efPb9kVetBT X-Received: by 2002:a17:90b:2705:b0:218:78ae:bdaa with SMTP id px5-20020a17090b270500b0021878aebdaamr6089793pjb.162.1668766478214; Fri, 18 Nov 2022 02:14:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668766478; cv=none; d=google.com; s=arc-20160816; b=ijpf2r3i3s22h52yQeSxYTJF96w/w7zzX0aroC4hU8R/q112cibMasXMeoF/ouKw2u esZZ/sy8TtE7hAEhRipgF4KaWHEzCEBgeDA29giZR8PJYRCUdUMHhR/w2AzwTDfxQwXf ia26SiBZ1jriLUHZyKFtHlar9M2Dtq5JcgDtH+89D9uAEOCT9c3iIKenjMu75gUl6FMS FSDDNJEFIQCZGFEUnScL1x7UOh8YJsFOpZJRD5UdzEmKHsBvGN1+8I6MAnyK/iHftE3/ 6IcC0OMUL5MiKETCd6ronvdJrLCe+Uqbb6IFoWokouh2XOXYG5/M/zz2WJQaECaRaV1k DlcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3Is1I9QvdchYKZWyGHMi0IpOc1aZGN19Qo5L5H3hW9g=; b=OCBmYhMPzeb+n/FMucYqUCHwLwMwkPtqScFyVaMHgeY0XBsxgq0FSVUkfvCUZLbsvP xt+gDTsI838sBHbe113eQMOUqCoEWK4SDZFkKH0vu68EXE6eyzSiTBqk2mvKm1NS8HDQ +n88eXdRIxBT5LVzNV+i3L4gdYY2IlyAR+U1WmEdXSW/qRtQVtzQaV3IPPPkhIdLKBVI MBBiv2SqsKI/5gNdqJzZRbV/KShmtbYuSD/3HP8BP8I6IOFwntEJKW9AXas1wiWZlkRT zTucvD331KsJuF039lk38VfvZU8QRK8Byjh7yOs9mUWEKMn+0LFAlSIza75xsDz/vrpj QFww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=CCLOXKSm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id eb19-20020a056a004c9300b0056be594a8b2si3125770pfb.202.2022.11.18.02.14.24; Fri, 18 Nov 2022 02:14:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=CCLOXKSm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241833AbiKRKHI (ORCPT + 99 others); Fri, 18 Nov 2022 05:07:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240950AbiKRKGw (ORCPT ); Fri, 18 Nov 2022 05:06:52 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 214DBCE2D; Fri, 18 Nov 2022 02:06:51 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4D8C66602AA7; Fri, 18 Nov 2022 10:06:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668766009; bh=HIRKl9LLbNCciqN5hCbiOvtTOlM19cvE0E9kI4/8XXQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CCLOXKSmWgktENVJ9T9gHm9n//U1kSSjxnX81IK0Sx/sinEjJVZK0HHHD/PLpeBSY w/2pwcvjtcuIhzm+IhjJEXjYj5mBNN3cOaSHUirxj4nuINv6JT6FgA55nNrekIVUg7 3JnGNMBAOsGs/8gkz/TjWGwC9/AMQV9hOomsWpDX/BMYYLONptCk1DJWtH4T7ZSOop myCKrDkLRIlx/LkIFWDJMu4mzfy1510i55BH5J2tU5DLOOGCG4Xn8qMkOGmySiw4n1 OCfdMLxWzP6eLtuH2sQ7aput/WPPwXmi85iBo/dhqqG0DMe9PX54cF01u24do0i4mu qRU4y/dtX4ufQ== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v1 2/4] dt-bindings: interrupt-controller: mediatek,cirq: Document MT8192 Date: Fri, 18 Nov 2022 11:06:37 +0100 Message-Id: <20221118100639.33704-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221118100639.33704-1-angelogioacchino.delregno@collabora.com> References: <20221118100639.33704-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749828478776382343?= X-GMAIL-MSGID: =?utf-8?q?1749828478776382343?= Add compatible to support the SYS_CIRQ controller found on MT8192. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../bindings/interrupt-controller/mediatek,mtk-cirq.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml index 21e709169907..e0d483d3b1fb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mtk-cirq.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2701-cirq - mediatek,mt8135-cirq - mediatek,mt8173-cirq + - mediatek,mt8192-cirq - const: mediatek,mtk-cirq reg: From patchwork Fri Nov 18 10:06:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 22249 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp104123wrr; Fri, 18 Nov 2022 02:15:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf5Sg4m3g5kXX4EhC9bIQSoqOUM1Cp/EJhEn/Y+rMIuqpLn70Dmy/cYQHAyr4qyDWzbL3OpO X-Received: by 2002:a17:906:26c6:b0:7ae:d8f:893c with SMTP id u6-20020a17090626c600b007ae0d8f893cmr5279979ejc.359.1668766507606; Fri, 18 Nov 2022 02:15:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668766507; cv=none; d=google.com; s=arc-20160816; b=RjvggUlTWn9ly7f/j4lQm4TUGVD02UgX8yeClnQt5h+CPaAEsRQupxU9acARaFwHRA UAKHDX5uAY/IlwgLqivMr8ZXg5JPWcIukajsUfRl8TowxK/OKhYlp9+Gg8VfnxaAvs1M ZJfx+O+RJzT8xGNvST5F4jcxuSDwlISg7c4jjpWNy7LP/oChJEQD7MTJ+MeYJ0GjzusF 0IsW3vIPaKXZrGuJJ3bG7kO6zqjck5Ht3C6/V0ZeQzl8Zwv4q8mxBCuXwVAq3JxyibTg KhfHxW0SncHZUGLMTsw9Kj//LJdXppfQM1FCIzxFN8hHCAhNDp1zgHpkHje3P55B5Aop UHCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PlJMwkpzlIWIbmk44rUkWhFwV2xH6YGQUeMz2w7/hK4=; b=dryZLqenhDScnmOlnumFugg2+YcK5oftT6CloxHd9i2l4NV9waVZvXc0r2crQcv/e8 hlSDFF9P9YU+iYrmr9j1rRzlFe1C8BAX6ECxDiH2307GRbgyJoZANWYoGNwy22FMLmU2 35uiKON6FR6LAhYLOYD/yL1sAl9Fi/xIXWcIIH8SDQYlHcBRoVwO/F0Loi5kaOB3f0RM 2vbYOUcS/KTyxxIJ9KSMVe3xfzc3T9DCWIXewiZTsLNwyKXgULrbCKrk6oragEtOLJcD Njkld1qeF6p8A4Th4oKlKV4L1LHS2xGHJqX5cB11JWLVarJ+qtJ6UFppCf3803Wndzx5 BpDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Tod0QP70; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g10-20020a170906538a00b0078db1258ae9si434008ejo.555.2022.11.18.02.14.41; Fri, 18 Nov 2022 02:15:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Tod0QP70; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241679AbiKRKHE (ORCPT + 99 others); Fri, 18 Nov 2022 05:07:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241558AbiKRKGx (ORCPT ); Fri, 18 Nov 2022 05:06:53 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C85798FB18; Fri, 18 Nov 2022 02:06:51 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 12ECE6602AAB; Fri, 18 Nov 2022 10:06:50 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668766010; bh=Z7OZ2v5y+VgIWD+PEZh2BYTDoHwy0VQjFBEGe4alcEk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tod0QP70T6g6dsjNDEOdW8OM+cI0IdaObMc0ArqspvhMQAQZxfpcv7eyzg/gzieQ8 i88fMoczQgCR2/DYiTnyYjN397Sagk4D7kvIuZN3uf/6vh+Vlo5/BLLqsGVNVob/Q2 BO3U6T7XzTgE08pa85/8l1x+w/rWPzLId9WL7ULr1GByEKEcWGcxfOsPRWVOC/I3+k jyssSh6CmrN92gDQXedbFjvF8WDIXAaZUhovMbpGOv/ZEgmxY9Ldi2QmdrkPtQUD0x 2LSiJy+ixeUCJ3xfJmS5hzuFKXyUSwu4F6MilWTE3SvJXLYmZMLYBHadRJCZU8Rv5G otxLyoWJUjErg== From: AngeloGioacchino Del Regno To: tglx@linutronix.de Cc: maz@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, youlin.pei@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v1 3/4] irqchip: irq-mtk-cirq: Move register offsets to const array Date: Fri, 18 Nov 2022 11:06:38 +0100 Message-Id: <20221118100639.33704-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221118100639.33704-1-angelogioacchino.delregno@collabora.com> References: <20221118100639.33704-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749828509429524666?= X-GMAIL-MSGID: =?utf-8?q?1749828509429524666?= In preparation to add support for new SoCs having different register offsets, add an enumeration that documents registers and move the register offsets definitions to a u32 array. Of course, every usage of the definitions was changed to use the newly introduced register offsets array. This change brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/irqchip/irq-mtk-cirq.c | 62 ++++++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index 9bca0918078e..affbc0f48550 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -15,14 +15,30 @@ #include #include -#define CIRQ_ACK 0x40 -#define CIRQ_MASK_SET 0xc0 -#define CIRQ_MASK_CLR 0x100 -#define CIRQ_SENS_SET 0x180 -#define CIRQ_SENS_CLR 0x1c0 -#define CIRQ_POL_SET 0x240 -#define CIRQ_POL_CLR 0x280 -#define CIRQ_CONTROL 0x300 +enum mtk_cirq_reg_index { + CIRQ_STA = 0, + CIRQ_ACK, + CIRQ_MASK_SET, + CIRQ_MASK_CLR, + CIRQ_SENS_SET, + CIRQ_SENS_CLR, + CIRQ_POL_SET, + CIRQ_POL_CLR, + CIRQ_CONTROL, + CIRQ_MAX +}; + +static const u32 mtk_cirq_regs_v1[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x40, + [CIRQ_MASK_SET] = 0xc0, + [CIRQ_MASK_CLR] = 0x100, + [CIRQ_SENS_SET] = 0x180, + [CIRQ_SENS_CLR] = 0x1c0, + [CIRQ_POL_SET] = 0x240, + [CIRQ_POL_CLR] = 0x280, + [CIRQ_CONTROL] = 0x300, +}; #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 @@ -32,18 +48,20 @@ struct mtk_cirq_chip_data { void __iomem *base; unsigned int ext_irq_start; unsigned int ext_irq_end; + const u32 *regs; struct irq_domain *domain; }; static struct mtk_cirq_chip_data *cirq_data; -static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset) +static void mtk_cirq_write_mask(struct irq_data *data, enum mtk_cirq_reg_index idx) { struct mtk_cirq_chip_data *chip_data = data->chip_data; unsigned int cirq_num = data->hwirq; u32 mask = 1 << (cirq_num % 32); + u32 reg = chip_data->regs[idx] + (cirq_num / 32) * 4; - writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4); + writel_relaxed(mask, chip_data->base + reg); } static void mtk_cirq_mask(struct irq_data *data) @@ -160,7 +178,7 @@ static const struct irq_domain_ops cirq_domain_ops = { #ifdef CONFIG_PM_SLEEP static int mtk_cirq_suspend(void) { - u32 value, mask; + u32 value, mask, reg; unsigned int irq, hwirq_num; bool pending, masked; int i, pendret, maskret; @@ -200,31 +218,34 @@ static int mtk_cirq_suspend(void) continue; } + reg = cirq_data->regs[CIRQ_ACK] + (i / 32) * 4; mask = 1 << (i % 32); - writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4); + writel_relaxed(mask, cirq_data->base + reg); } /* set edge_only mode, record edge-triggerd interrupts */ /* enable cirq */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); + reg = cirq_data->regs[CIRQ_CONTROL]; + value = readl_relaxed(cirq_data->base + reg); value |= (CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, cirq_data->base + reg); return 0; } static void mtk_cirq_resume(void) { + u32 reg = cirq_data->regs[CIRQ_CONTROL]; u32 value; /* flush recorded interrupts, will send signals to parent controller */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); - writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL); + value = readl_relaxed(cirq_data->base + reg); + writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + reg); /* disable cirq */ - value = readl_relaxed(cirq_data->base + CIRQ_CONTROL); + value = readl_relaxed(cirq_data->base + reg); value &= ~(CIRQ_EDGE | CIRQ_EN); - writel_relaxed(value, cirq_data->base + CIRQ_CONTROL); + writel_relaxed(value, cirq_data->base + reg); } static struct syscore_ops mtk_cirq_syscore_ops = { @@ -240,6 +261,9 @@ static void mtk_cirq_syscore_init(void) static inline void mtk_cirq_syscore_init(void) {} #endif +static const struct of_device_id mtk_cirq_of_match[] = { + { .compatible = "mediatek, + static int __init mtk_cirq_of_init(struct device_node *node, struct device_node *parent) { @@ -274,6 +298,8 @@ static int __init mtk_cirq_of_init(struct device_node *node, if (ret) goto out_unmap; + cirq_data->regs = mtk_cirq_regs_v1; + irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1; domain = irq_domain_add_hierarchy(domain_parent, 0, irq_num, node, From patchwork Fri Nov 18 10:06:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 22248 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp104052wrr; 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Add the new "v2" register layout and use it if the compatible "mediatek,mt8192-cirq" is found; to retain compatibility with older devicetrees and/or with SoCs that don't need any register layout variation, if no "special" compatible is found, we use the "v1" register layout by default. Signed-off-by: AngeloGioacchino Del Regno --- drivers/irqchip/irq-mtk-cirq.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index affbc0f48550..8d6b3d9c40cf 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -40,6 +40,18 @@ static const u32 mtk_cirq_regs_v1[] = { [CIRQ_CONTROL] = 0x300, }; +static const u32 mtk_cirq_regs_v2[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x80, + [CIRQ_MASK_SET] = 0x180, + [CIRQ_MASK_CLR] = 0x200, + [CIRQ_SENS_SET] = 0x300, + [CIRQ_SENS_CLR] = 0x380, + [CIRQ_POL_SET] = 0x480, + [CIRQ_POL_CLR] = 0x500, + [CIRQ_CONTROL] = 0x600, +}; + #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 #define CIRQ_FLUSH 0x4 @@ -262,12 +274,15 @@ static inline void mtk_cirq_syscore_init(void) {} #endif static const struct of_device_id mtk_cirq_of_match[] = { - { .compatible = "mediatek, + { .compatible = "mediatek,mt8192-cirq", .data = &mtk_cirq_regs_v2 }, + { /* sentinel */ } +}; static int __init mtk_cirq_of_init(struct device_node *node, struct device_node *parent) { struct irq_domain *domain, *domain_parent; + const struct of_device_id *match; unsigned int irq_num; int ret; @@ -298,7 +313,11 @@ static int __init mtk_cirq_of_init(struct device_node *node, if (ret) goto out_unmap; - cirq_data->regs = mtk_cirq_regs_v1; + match = of_match_node(mtk_cirq_of_match, node); + if (match) + cirq_data->regs = match->data; + else + cirq_data->regs = mtk_cirq_regs_v1; irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1; domain = irq_domain_add_hierarchy(domain_parent, 0,