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Move it before the dereferencing operator to cure this. Signed-off-by: Thomas Gleixner --- arch/x86/events/amd/uncore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -71,7 +71,7 @@ union amd_uncore_info { }; struct amd_uncore { - union amd_uncore_info * __percpu info; + union amd_uncore_info __percpu *info; struct amd_uncore_pmu *pmus; unsigned int num_pmus; bool init_done; From patchwork Mon Mar 4 10:12:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 209478 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp1326380dyc; Mon, 4 Mar 2024 02:14:45 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWigMEPpwgECIqs0eff0pmdy8Ibl/McNqKS9TY27ZtVVJrqLeDGsSKS7V2g6wDsW6o5O5aPrGTkA7pUeiqw/YNiAo3AEQ== X-Google-Smtp-Source: AGHT+IH30RH5Hugh68xpvlHE/OAU8ag9HOa94Dz/FjP9M2pBExc1Q8lwLNgPU0qGPzg/U/nRNG5Y X-Received: by 2002:a05:622a:84:b0:42e:ecab:582 with SMTP id o4-20020a05622a008400b0042eecab0582mr4268600qtw.68.1709547285077; Mon, 04 Mar 2024 02:14:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709547285; cv=pass; d=google.com; s=arc-20160816; b=BU2KXRQJrQJRS4ne6Bicu1PvUKCQo3GNx0dLLPJFvZewWswOiNglaD8UybU4S0xKYG DzLqjyJHhin8VXu6Kf5fJJfMezqNrY/oJA0YxWdpcar6csV7DIcnRPvUvB4/oWg1Y0nt VZJm+KIoFtDQQvf7mV81kBdCfnt+IYZRk8ROs4WMUmIM9MSNzl2Rb0gphH1QV5Af0Q0H 2oV63TQyiUh0KHl2QyyaCRgv2sDbz7UBzJQlSRvn8/3DQ9iI8ZtDsXD4qgzrktk2uzT/ L0kJ0/VahbMriCUkYZ7D7Aq6gYguDvtbXHvvAleSUG+TurVIqfCacCqHbNXtkxnFEham PuOA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=date:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:subject:cc:to:from:dkim-signature :dkim-signature:message-id; bh=JjiiERu9azu6SWbDWr4pKpCYy2SlURHt/nrJBAl1h1Y=; fh=XPJs5ZGCvlB7w9yfpC1hED1EJsKLDZjsVhRhMNCPkns=; b=Mrzp1DxLNQfu0GWHwVUAdo18YibKm5J8BYib/guOUT1QlOe6yOM/A1bnMqVXiefTw5 PScwBJW2rzWZc1WCaVHVWvwJgPZs8JZI+gX1TSBZlMDutD+bk9lt/cAG9rhYH0ZcXIvg Jz6MHxSJ7agQ6p/xlh6ok8+XF/n0ZCZ6SPXcnX8Ie6HgIwPaOml9ihvaCI6QUP6MPTEi psf6Y4sOSI7JwD6iAH//Ax/blio9gmZtcG6b3cA24J1Bn8ww6/Id25bZZL1tt9PiGUwp mY8yPFP1bnyuY+jAr825PiXGSM2F6+eFBBh5FAdIpaOT6x5V4yYqKD+VV00XeRL6ZXaY 559g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="T/53tueK"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90391-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90391-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547139; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JjiiERu9azu6SWbDWr4pKpCYy2SlURHt/nrJBAl1h1Y=; b=T/53tueKe10l1d+k71sAf8TP1Hj98kgPukmmg7e9npKY0SbnwTXurPJEINjp3sop4ispQH zRXHcPzn5+l8Q6vSmRvB5AUr8lymIZZ1EwmHaHyZpK8Iky5opS49s7GjFQnh/e5QoXkZGr +8Bf8hirsVGHAo3f9B05aQ/mFhm4jIiSQrySYEkYhMWjFFCQxYMIt3qpHOGjqkl0cuO2jj pvrg62BavUrUEY9h/DaMjk5dDmyQ2dL2dAFA0AO2weYA4kLtRic6c5IC8j6ndW0Hde2qvP oc00Gvk860ZFz9HWijHppw3Gw01z7LoZfKTIoGYyRGHa3KQQ4jwW7wP3ZpH1+g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547139; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=JjiiERu9azu6SWbDWr4pKpCYy2SlURHt/nrJBAl1h1Y=; b=/WAp4UrICNOMuK6YuFiovxtgIq4qvrMbHE2iTwY9A85zUpHj8F9CFJpKKWXB1n29tO4ORy ovTj+gEjKENOOCCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 2/9] x86/msr: Prepare for including percpu.h References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:19 +0100 (CET) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792590254442863182 X-GMAIL-MSGID: 1792590254442863182 To cleanup the per CPU insanity of UP which causes sparse to be rightfully unhappy and prevents the usage of the generic per cpu accessors on cpu_info it is necessary to include linux/percpu.h into asm/msr.h. Including percpu.h into msr.h is impossible because it ends up in header dependency hell. The problem is that processor.h includes msr.h. The inclusion of percpu.h results in a compile fail where the compiler cannot longer handle an include in cpufeature.h which references boot_cpu_data which is defined in processor.h The only reason why msr.h is included in processor.h are the set/get_debugctlmsr() inlines. They are defined there because processor.h is such a nice dump ground for everything. In fact they belong obviously into debugreg.h. Move them to debugreg.h and fixup the resulting damage which is just exposing the reliance on random include chains. Signed-off-by: Thomas Gleixner --- arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 1 + arch/x86/include/asm/debugreg.h | 24 ++++++++++++++++++++++++ arch/x86/include/asm/fsgsbase.h | 2 +- arch/x86/include/asm/processor.h | 22 ---------------------- arch/x86/include/asm/special_insns.h | 4 ++-- arch/x86/kernel/cpu/intel_pconfig.c | 2 ++ arch/x86/kernel/cpu/rdrand.c | 1 + arch/x86/kernel/fpu/bugs.c | 2 ++ arch/x86/kernel/step.c | 2 ++ 10 files changed, 36 insertions(+), 25 deletions(-) --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include --- a/arch/x86/include/asm/debugreg.h +++ b/arch/x86/include/asm/debugreg.h @@ -5,7 +5,9 @@ #include #include #include + #include +#include DECLARE_PER_CPU(unsigned long, cpu_dr7); @@ -159,4 +161,26 @@ static inline unsigned long amd_get_dr_a } #endif +static inline unsigned long get_debugctlmsr(void) +{ + unsigned long debugctlmsr = 0; + +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return 0; +#endif + rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); + + return debugctlmsr; +} + +static inline void update_debugctlmsr(unsigned long debugctlmsr) +{ +#ifndef CONFIG_X86_DEBUGCTLMSR + if (boot_cpu_data.x86 < 6) + return; +#endif + wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); +} + #endif /* _ASM_X86_DEBUGREG_H */ --- a/arch/x86/include/asm/fsgsbase.h +++ b/arch/x86/include/asm/fsgsbase.h @@ -6,7 +6,7 @@ #ifdef CONFIG_X86_64 -#include +#include /* * Read/write a task's FSBASE or GSBASE. This returns the value that --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -578,28 +578,6 @@ extern void cpu_init(void); extern void cpu_init_exception_handling(void); extern void cr4_init(void); -static inline unsigned long get_debugctlmsr(void) -{ - unsigned long debugctlmsr = 0; - -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return 0; -#endif - rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); - - return debugctlmsr; -} - -static inline void update_debugctlmsr(unsigned long debugctlmsr) -{ -#ifndef CONFIG_X86_DEBUGCTLMSR - if (boot_cpu_data.x86 < 6) - return; -#endif - wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); -} - extern void set_task_blockstep(struct task_struct *task, bool on); /* Boot loader type from the setup header: */ --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -2,11 +2,11 @@ #ifndef _ASM_X86_SPECIAL_INSNS_H #define _ASM_X86_SPECIAL_INSNS_H - #ifdef __KERNEL__ - #include #include + +#include #include #include --- a/arch/x86/kernel/cpu/intel_pconfig.c +++ b/arch/x86/kernel/cpu/intel_pconfig.c @@ -7,6 +7,8 @@ * Author: * Kirill A. Shutemov */ +#include +#include #include #include --- a/arch/x86/kernel/cpu/rdrand.c +++ b/arch/x86/kernel/cpu/rdrand.c @@ -6,6 +6,7 @@ * Authors: Fenghua Yu , * H. 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This also cures the related sparse warnings at the callsites in drivers/edac/amd64_edac.c. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/msr.h | 26 ++++++++++++++------------ arch/x86/include/asm/processor.h | 1 - arch/x86/include/asm/tsc.h | 3 ++- arch/x86/lib/msr-smp.c | 12 +++++------- arch/x86/lib/msr.c | 6 +++--- 5 files changed, 24 insertions(+), 24 deletions(-) --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -12,11 +12,13 @@ #include #include +#include + struct msr_info { - u32 msr_no; - struct msr reg; - struct msr *msrs; - int err; + u32 msr_no; + struct msr reg; + struct msr __percpu *msrs; + int err; }; struct msr_regs_info { @@ -323,8 +325,8 @@ static inline int wrmsrl_safe(u32 msr, u return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); } -struct msr *msrs_alloc(void); -void msrs_free(struct msr *msrs); +struct msr __percpu *msrs_alloc(void); +void msrs_free(struct msr __percpu *msrs); int msr_set_bit(u32 msr, u8 bit); int msr_clear_bit(u32 msr, u8 bit); @@ -333,8 +335,8 @@ int rdmsr_on_cpu(unsigned int cpu, u32 m int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); -void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); -void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); +void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); +void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs); int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); @@ -363,14 +365,14 @@ static inline int wrmsrl_on_cpu(unsigned return 0; } static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, - struct msr *msrs) + struct msr __percpu *msrs) { - rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); + rdmsr_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->l), raw_cpu_ptr(&msrs->h)); } static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, - struct msr *msrs) + struct msr __percpu *msrs) { - wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); + wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->l), raw_cpu_read(msrs->h)); } static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -20,7 +20,6 @@ struct vm86; #include #include #include -#include #include #include #include --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -5,8 +5,9 @@ #ifndef _ASM_X86_TSC_H #define _ASM_X86_TSC_H -#include #include +#include +#include /* * Standard way to access the cycle counter. --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -9,10 +9,9 @@ static void __rdmsr_on_cpu(void *info) { struct msr_info *rv = info; struct msr *reg; - int this_cpu = raw_smp_processor_id(); if (rv->msrs) - reg = per_cpu_ptr(rv->msrs, this_cpu); + reg = this_cpu_ptr(rv->msrs); else reg = &rv->reg; @@ -23,10 +22,9 @@ static void __wrmsr_on_cpu(void *info) { struct msr_info *rv = info; struct msr *reg; - int this_cpu = raw_smp_processor_id(); if (rv->msrs) - reg = per_cpu_ptr(rv->msrs, this_cpu); + reg = this_cpu_ptr(rv->msrs); else reg = &rv->reg; @@ -97,7 +95,7 @@ int wrmsrl_on_cpu(unsigned int cpu, u32 EXPORT_SYMBOL(wrmsrl_on_cpu); static void __rwmsr_on_cpus(const struct cpumask *mask, u32 msr_no, - struct msr *msrs, + struct msr __percpu *msrs, void (*msr_func) (void *info)) { struct msr_info rv; @@ -124,7 +122,7 @@ static void __rwmsr_on_cpus(const struct * @msrs: array of MSR values * */ -void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs) +void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs) { __rwmsr_on_cpus(mask, msr_no, msrs, __rdmsr_on_cpu); } @@ -138,7 +136,7 @@ EXPORT_SYMBOL(rdmsr_on_cpus); * @msrs: array of MSR values * */ -void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs) +void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr __percpu *msrs) { __rwmsr_on_cpus(mask, msr_no, msrs, __wrmsr_on_cpu); } --- a/arch/x86/lib/msr.c +++ b/arch/x86/lib/msr.c @@ -6,9 +6,9 @@ #define CREATE_TRACE_POINTS #include -struct msr *msrs_alloc(void) +struct msr __percpu *msrs_alloc(void) { - struct msr *msrs = NULL; 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Provide a weak function in the init code and remove the stubs. This also allows to utilize the function on UP which is required to sanitize the percpu handling on X86 UP. Signed-off-by: Thomas Gleixner --- arch/alpha/kernel/smp.c | 5 ----- arch/arc/kernel/smp.c | 5 ----- arch/csky/kernel/smp.c | 4 ---- arch/hexagon/kernel/smp.c | 4 ---- arch/openrisc/kernel/smp.c | 4 ---- arch/riscv/kernel/smpboot.c | 4 ---- arch/sparc/kernel/smp_64.c | 4 ---- arch/x86/include/asm/smp.h | 5 ----- arch/x86/kernel/smpboot.c | 5 +++++ include/linux/smp.h | 13 ++++++------- init/main.c | 4 ++++ 11 files changed, 15 insertions(+), 42 deletions(-) --- a/arch/alpha/kernel/smp.c +++ b/arch/alpha/kernel/smp.c @@ -467,11 +467,6 @@ smp_prepare_cpus(unsigned int max_cpus) smp_num_cpus = smp_num_probed; } -void -smp_prepare_boot_cpu(void) -{ -} - int __cpu_up(unsigned int cpu, struct task_struct *tidle) { --- a/arch/arc/kernel/smp.c +++ b/arch/arc/kernel/smp.c @@ -39,11 +39,6 @@ struct plat_smp_ops __weak plat_smp_ops /* XXX: per cpu ? Only needed once in early secondary boot */ struct task_struct *secondary_idle_tsk; -/* Called from start_kernel */ -void __init smp_prepare_boot_cpu(void) -{ -} - static int __init arc_get_cpu_map(const char *name, struct cpumask *cpumask) { unsigned long dt_root = of_get_flat_dt_root(); --- a/arch/csky/kernel/smp.c +++ b/arch/csky/kernel/smp.c @@ -152,10 +152,6 @@ void arch_irq_work_raise(void) } #endif -void __init smp_prepare_boot_cpu(void) -{ -} - void __init smp_prepare_cpus(unsigned int max_cpus) { } --- a/arch/hexagon/kernel/smp.c +++ b/arch/hexagon/kernel/smp.c @@ -114,10 +114,6 @@ void send_ipi(const struct cpumask *cpum local_irq_restore(flags); } -void __init smp_prepare_boot_cpu(void) -{ -} - /* * interrupts should already be disabled from the VM * SP should already be correct; need to set THREADINFO_REG --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -57,10 +57,6 @@ static void boot_secondary(unsigned int spin_unlock(&boot_lock); } -void __init smp_prepare_boot_cpu(void) -{ -} - void __init smp_init_cpus(void) { struct device_node *cpu; --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -42,10 +42,6 @@ static DECLARE_COMPLETION(cpu_running); -void __init smp_prepare_boot_cpu(void) -{ -} - void __init smp_prepare_cpus(unsigned int max_cpus) { int cpuid; --- a/arch/sparc/kernel/smp_64.c +++ b/arch/sparc/kernel/smp_64.c @@ -1206,10 +1206,6 @@ void __init smp_prepare_cpus(unsigned in { } -void smp_prepare_boot_cpu(void) -{ -} - void __init smp_setup_processor_id(void) { if (tlb_type == spitfire) --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h @@ -59,11 +59,6 @@ static inline void stop_other_cpus(void) smp_ops.stop_other_cpus(1); } -static inline void smp_prepare_boot_cpu(void) -{ - smp_ops.smp_prepare_boot_cpu(); -} - static inline void smp_prepare_cpus(unsigned int max_cpus) { smp_ops.smp_prepare_cpus(max_cpus); --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1187,6 +1187,11 @@ void __init smp_prepare_cpus_common(void set_cpu_sibling_map(0); } +void __init smp_prepare_boot_cpu(void) +{ + smp_ops.smp_prepare_boot_cpu(); +} + #ifdef CONFIG_X86_64 /* Establish whether parallel bringup can be supported. */ bool __init arch_cpuhp_init_parallel_bringup(void) --- a/include/linux/smp.h +++ b/include/linux/smp.h @@ -105,6 +105,12 @@ static inline void on_each_cpu_cond(smp_ on_each_cpu_cond_mask(cond_func, func, info, wait, cpu_online_mask); } +/* + * Architecture specific boot CPU setup. Defined as empty weak function in + * init/main.c. Architectures can override it. + */ +void smp_prepare_boot_cpu(void); + #ifdef CONFIG_SMP #include @@ -171,12 +177,6 @@ void generic_smp_call_function_single_in #define generic_smp_call_function_interrupt \ generic_smp_call_function_single_interrupt -/* - * Mark the boot cpu "online" so that it can call console drivers in - * printk() and can access its per-cpu storage. - */ -void smp_prepare_boot_cpu(void); - extern unsigned int setup_max_cpus; extern void __init setup_nr_cpu_ids(void); extern void __init smp_init(void); @@ -203,7 +203,6 @@ static inline void up_smp_call_function( (up_smp_call_function(func, info)) static inline void smp_send_reschedule(int cpu) { } -#define smp_prepare_boot_cpu() do {} while (0) #define smp_call_function_many(mask, func, info, wait) \ (up_smp_call_function(func, info)) static inline void call_function_init(void) { } --- a/init/main.c +++ b/init/main.c @@ -776,6 +776,10 @@ void __init __weak smp_setup_processor_i { } +void __init __weak smp_prepare_boot_cpu(void) +{ +} + # if THREAD_SIZE >= PAGE_SIZE void __init __weak thread_stack_cache_init(void) { From patchwork Mon Mar 4 10:12:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 209481 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp1326754dyc; Mon, 4 Mar 2024 02:15:26 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVj7SeFjKOqhGx1CtPLIpgCqOPrh61QI9wSX6Ez99F8UW7yNHN8Tu6QDs/LaAtdHPIpaHDHuSSn7qgxiPk2rAmVKn1j7Q== X-Google-Smtp-Source: AGHT+IFhJGw9BGBcNt9SQG+cb9srCm+XLPwdBdtTp7nsop5U59KlEY/AbcuJHShOwKj9/sC9BJE9 X-Received: by 2002:a05:6a20:3c8d:b0:1a1:1fee:5fea with SMTP id b13-20020a056a203c8d00b001a11fee5feamr418598pzj.12.1709547325791; Mon, 04 Mar 2024 02:15:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709547325; cv=pass; d=google.com; s=arc-20160816; b=hWH17jUop/i9Xq7OygtGW3MfLpWu8UtrBxXLnILOzv2S3hI5OQx8b44R2JJoVoLwNN CLF+OABYVvzQ3cDfhSkXE2iAd3g3TkLElfY7NeY+g2UlTs6Sk0L6wAX2k1l5uniNC30f 4l/yXsVOKbIckovWtV1RL99GPIr+SLqAcDqdSlNH1Iq8MuzN/1D4KdOnSPR+nyzz8Z5/ HNcCj1LrkVaThopou6N116fLCgEoNFHef2yITmnVXB8p0k0O+r3vDD2PZmKPRmF7b4Pz UCwPaVthBrrGR703ZN79SauPD6Yuv26RZvBpGoHQZvlNuBb2YxpS6N2D3sg1HPRaM5TH Q+jQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=date:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:subject:cc:to:from:dkim-signature :dkim-signature:message-id; bh=waWca13nkXlTk1KdzjjO2eUHwkXJkPInhR1X09TJX+0=; fh=XPJs5ZGCvlB7w9yfpC1hED1EJsKLDZjsVhRhMNCPkns=; b=PAjbuZD5ecpX6Pq6j1TJWdpTzb8ZkS1dArOhhl9HOHSW+5MOFNa84NXuI5WfoeK+aY 7UYH+BvaDeH2jAUx08fhmHIJf5NuGIP1qn59byc49Ay0IDn1CIU3ECvuGP4xIGmd5Qtr AWjtn+J35AI7NE6kH64nVDXP5HbboHwnKXSHsxC6x/X7Pe0DBn0bLya+fn02VYm0NOja +OCKqeM9xkRUMNvx0Ytxgc/nNwkFws4OYWKHTNy9KswK1eHibIo0PjzIXB3+q8PL7pgB 8XzqP8V0o6GTVuFXiD8r6mJ1fO5xg2QEj1GWWurwCONhzCuHNOmq5QW1Gu/fX8hWHc3w fl+Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="IENSuJ/e"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DybwRAza; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90394-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90394-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547144; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=waWca13nkXlTk1KdzjjO2eUHwkXJkPInhR1X09TJX+0=; b=IENSuJ/e6a+O59bFfGCzBu967ngLsRmjlrdNl9Yj+0nWcQ2bC0X2PFYcW/Ogp06sGMJLIB ELnjGItFWtLl/DhXffYbhfYuZWdTuAHy8P8NVHuKbhqqPd+K6BZJft2vySb2+rum2C09Aq cWLbAXlF9oprSMGGqHOjLNW9tMb08579es9MRNnrISA4hAX/P0g8vPVJRs53u0MiCEmg6E uPe2Xr/qEg48MKdoe0aRLao5JNxk0MSqCCwClODcnS+OboqfNXt0nkNhir9tdrbcBn9GiL H2I7NG7MHqA3R/H+15AKqhR+hAQvt2gdQuqJz62UKfwqHFHBPFCLeUK+U6W0Iw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547144; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=waWca13nkXlTk1KdzjjO2eUHwkXJkPInhR1X09TJX+0=; b=DybwRAzaUVoj3GiTZNCzx4w9/5h1J6i6awKRx6ALpGlnYu7RBOoHK+EpiWo6GAfyzSUvKj 08Qabz6R7eWQ3kBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 5/9] x86: Cure per CPU madness on UP References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:23 +0100 (CET) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792590296612498599 X-GMAIL-MSGID: 1792590296612498599 On UP builds sparse complains rightfully about accesses to cpu_info with per CPU accessors: cacheinfo.c:282:30: sparse: warning: incorrect type in initializer (different address spaces) cacheinfo.c:282:30: sparse: expected void const [noderef] __percpu *__vpp_verify cacheinfo.c:282:30: sparse: got unsigned int * The reason is that on UP builds cpu_info which is a per CPU variable on SMP is mapped to boot_cpu_info which is a regular variable. There is a hideous accessor cpu_data() which tries to hide this, but it's not sufficient as some places require raw accessors and generates worse code than the regular per CPU accessors. Waste sizeof(struct x86_cpuinfo) memory on UP and provide the per CPU cpu_info unconditionally. This requires to update the CPU info on the boot CPU as SMP does. (Ab)use the weakly defined smp_prepare_boot_cpu() function and implement exactly that. This allows to use regular per CPU accessors uncoditionally and paves the way to remove the cpu_data() hackery. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/processor.h | 5 ----- arch/x86/kernel/cpu/common.c | 3 +++ arch/x86/kernel/setup.c | 10 ++++++++++ arch/x86/kernel/smpboot.c | 4 ---- 4 files changed, 13 insertions(+), 9 deletions(-) --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -185,13 +185,8 @@ extern struct cpuinfo_x86 new_cpu_data; extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; -#ifdef CONFIG_SMP DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); #define cpu_data(cpu) per_cpu(cpu_info, cpu) -#else -#define cpu_info boot_cpu_data -#define cpu_data(cpu) boot_cpu_data -#endif extern const struct seq_operations cpuinfo_op; --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -70,6 +70,9 @@ #include "cpu.h" +DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); +EXPORT_PER_CPU_SYMBOL(cpu_info); + u32 elf_hwcap2 __read_mostly; /* Number of siblings per CPU package */ --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1211,6 +1211,16 @@ void __init i386_reserve_resources(void) #endif /* CONFIG_X86_32 */ +#ifndef CONFIG_SMP +void __init smp_prepare_boot_cpu(void) +{ + struct cpuinfo_x86 *c = &cpu_data(0); + + *c = boot_cpu_data; + c->initialized = true; +} +#endif + static struct notifier_block kernel_offset_notifier = { .notifier_call = dump_kernel_offset }; --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -101,10 +101,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map); DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); EXPORT_PER_CPU_SYMBOL(cpu_die_map); -/* Per CPU bogomips and other parameters */ -DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); -EXPORT_PER_CPU_SYMBOL(cpu_info); - /* CPUs which are the primary SMT threads */ struct cpumask __cpu_primary_thread_mask __read_mostly; From patchwork Mon Mar 4 10:12:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 209482 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp1326914dyc; Mon, 4 Mar 2024 02:15:45 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUKBbxMmA1K4SCfVwhTIYhXUKnK8m5sWoKnG5AwD47RjVKFe4Ho3pXWQAhyzL8/fnEnb8dmmnp75f74aBFEMp9GqjaUtg== X-Google-Smtp-Source: AGHT+IHtEbbDeCt4ARbV3Xa6C+KxDLHAeW81kR396CxchL95oIW/g6B7S7SzvWHQscs7yEJ1mHnd X-Received: by 2002:a05:620a:6888:b0:788:1ddc:5483 with SMTP id rv8-20020a05620a688800b007881ddc5483mr6666408qkn.64.1709547345111; Mon, 04 Mar 2024 02:15:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709547345; cv=pass; d=google.com; s=arc-20160816; b=HD4pAUy65auE9EhtUvn9nwLBjA+k8d/JWXFN5jvPYCwXnauHC78uKl2rmq6J/KtFpf mt+PJ37ipXaQ9H5RSSR5XvdYlrJydRbON3DTzAvWDtRXspXMJL2gjfyl8PXEgVnl5p+X vnA91Vh80Dj/wH4i4c1LRrQdQ68zRCmsfrtp16Izq8jj6FLud4OqvEew4M7At5CmKcFK dQhZBNdrWN3/N8UybbXp3Rr40atxbtzxAXAMYqG/rNZeG5jDtMUpVa8+SRo8YsbrE2Ag d5nofu6cenAgMJ0afslOQT7HzIwfUuA3NYHra7tXhmjZpxpkvh5J0j0+YPSv5NiB1Whm 6mhg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=date:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:subject:cc:to:from:dkim-signature :dkim-signature:message-id; bh=JtmrisRHZR6UF3WBSqph8+Mk5bBFqrMgy9HjBdcJVEk=; fh=XPJs5ZGCvlB7w9yfpC1hED1EJsKLDZjsVhRhMNCPkns=; b=ARwVF9eBbl46rb3xvRdZ98pUzGHxHJRGhsKg5LgfFGRwzOGfQh9+2NuieojvxtDYFY t7izbVTFX3cVw9ROUNtQBPZeMkV3XhLKpRtxnyYBXn468ve3yeKainkLj3fhorWNokBP /TP8agwIApZUjfaxw5iIXmu4OQSdvYKAGCd5yHNQOPqkWe4cqtKhxWZgFaxLFigUSG6F f9q4iTpsdUU2qEaAZuGSH14y46NgkYONlb1XAkof2J3GCrlBWgF6pY7TuLiOhz3pBKU9 OfZbtsrUM33eLf0ZvzI0yh1M4oHAdSiFrp0rrdUbyyA8yvoqcA1vfeWE08WdptefU8Lr uJvw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=eDZv0UmS; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90395-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90395-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/uaccess_64.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h @@ -54,7 +54,7 @@ static inline unsigned long __untagged_a * half and a user half. When cast to a signed type, user pointers * are positive and kernel pointers are negative. */ -#define valid_user_address(x) ((long)(x) >= 0) +#define valid_user_address(x) ((__force long)(x) >= 0) /* * User pointers can have tag bits on x86-64. This scheme tolerates @@ -87,8 +87,9 @@ static inline bool __access_ok(const voi if (__builtin_constant_p(size <= PAGE_SIZE) && size <= PAGE_SIZE) { return valid_user_address(ptr); } else { - unsigned long sum = size + (unsigned long)ptr; - return valid_user_address(sum) && sum >= (unsigned long)ptr; + unsigned long sum = size + (__force unsigned long)ptr; + + return valid_user_address(sum) && sum >= (__force unsigned long)ptr; } } #define __access_ok __access_ok From patchwork Mon Mar 4 10:12:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 209483 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp1326972dyc; Mon, 4 Mar 2024 02:15:53 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXUO4xMXcm7Y9GWE945PEM2VcUeNTnEjU9WJFNl7eD1wXQVZErSTtukDqTs/e7Kzao2mdt6tY3I/u5dAcx8NeuE+8Nkjw== X-Google-Smtp-Source: AGHT+IGBtsvxNpi2MNYJMrALfhvOjRgCg/nvjFcnbpI7uMhvKL1UNh9EnNiJ/Q2/2FIejdLn4F9x X-Received: by 2002:a05:620a:248b:b0:787:c569:edea with SMTP id i11-20020a05620a248b00b00787c569edeamr11773167qkn.53.1709547353770; Mon, 04 Mar 2024 02:15:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709547353; cv=pass; d=google.com; s=arc-20160816; b=yIRoo8N0wv7+SN9xpV9XClVuoWvq2AQT1XHkItQZPWBeM/46bZMQCMKoTEqvkikvHW p7qKfJH3zuajZHdvDPhu1OXUZMb80Az5w0A+8/dOzm+rDSDO0AbSkKLfM52KyH6wKmQv w5Ld8b0fAr3v8gH3YtCjnkmpEE8wiSJkugLw3GgWuB4I6qURANRw8GYsjhJzcwi5HZWj dxQ7YzjdcYplWYmw5eeMrJodxY5m80fR8b+j4ovkOegEJuaBnvI1/xzS9u0SF7RotMW1 h9dJYWaqdJVM8MWMbL/g+EQhvD71eLhcWIiuM90nILocPMGnDz0AzG8V6wIJLvVB90DS UVig== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=date:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:subject:cc:to:from:dkim-signature :dkim-signature:message-id; bh=P1puNPiaRZsJi3LvDbzvEOsTfk74hgQ7qSp99Hl7hDM=; fh=XPJs5ZGCvlB7w9yfpC1hED1EJsKLDZjsVhRhMNCPkns=; b=DSpiozor/v8B/Zpn+99n7OZQyBjpvZd3SK9kMPObJZNzfJny93n/i3XMLfAXQBavZm bvkgkBCgSq9VWo2IrDpDRedU75kZIrH5UGNmE95kHrmEWUBvF7QUmt+iuWMbNIwusuaw UGvvcakKAhX0DNx48C4fs00lm/qI0P1HgeXPcEW/biy2aRgSlvxNIAEg+YZOVQcmmpuY hBZvHczOsyiI0xGSphsB0vaqbubTESHyKvhUMKvAKFv5KEzOW6HX/YDRq2M5kf4seI1Y lPYGc1GEh6+gjo7OxO9evZ6phUfvE95WQTmbtIdyJ8eVgztx7HyuY51Ym+Uw13ZSUnB8 I+kQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="oDT/Xu+F"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90396-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90396-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Use EXPORT_PER_CPU_SYMBOL_GPL() instead. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/bugs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -56,7 +56,7 @@ EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); /* The current value of the SPEC_CTRL MSR with task-specific bits set */ DEFINE_PER_CPU(u64, x86_spec_ctrl_current); -EXPORT_SYMBOL_GPL(x86_spec_ctrl_current); +EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB; EXPORT_SYMBOL_GPL(x86_pred_cmd); From patchwork Mon Mar 4 10:12:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 209490 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp1329641dyc; Mon, 4 Mar 2024 02:22:43 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU1MnBHruVOmIDORBFJQ6gL6dXwxOApooJ4eC03MfhocVz2ISqc19D3Efz7WrxoMU1dpI0OXlGUJBeeV14tfNc3xtueiw== X-Google-Smtp-Source: AGHT+IHr/Yj9LSk3JSayjfDGHCPvH8bsYlyEu3vH+v0WCvUxiM5TeSUQTvHk21Grxj8jPI9pUTok X-Received: by 2002:aca:d04:0:b0:3c1:eb85:f478 with SMTP id 4-20020aca0d04000000b003c1eb85f478mr3091128oin.51.1709547763058; Mon, 04 Mar 2024 02:22:43 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709547763; cv=pass; d=google.com; s=arc-20160816; b=XEj1gr5yT9Ufzzb8IHOV6OoGsseI5bSfT/GbFVGkzVfDkG2xSqyqVZ+GR56RYDZf9n R9ARfkP+ROelOiEIAwZVVLV3V9IqBwoKSpWhUWifBsMwqCmKGocizYrykALBLbs3/P4+ VUKfw4bCQumpYvSeBigExM7jKBczUMqfhwJb3jOe1hkAH+rOpD//HzFvhs8GdAt3KeQp 6XtYw7bXyVQhTwpVzDrPPKBvmwE6Zf+9sCRkV+NcmS+6zjfKy6mGCBTCWtTJU1LoVOOu OqgBMJJj/jQa5TkpRTMhe8QlIRae9+UiZPcewDrReotQJkYDtI3VNaQ0Jl/6IZG+hACY is3Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=date:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:subject:cc:to:from:dkim-signature :dkim-signature:message-id; bh=6Jgk9G7c0E4dzMxbvaTsjGPBA2bcPCPscX5bks01Uro=; fh=XPJs5ZGCvlB7w9yfpC1hED1EJsKLDZjsVhRhMNCPkns=; b=uBLMKOFeRV/AuinIWPzJ9kJfLnR0dQdytzndykWScNzZbTN8HSEIvWPpSRO4exXIeH 7Ab2QULCi+JIbCjsovNiamdTh4v2uCZrOCEQ7yyjR3Bx0GayYKzDejV1uycTTQzV10U4 1XZVgK1/ZwLcEJ2Kdtwh89DL/tRWdl/Vhhk6t+Fh7ux4Zjx8B9b1vsYPA5uAmvliyx4W uB4DmPbrvpBoROd0dGDEmiGpke2j8WcDXrA/ViqZGF2aIaE6PsjcoeKoEhqnethWipGr tQuzptDe2OI0NnoaJureF+9LQitBttS/3Ocat7MXGQceYB0MwhhPTW8wUZXBUAtgjMtl XIgQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=NO8lSC7k; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=90m2Rl2o; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90397-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90397-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Should it be static? Add it to spec-ctrl.h where it belongs and remove the one in the kvm code. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/spec-ctrl.h | 2 ++ arch/x86/kvm/mmu/mmu.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) --- a/arch/x86/include/asm/spec-ctrl.h +++ b/arch/x86/include/asm/spec-ctrl.h @@ -96,4 +96,6 @@ static inline void speculative_store_byp extern void speculation_ctrl_update(unsigned long tif); extern void speculation_ctrl_update_current(void); +extern bool itlb_multihit_kvm_mitigation; + #endif --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -53,12 +53,11 @@ #include #include #include +#include #include #include "trace.h" -extern bool itlb_multihit_kvm_mitigation; - static bool nx_hugepage_mitigation_hard_disabled; int __read_mostly nx_huge_pages = -1; From patchwork Mon Mar 4 10:12:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 209491 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp1329718dyc; Mon, 4 Mar 2024 02:22:54 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUUD4U1lp1jdfuxsPoEkc+UrhDTnOMAeVm/cNROa9FNKcYm6uYbOroV+YWlBEE+uRZGm6FyMqiqv96mGVcMYrwlgczlBw== X-Google-Smtp-Source: AGHT+IEhncNj78m/esh36k0Id/7miGCxCrXMZELR60SPM/aOQ+3Asj/2BC4oKhzRGCd/C51ijXiK X-Received: by 2002:a17:903:230a:b0:1dc:68b6:9243 with SMTP id d10-20020a170903230a00b001dc68b69243mr11321755plh.58.1709547774779; Mon, 04 Mar 2024 02:22:54 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709547774; cv=pass; d=google.com; s=arc-20160816; b=pnXwumG2w0BOKzmAZmTYA2iDOl9/Rj5GzqF6fWdbtRvuEDYqzQvQX28Eb0QitlqKW4 BTYiww0QlVyDguRXEcFAmrH2AtvfCt/tRK/XiXaQnrIL6Ia3GD/mazUyba2M5mJiM3JJ NKnW4qrP820FUuHQJvJqna+ChVJak12/GlMibWVCTtHnFJ/vcNQzwmn9myLolEEjwHaI hm1iwZ4teZYpGjUjcqHzuIFoBlAd/z/2slc6OA4VdmUdowu+cagSH/b0YxP9+bZz3LSR RogQb5MESEAIdi6D5Mso5tDwLrJnH8CFqsIIeUg18UE2jl15P2/JAcL//2I96cOyOLeh inKA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=date:mime-version:list-unsubscribe:list-subscribe:list-id :precedence:references:subject:cc:to:from:dkim-signature :dkim-signature:message-id; bh=CNfpfUdf+bJ/WXlKRuxwbcf+mJAjRsom7OLtmfNUsUs=; fh=XPJs5ZGCvlB7w9yfpC1hED1EJsKLDZjsVhRhMNCPkns=; b=k2LVJk9QrarJLXh9MSMZ3oIeF5+aQfIPB1MxnGDahFNe85Khx3jSK03eYtzvAvemMH cAxZpg8jkaB4h2L7sMfPdEwrnoRubDoxROF9/gNvTeeZHvOJ1rxJoC2u9zBz4Rvrt5fR ewFeAG0Ra8IUyVITGZkMbuP62ecEVx04bS5i9aQgskTjfO/b00oUujRz2GugQBrEdmuA sTXy8Pn355ow65GEoQX2qfPis1v7brBIm+LkZ8W/WOQWGWg3fFL1SIEpyzT/OfncJ/Ex SV9MlzjdXkjXrqVG9tSzUNPM4vhIUk6nvcaVy88lfU0bjmpgSmsbREptu6yQ49UCpLHc GgEA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=oF47lkb4; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="bC/zpfQn"; arc=pass (i=1 spf=pass spfdomain=linutronix.de dkim=pass dkdomain=linutronix.de dmarc=pass fromdomain=linutronix.de); spf=pass (google.com: domain of linux-kernel+bounces-90398-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-90398-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1709547149; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CNfpfUdf+bJ/WXlKRuxwbcf+mJAjRsom7OLtmfNUsUs=; b=oF47lkb4Rk/qvj8Db0DRNJP1DueeQS9kXvhHnhNzDRR8etK9qNQysmWn7gl1vnhJGoyRVU G3nly8CjbNeLALkuKp6qhtOlQd+IXybJsPeFN902wLcz/8bciN4T9Ts55RgXlE5yXECQ4P r0ndTbug4smvpyy4oBE5xvh0KjUTBclNR58/LW3vsJX66Po7iz+XKA54haE3NDtexiWtfE j/YvojK59blwLY6kn3bHJN7VVH/HW8RXyhm4kDQtDYTYj6yf8zCphUO2GgAQU5u39vfP7p BH3jv35bwdDorlupW8PDfesjvd9M9ky6L2OXWfJz+TUUtjJFZ1GURBq9K8kkRA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1709547149; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CNfpfUdf+bJ/WXlKRuxwbcf+mJAjRsom7OLtmfNUsUs=; b=bC/zpfQngeugmwtDkBFAMAJ1oOblN8I8e29J1a4Gq0IsYlUkp4Ep8z7A48ioHN+x2JjHE3 QcneLlx7+eISCTAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Linus Torvalds , Uros Bizjak , linux-sparse@vger.kernel.org, lkp@intel.com, oe-kbuild-all@lists.linux.dev Subject: [patch 9/9] x86/callthunks: Use EXPORT_PER_CPU_SYMBOL_GPL() for per CPU variables References: <20240303235029.555787150@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Mon, 4 Mar 2024 11:12:29 +0100 (CET) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792590767307870259 X-GMAIL-MSGID: 1792590767307870259 sparse complains rightfully about the usage of EXPORT_SYMBOL_GPL() for per CPU variables: callthunks.c:346:20: sparse: warning: incorrect type in initializer (different address spaces) callthunks.c:346:20: sparse: expected void const [noderef] __percpu *__vpp_verify callthunks.c:346:20: sparse: got unsigned long long * Use EXPORT_PER_CPU_SYMBOL_GPL instead. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/callthunks.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/callthunks.c +++ b/arch/x86/kernel/callthunks.c @@ -44,8 +44,8 @@ DEFINE_PER_CPU(u64, __x86_call_count); DEFINE_PER_CPU(u64, __x86_ret_count); DEFINE_PER_CPU(u64, __x86_stuffs_count); DEFINE_PER_CPU(u64, __x86_ctxsw_count); -EXPORT_SYMBOL_GPL(__x86_ctxsw_count); -EXPORT_SYMBOL_GPL(__x86_call_count); +EXPORT_PER_CPU_SYMBOL_GPL(__x86_ctxsw_count); +EXPORT_PER_CPU_SYMBOL_GPL(__x86_call_count); #endif extern s32 __call_sites[], __call_sites_end[];