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Reviewed-by: Manivannan Sadhasivam Acked-by: Rob Herring Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..5ad5c4cfd2a8 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -834,6 +834,8 @@ allOf: - qcom,pcie-sa8540p - qcom,pcie-sa8775p - qcom,pcie-sc8280xp + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 then: required: - interconnects From patchwork Sat Mar 2 03:59:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 209172 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp302351dyc; Fri, 1 Mar 2024 20:01:16 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCViGvsSlI9saVJ6PMgLk7IW9P65GmBtAz2tcYMgB+ulsAwJnM209O2HNik6RhJLPDkXgoNewh/NorvyZeKIC9CkKEDuvg== X-Google-Smtp-Source: AGHT+IFZVweWiDuFXsRlJJCLfhNlz+zsSQYaaBoEbwobPZ6uBjJyszdAU9tzbPoWCO/JV/SRycHP X-Received: by 2002:a17:906:1906:b0:a44:7db8:a343 with SMTP id a6-20020a170906190600b00a447db8a343mr2506010eje.76.1709352076209; Fri, 01 Mar 2024 20:01:16 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709352076; cv=pass; d=google.com; s=arc-20160816; b=AngmS3ahVNW1nizeWZIPBTYZFYWJZ9S7Din0HP/jbFc7GJEUlfIYLFNrBo1CKrdGTX dyna2hh6VwXmh+A+F/meSYwX4RS1yTV3k2VKLUrOvwXuiWF+Gaj34JrliHYgfMvyjIzo SxWm2jguQKtoUQyAdi8kjpkY8M72zvR5NNpwFN8JmAnEgyL9/nC0fAABdncgsEbq1Wgh UVnEPMvwvOlTw4nR55q25PAszwN+I2lwy33NtNgJIKSfdv2ljybcWvftljQKQYFjiwEw Ei9DbWjw4OP0eTKUf/1ao2IdoSPHrWBnVsSJQki3gHA/UlrRFJw3K1FrB04HKWFneQp8 4Gmw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=3FogZb3RjOu/p0gevLn/krzCPQWG9ibDSved21e76mM=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=0VeG4y3exlm8DsTRCn+YX93oP66cR8O9pQj3982Oid3+vGsc8NrVPKRx34NYkrhVCb bdmV0iOu3XOoEq1QVehboGORswOiXnUhCv9/tCq2eMH/7WtQfRCLDogIDZHGOXPRJE4m HssZUKyKiOI8j9ngHJu6GcVCtPWto99aAIGpxapscrssGDdjiwR4U1Ryd97AvrUfFelU wqXkkJzlPHAERQMLJJarO1J+OenJUD1jIJZDFVPKHDimqGIMLzawPUsfdpwFEn8O40TZ jPvtT0XGPgcfo0brCjIMEWnDswGj3YLdmk+au1dENAMzTIC7LmxvCVE79w4kaBMp1DuZ aTvA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=QxGaPWEE; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-89323-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-89323-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..6b1d2e0d9d14 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1781,6 +1781,10 @@ pcie0: pcie@1c00000 { <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie0_phy>, @@ -1890,6 +1894,10 @@ pcie1: pcie@1c08000 { <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>, From patchwork Sat Mar 2 03:59:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 209173 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp302440dyc; Fri, 1 Mar 2024 20:01:31 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCW6B47Gd1AdzQvH1INaY8Duhiirp/xW/Bhe/R2PwT3UlmIHpPhR+tZrGZiZXW9eNewNCjrcyyo3GykZPN9RV/XBA31gHA== X-Google-Smtp-Source: AGHT+IHYvsFMtVBkshTTvCF0exz8jq23IIPR6jer28dIGL4+DF+kiB21qX/wtaDc/4NZAdiIj/s8 X-Received: by 2002:a17:902:ed85:b0:1dc:90d6:1dd6 with SMTP id e5-20020a170902ed8500b001dc90d61dd6mr2861241plj.28.1709352091025; Fri, 01 Mar 2024 20:01:31 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709352091; cv=pass; d=google.com; s=arc-20160816; b=DJczY3OXD8q530g0k+JO73gTL9Nfx10pRWEM6Nx5YM9slAemAMIHaoSd6FkYIRBd0O jtrq0W1+sf8vFrVzekeUoFx1mziYR0mL20TXJvIjchhXAzx4HNv9GIX349g/wCK1cIx/ RcaMJMK9Vo/+L8D7zUtaJN5htbG0e7/kvZKlm7nL2jM3rlCfj2CHtgiqSNDtFW1EvBmk /RwYjZwdWrDxf2p42p0xzptWVCvD3tHCZ2BbpOXuwx/fy9QHN557cssg1EOOFSOMVRJ8 k1yZ1AWwKvMZroghzUseJHYVHxTbDDmt8wbEjFQKpeS5ET0EFeK6hP+LXz+6j+CmIxF5 Lbeg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=JTt03ap6invxnj8mxB5rD01WcQ5nu+m9RxcfWbtVUag=; fh=5wKdp1w3tJCZLDv0YnxzrGW5vWq2MtI74/8F2XmS3Nc=; b=Pq7rZ3X/O4bSzN6ndEAf2sQ+VeEihbepDSZiXr4GfRMqqIdj4Hxc7Q82dZlXv4oTBi C15fNLJWRyM8SrekZIL8E/VzPFPap67fDWFTwsrw4D+60nuIRcN7opf7AOM8I+Cuea0Q xCme5TRMV753sdlt1pg9xuYk5/gs7LfEb0JU+Igd6vT/Rz+qkwIWgbqQL+IIbEryugej QMydHRevitQ8GxxMYfS12ZHZevTXkNuofAATgnbaJrunqOYSGxypP1SeoGMOfb8d3nJ8 UOQzW/LR2mkAr5qT/SuLxb2HLdYFv17DgM1Xvxk/sPxM60AXfSU9epZU+G0E6k2cWxii t04g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=M00g1QlS; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-89324-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-89324-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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We are surviving because of other driver vote for this path. As there is less access on this path compared to PCIe to mem path add minimum vote i.e 1KBps bandwidth always. When suspending, disable this path after register space access is done. Reviewed-by: Bryan O'Donoghue Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 10f2d0bb86be..a0266bfe71f1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -240,6 +240,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; + struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; @@ -1372,6 +1373,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) if (IS_ERR(pcie->icc_mem)) return PTR_ERR(pcie->icc_mem); + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); + if (IS_ERR(pcie->icc_cpu)) + return PTR_ERR(pcie->icc_cpu); /* * Some Qualcomm platforms require interconnect bandwidth constraints * to be set before enabling interconnect clocks. @@ -1381,7 +1385,19 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) */ ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + dev_err(pci->dev, "failed to set interconnect bandwidth for pcie-mem: %d\n", + ret); + return ret; + } + + /* + * The config space, BAR space and registers goes through cpu-pcie path + * Set peak bandwidth to 1KBps as recommended by HW team for this path + * all the time. + */ + ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth for cpu-pcie: %d\n", ret); return ret; } @@ -1573,7 +1589,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) */ ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); if (ret) { - dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); + dev_err(dev, "Failed to set interconnect bandwidth for pcie-mem: %d\n", ret); return ret; } @@ -1597,6 +1613,18 @@ static int qcom_pcie_suspend_noirq(struct device *dev) pcie->suspended = true; } + /* Remove CPU path vote after all the register access is done */ + ret = icc_disable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "failed to disable icc path of cpu-pcie: %d\n", ret); + if (pcie->suspended) { + qcom_pcie_host_init(&pcie->pci->pp); + pcie->suspended = false; + } + qcom_pcie_icc_update(pcie); + return ret; + } + return 0; } @@ -1605,6 +1633,12 @@ static int qcom_pcie_resume_noirq(struct device *dev) struct qcom_pcie *pcie = dev_get_drvdata(dev); int ret; + ret = icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "failed to enable icc path of cpu-pcie: %d\n", ret); + return ret; + } + if (pcie->suspended) { ret = qcom_pcie_host_init(&pcie->pci->pp); if (ret) From patchwork Sat Mar 2 03:59:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 209174 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp302524dyc; Fri, 1 Mar 2024 20:01:46 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUtVoFbTIV66rOAtVphUH3SEoOjij3ImTaOpVxd2i+NbgUXCm8jV1vqm/yopS8fWkk635juzygMWzkk5sccnuaDpCVFUg== X-Google-Smtp-Source: AGHT+IGGplddT+Cj/XgjtKXv0Kg1XyvsDxtDtcCLH6FUuNFQHJF9iZO516GbRqNNyI2FuwZclFOb X-Received: by 2002:a05:6a21:33a8:b0:19c:9b38:f398 with SMTP id yy40-20020a056a2133a800b0019c9b38f398mr4431002pzb.22.1709352106679; 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Sat, 2 Mar 2024 04:00:37 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 1 Mar 2024 20:00:31 -0800 From: Krishna chaitanya chundru Date: Sat, 2 Mar 2024 09:29:58 +0530 Subject: [PATCH v8 4/7] dt-bindings: pci: qcom: Add opp table Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240302-opp_support-v8-4-158285b86b10@quicinc.com> References: <20240302-opp_support-v8-0-158285b86b10@quicinc.com> In-Reply-To: <20240302-opp_support-v8-0-158285b86b10@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Rob Herring , Johan Hovold , Brian Masney , Georgi Djakov CC: , , , , , , , , , Krishna chaitanya chundru , Krzysztof Kozlowski X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Adding the Operating Performance Points table allows to adjust power domain performance state and icc peak bw, depending on the PCIe gen speed and width. Acked-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 5ad5c4cfd2a8..e1d75cabb1a9 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -127,6 +127,10 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + operating-points-v2: true + opp-table: + type: object + required: - compatible - reg From patchwork Sat Mar 2 03:59:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 209175 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp302692dyc; Fri, 1 Mar 2024 20:02:14 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVZeFlBcjSa3POBel+M7sEBza6H8+MMgxRB1oUh+hPLiFm73Ult5rQT6aUxAu/w4CvVzedIigYyjK6RdXTrXzdhy87Vpg== X-Google-Smtp-Source: AGHT+IGu/IwZy4XO6keEnYOF2Zi5orvtKVvv+a7+wc7l8F7+OcPO16McMPgwezU63Xvzu6VPoLq2 X-Received: by 2002:a05:6402:2695:b0:566:9fef:1ee9 with SMTP id w21-20020a056402269500b005669fef1ee9mr3437276edd.22.1709352134562; Fri, 01 Mar 2024 20:02:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709352134; cv=pass; d=google.com; s=arc-20160816; b=vUPq7nK22xO3y2Jk/pRXeyAocVvLpAPjUKwxlsMAp4LkXslvOBn7LfbqbipCuCQrRE XmCO8caGcF8Y5l48Ls0wKKR3mBgdg4FWhs8FD9AzF3ABuqLvdeJiyOxSV/giMkLwhzly g1N5d0uU0YmR5paakNM0wwJFHQn4dMjGBfTqp/8zq4nUTVslOm5IXWllI6+W48AxXIiG 2x57xC6fgTqP/EASq7I9H7cteYPsFTQUmdT0XZ8MmZhQKqQBLSfQtegRjSx0zBC5IEtt s2aw9OXxn/BOhuN1G/Ee1D1HxAUTkSNiL1FPW3lO9P9YH9gMkYig63uPAODuK4UO+O9A nJdA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=MWJFlLU/eSswcHRepliMx7VnE186DBZvx1uc7BliI60=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=eIuc4ICR4jORo8aTW38tdYrx886+Ql/KxVMiEWNB25Rx2jTiYhM3ox3bR8BrraVkHh 1ZYIq89xnIGt2D4GK3jY6DP9ZSZ2Tq1vBcbM469uI2Ah8Y0g2uqf/vRjjqrDbp1LeAqv wc5ymfMvnVsyVj1DsMs1LoO8f4l0hIjDGIk/KGH6w4S3YFsRa/2vHJYE0Kq6zufZdcfk cohczitAIBchywHu3sBLtrOIM5mJ/6Ds4MQHdS2gc97R0RVNTE/cOs6J36OzGtEqSZyh IFAqP+lTGN+yR08nTT0SiR1Zc3zZIzXKVMZ/M+43EFc5Xb6A78G4HNYYZjuSZ1ma7Ywy DCFg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=U8tIVKdP; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-89326-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-89326-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Add the OPP table support to specify RPMH performance states and interconnect peak bandwidth. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6b1d2e0d9d14..662f2129f20d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1827,7 +1827,32 @@ pcie0: pcie@1c00000 { pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + }; + }; pcie0_phy: phy@1c06000 { @@ -1938,7 +1963,56 @@ pcie1: pcie@1c08000 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1x2 GEN 2x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3x2 GEN 4x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + }; pcie1_phy: phy@1c0e000 { From patchwork Sat Mar 2 04:00:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 209176 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp302745dyc; Fri, 1 Mar 2024 20:02:20 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCW/u/lgDqqNfNHCDn1MyP2RxgordInHqX0wdsu3uUsT0Wwhl5XiKUV21Y0YQw6pitxMtllL83WSPMYMwM7qZJPlMzr7Xg== X-Google-Smtp-Source: AGHT+IEbj52eo2SQj59o1grGktDTv3WkU1w3knudRuurxYsdcPCgBX/lwr890TcdU2Ocw4gB5zNr X-Received: by 2002:a17:907:11d9:b0:a44:1893:437d with SMTP id va25-20020a17090711d900b00a441893437dmr2689020ejb.7.1709352140511; Fri, 01 Mar 2024 20:02:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709352140; cv=pass; d=google.com; s=arc-20160816; b=y7pZ0660MmlHcxdNMl2yGn9+rW+yFqDXGAejq8DGr+VfRi7tAXAdrTgwb8aadd4rcF JpjVrIvJyB+17tv1OkhV12oyspNKK1Gt5k/Bwc0c83gPthicsMX6iB93ixbroxAKKAKA DevZMtcK8tYE/Y0ko8bo6SgWUyw6A+SapOcFB6HN+SS77r21z4bOx6dGtZr5rX+SxMKd gqfnL10mUfi9HobKjFlalSSZhBCj30WqPTqxDrhvLnvNKiQ5RJvTKRAB2FTMo+WTZxQM 0o70BmvkFknXYTjZy2wCbnZ/peiEPdQ685fKd1++QMP2EyYhh8CrlrIUynX6ysGHMbMk cHlg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=NzS2INWWqVE2VaxwVYFo0ZkDao5Z7uZu2P/3PWHMcGI=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=Y3AGVTGrdUHgsSMbe4Zr2GNcN9LxGlQWVoHTszsO3o34HAY4usHRRk8n61WHUqPMaa jjaSf2kVhY2QzT5jdM9MTFeuz3+23rXqiM2I1UBdX+ErbDypTsMBATr3DFbG+ncS0ais u2ctH/PfBN7b4bd+YulR5SV3OtUdiapFMjsZezC+OIq31Ab9cqSLFmSEDAVRdwD3AQWk oByyzM+VZ8p9kEr+naF3juZWD5sRPtjUvqX4dNm0wNZhZpNs/NqZRDM0e5x9tbYIni8f ru71MViKlcFrlgEbwxZ0Xsg86EWc2Jdq5QVDIy12napXB+3shz/00VSKIO7/DSgYwKxr dCQA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ccl2kzYj; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-89327-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-89327-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/pci.c | 19 +------------------ drivers/pci/pci.h | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d8f11a078924..b441ab862a8d 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6309,24 +6309,7 @@ int pcie_link_speed_mbps(struct pci_dev *pdev) if (err) return err; - switch (to_pcie_link_speed(lnksta)) { - case PCIE_SPEED_2_5GT: - return 2500; - case PCIE_SPEED_5_0GT: - return 5000; - case PCIE_SPEED_8_0GT: - return 8000; - case PCIE_SPEED_16_0GT: - return 16000; - case PCIE_SPEED_32_0GT: - return 32000; - case PCIE_SPEED_64_0GT: - return 64000; - default: - break; - } - - return -EINVAL; + return pcie_link_speed_to_mbps(to_pcie_link_speed(lnksta)); } EXPORT_SYMBOL(pcie_link_speed_mbps); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2336a8d1edab..40403783229f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -282,6 +282,28 @@ void pci_bus_put(struct pci_bus *bus); (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 0) +static inline int pcie_link_speed_to_mbps(enum pci_bus_speed speed) +{ + switch (speed) { + case PCIE_SPEED_2_5GT: + return 2500; + case PCIE_SPEED_5_0GT: + return 5000; + case PCIE_SPEED_8_0GT: + return 8000; + case PCIE_SPEED_16_0GT: + return 16000; + case PCIE_SPEED_32_0GT: + return 32000; + case PCIE_SPEED_64_0GT: + return 64000; + default: + break; + } + + return -EINVAL; +} + const char *pci_speed_string(enum pci_bus_speed speed); enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); From patchwork Sat Mar 2 04:00:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 209177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp302916dyc; Fri, 1 Mar 2024 20:02:47 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVpBfOSzUFLTNnxec3+lvDaJ/9MpWlUeTbon0tSGVBPd3/h0MgpoiNt/GBk40ujGaMSCZsISXgsJuDlPNpy6QpldvLhlQ== X-Google-Smtp-Source: AGHT+IH6sd0HZzn68r08FmsHqyddr4AJ0neqxwuyFkAGDtpFERf3ez2mySPTR8N1pzJX7KyjKBfZ X-Received: by 2002:a05:6e02:1aaf:b0:365:117c:c957 with SMTP id l15-20020a056e021aaf00b00365117cc957mr3961715ilv.16.1709352167224; Fri, 01 Mar 2024 20:02:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709352167; cv=pass; d=google.com; s=arc-20160816; b=xbiEpAtT2GG1+5KhYZqGf5bJNavrgZd6na42rJPml2X+So/ws8jodDUOeJudFc3ble +Yx+PxXF2Ji/9b3XR/EsWehFk94MhcwZaLj6Rv+dXYC5z8mI4uepaU+vgZwVGQNc5orX xBtPj5E4PZmc3wiDylCQ2zpi/lP8CnEwI3NLmryDYVzrKcGgDvhEGXUl9BHE/4u4AD85 y9NBHVnQdnw0AfhLNSgtXqkfOwlTT/j5Z93qO0hSHOtVlQq9Wlk4JMRAAAMpuY2Yvl93 Mk3/Fx9L38wjyr5kdSivb3tUyvHI/ys5Is3qQs35sKHJ+M3ATVPjrlKvW4QcBH298KHe gBag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=UgXdaho2g1wAGEkx5lrs8R4Q61U+T3fkNPkjg6bs7M4=; fh=mLeyOiXXxJHJYs8dxImKbmNctx3gBpnhH0V2tKEUcOs=; b=BsjXwKYFr0Bv7CpFQgG/XTNM/28bariMg39bqqy0L9FIeEHp383qtXCK0C59k2QJO5 ho8Pw6fzdQ9Mm2cjhhJictPgbgFO0GuvgjvvQflTBuK1wJ4lZhdPd+bIXe4vO6ojqQ/7 9wRY3GGkhDgFCCj0vdTDdUm54WlTQWhMPC+DoWfvf0W0cXwvwOT3m8QTRZfJDuGZ7VN0 41vdWd2GzrwQLHFnpIgU98zKd8kHdH3P9xo+jfKyJ3h98hLMu2EuUC+u26cBY3J+bUbh eis8xaeJv68Fc15qAkvNWwDnZoqd0btxa3UjlwYbWPptuibLvDoA1Q9vdo+QQxSi0uda rWYw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=f1kXHz4N; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-89329-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-89329-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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a=ed25519-sha256; t=1709352004; l=5942; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=QUJ+uyOOht+Lnc6Y4adY/bs8ZcDhOvU50AmkDpCQsfQ=; b=hW7ITjW6G5LvtaqTuJ34NeeUYCWzHiMfeFprZaObeexidG+hGigmIx//ij8DAZ0EZVd7NgK1+ Sb7gRxYjNI7B+iIK3DWlCVI0HKfrNZ3wGYeUrRERqZuR99URx8KejEH X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ksJOpkJ0QGO-ZZOAlhlqsbEcauEdec9Q X-Proofpoint-ORIG-GUID: ksJOpkJ0QGO-ZZOAlhlqsbEcauEdec9Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-01_24,2024-03-01_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 clxscore=1015 spamscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403020031 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792385657959545082 X-GMAIL-MSGID: 1792385657959545082 QCOM Resource Power Manager-hardened (RPMh) is a hardware block which maintains hardware state of a regulator by performing max aggregation of the requests made by all of the clients. PCIe controller can operate on different RPMh performance state of power domain based on the speed of the link. And this performance state varies from target to target, like some controllers support GEN3 in NOM (Nominal) voltage corner, while some other supports GEN3 in low SVS (static voltage scaling). The SoC can be more power efficient if we scale the performance state based on the aggregate PCIe link bandwidth. Add Operating Performance Points (OPP) support to vote for RPMh state based on the aggregate link bandwidth. OPP can handle ICC bw voting also, so move ICC bw voting through OPP framework if OPP entries are present. Different link configurations may share the same aggregate bandwidth, e.g., a 2.5 GT/s x2 link and a 5.0 GT/s x1 link have the same bandwidth and share the same OPP entry. As we are moving ICC voting as part of OPP, don't initialize ICC if OPP is supported. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 81 +++++++++++++++++++++++++++------- 1 file changed, 66 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a0266bfe71f1..2ec14bfafcfc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -244,6 +245,7 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; + bool opp_supported; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -1405,15 +1407,13 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) return 0; } -static void qcom_pcie_icc_update(struct qcom_pcie *pcie) +static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; - u32 offset, status; + u32 offset, status, freq; + struct dev_pm_opp *opp; int speed, width; - int ret; - - if (!pcie->icc_mem) - return; + int ret, mbps; offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); @@ -1425,11 +1425,30 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); - if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", - ret); + if (pcie->opp_supported) { + mbps = pcie_link_speed_to_mbps(pcie_link_speed[speed]); + if (mbps < 0) + return; + + freq = mbps * 1000; + opp = dev_pm_opp_find_freq_exact(pci->dev, freq * width, true); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(pci->dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set opp: freq %ld ret %d\n", + dev_pm_opp_get_freq(opp), ret); + dev_pm_opp_put(opp); + } + } else { + ret = icc_set_bw(pcie->icc_mem, 0, + width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); + if (ret) { + dev_err(pci->dev, + "failed to set interconnect bandwidth for pcie-mem: %d\n", ret); + } } + + return; } static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) @@ -1472,8 +1491,10 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; + unsigned long max_freq = INT_MAX; struct device *dev = &pdev->dev; struct qcom_pcie *pcie; + struct dev_pm_opp *opp; struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; @@ -1540,9 +1561,36 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - ret = qcom_pcie_icc_init(pcie); - if (ret) + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) { + dev_err_probe(dev, ret, "Failed to add OPP table\n"); goto err_pm_runtime_put; + } + + /* + * Use highest OPP here if the OPP table is present. At the end of + * the probe(), OPP will be updated using qcom_pcie_icc_opp_update(). + */ + if (ret != -ENODEV) { + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(dev, opp); + if (ret) + dev_err_probe(pci->dev, ret, + "Failed to set opp: freq %ld\n", + dev_pm_opp_get_freq(opp)); + dev_pm_opp_put(opp); + } + pcie->opp_supported = true; + } + + /* Skip ICC init if OPP is supported as ICC bw is handled by OPP */ + if (!pcie->opp_supported) { + ret = qcom_pcie_icc_init(pcie); + if (ret) + goto err_pm_runtime_put; + } ret = pcie->cfg->ops->get_resources(pcie); if (ret) @@ -1562,7 +1610,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) qcom_pcie_init_debugfs(pcie); @@ -1621,10 +1669,13 @@ static int qcom_pcie_suspend_noirq(struct device *dev) qcom_pcie_host_init(&pcie->pci->pp); pcie->suspended = false; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); return ret; } + if (pcie->opp_supported) + dev_pm_opp_set_opp(pcie->pci->dev, NULL); + return 0; } @@ -1647,7 +1698,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) pcie->suspended = false; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); return 0; }