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Fri, 01 Mar 2024 17:45:40 -0800 (PST) From: Charlie Jenkins Date: Fri, 01 Mar 2024 17:45:32 -0800 Subject: [PATCH v6 1/4] riscv: lib: Introduce has_fast_unaligned_access function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-disable_misaligned_probe_config-v6-1-612ebd69f430@rivosinc.com> References: <20240301-disable_misaligned_probe_config-v6-0-612ebd69f430@rivosinc.com> In-Reply-To: <20240301-disable_misaligned_probe_config-v6-0-612ebd69f430@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Eric Biggers , Elliot Berman , Charles Lohr , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709343937; l=3372; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=FzR0GpkIwoZRYWxFyEryVlUwRX7agq76vtFdOU7VZ+M=; b=MTe+OzVOyEChCkgWAjVjTKJ1KGldjB3X8XOlTPihrud5sPuCHjpapts64+9B/jDdMiVP4tKOR 9wf0fy4i0KRBUiNT07bmPtNKyvrHOeVYeniuqlbOHRIcZCWcU6fLy9n X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792377076691303487 X-GMAIL-MSGID: 1792377076691303487 Create has_fast_unaligned_access to avoid needing to explicitly check the fast_misaligned_access_speed_key static key. Signed-off-by: Charlie Jenkins Reviewed-by: Evan Green --- arch/riscv/include/asm/cpufeature.h | 11 ++++++++--- arch/riscv/kernel/cpufeature.c | 6 +++--- arch/riscv/lib/csum.c | 7 ++----- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 5a626ed2c47a..466e1f591919 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright 2022-2023 Rivos, Inc + * Copyright 2022-2024 Rivos, Inc */ #ifndef _ASM_CPUFEATURE_H @@ -53,6 +53,13 @@ static inline bool check_unaligned_access_emulated(int cpu) static inline void unaligned_emulation_finish(void) {} #endif +DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); + +static __always_inline bool has_fast_unaligned_accesses(void) +{ + return static_branch_likely(&fast_unaligned_access_speed_key); +} + unsigned long riscv_get_elf_hwcap(void); struct riscv_isa_ext_data { @@ -135,6 +142,4 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } -DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); - #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..7878cddccc0d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -810,14 +810,14 @@ static void check_unaligned_access_nonboot_cpu(void *param) check_unaligned_access(pages[cpu]); } -DEFINE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); +DEFINE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); static void modify_unaligned_access_branches(cpumask_t *mask, int weight) { if (cpumask_weight(mask) == weight) - static_branch_enable_cpuslocked(&fast_misaligned_access_speed_key); + static_branch_enable_cpuslocked(&fast_unaligned_access_speed_key); else - static_branch_disable_cpuslocked(&fast_misaligned_access_speed_key); + static_branch_disable_cpuslocked(&fast_unaligned_access_speed_key); } static void set_unaligned_access_static_branches_except_cpu(int cpu) diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index af3df5274ccb..7178e0acfa22 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -3,7 +3,7 @@ * Checksum library * * Influenced by arch/arm64/lib/csum.c - * Copyright (C) 2023 Rivos Inc. + * Copyright (C) 2023-2024 Rivos Inc. */ #include #include @@ -318,10 +318,7 @@ unsigned int do_csum(const unsigned char *buff, int len) * branches. The largest chunk of overlap was delegated into the * do_csum_common function. */ - if (static_branch_likely(&fast_misaligned_access_speed_key)) - return do_csum_no_alignment(buff, len); - - if (((unsigned long)buff & OFFSET_MASK) == 0) + if (has_fast_unaligned_accesses() || (((unsigned long)buff & OFFSET_MASK) == 0)) return do_csum_no_alignment(buff, len); return do_csum_with_alignment(buff, len); From patchwork Sat Mar 2 01:45:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 209167 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp263672dyc; Fri, 1 Mar 2024 17:46:33 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXYpmur8gu7L2NL2fWHHf9b6h6yMhcp1dqyGTgc9GZQ88NNICc2FvRKETuXGeQCLOMB0AqaQkVGsG7RDL8AhhnUcueZag== X-Google-Smtp-Source: AGHT+IEHmvRkyKueYE20fcGSdQ26hpnV4/9Az8PT82egdj8nnbejhuBxYUis4c3qxsSB0WQZBR2+ X-Received: by 2002:a05:6402:1d93:b0:566:8495:d4ef with SMTP id dk19-20020a0564021d9300b005668495d4efmr2066986edb.32.1709343993343; Fri, 01 Mar 2024 17:46:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709343993; cv=pass; d=google.com; s=arc-20160816; b=egipRbDVHirndAqifVn9c5fiT9dZ5VaNl2t4YSe3b9hPP6tZaxqOE3EtlfzpIbfJJR 5hNAeqmDvmbmtWAOfehVgwJOh0Az0hqJH6fbFKxxdLKlwFrjLn+5Pr4kzEqGEP9o4Ekj CEAnoH2vlT6EdZyhFpFezLxsL8HIc9VXAes5WtZo2UYNdQl+AHpk/iKX//82wfbL9/v5 cuvk0c6udQ/I0m7wSrw9Vypy+NRMEExSsXTGPAXVieJPmB3cw7ckzz704J9ybVPwh/rw xOq7gSrRsLDEo6CPnzIvIhiz4DzHlqwwv79shGu+kRJg/ttz6LITMpwnXN0gedkbW/w8 02nw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=HtnskPkRhYiZU7za9ryep8TQ6a4uPdl3XXtWJSoiADM=; fh=tJFEQlYn2vYgq6GDzROGzCUsd+s1MQm28RMZ1tpcL3Q=; b=ixsKWBWVTWgz8ru8r33W867nfTaFxb42G0/x8ooiq91Eqt+2W/99oJjolg/wGyjN7A /Yr36Jtxv87M3meFbkjZyZ+JkMsttHejaBqAAvkXalIwkeYI4PjwA5+uDyEOkFQ/QAef yoBtbtlzkIGKXEKKB+f8ojwCxn3DIO6NXMyB5SaxqVFj7wNIsV/pmP3meQIXT5eNmOep G7sobZ9J/pJ1k6LZIhsNewp7+HWyD5AGXYM3j7Rr6GO9LVghEUolky/wgAsSbIEG4P2L +dNGhB05wgjkDSCNHgB8TC0UXOtlFZcxYAT+HOrN7lKSCWLVm1o/JdNQz4U49qqXBEBT HU0g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=RFCjloGD; arc=pass (i=1 spf=pass spfdomain=rivosinc.com dkim=pass dkdomain=rivosinc-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-89297-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-89297-ouuuleilei=gmail.com@vger.kernel.org" Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 01 Mar 2024 17:45:42 -0800 (PST) From: Charlie Jenkins Date: Fri, 01 Mar 2024 17:45:33 -0800 Subject: [PATCH v6 2/4] riscv: Only check online cpus for emulated accesses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-disable_misaligned_probe_config-v6-2-612ebd69f430@rivosinc.com> References: <20240301-disable_misaligned_probe_config-v6-0-612ebd69f430@rivosinc.com> In-Reply-To: <20240301-disable_misaligned_probe_config-v6-0-612ebd69f430@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Eric Biggers , Elliot Berman , Charles Lohr , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709343937; l=929; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=UUdT4DeT5/dOQZ05jhj8UeaRSkQffyRcQJbuhlDryrg=; b=8PmXJ6dPykReAEr2oVdcdTdjbyNW1n+hkJwqkARm+ne05UxS/l+kJ7+aXvipYzLBMxOTOE/j/ 2410PfeOQLFDLfFBbI/C09RxasD89zBRF5GyE4tEEIgI5PD+ang1sQa X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792377087115927932 X-GMAIL-MSGID: 1792377087115927932 The unaligned access checker only sets valid values for online cpus. Check for these values on online cpus rather than on present cpus. Signed-off-by: Charlie Jenkins Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwprobe") --- arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 8ded225e8c5b..c2ed4e689bf9 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -632,7 +632,7 @@ void unaligned_emulation_finish(void) * accesses emulated since tasks requesting such control can run on any * CPU. */ - for_each_present_cpu(cpu) { + for_each_online_cpu(cpu) { if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_EMULATED) { return; From patchwork Sat Mar 2 01:45:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 209168 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp263709dyc; Fri, 1 Mar 2024 17:46:43 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWmN8DobxhHIpiEQNYR+AP+wMErELCXUrFmMb5xhDzNIPu7JWdum7SF+9wADcPfz4L0tOe18rwLhY2vzKiZwVKE3+U7RA== X-Google-Smtp-Source: AGHT+IFmt8tuaxLOnk5hGSZfJZzKEbs3Wvrf4BncugbqlUzKHRTay+QCJ0KdJPf49xwIl3jepOpv X-Received: by 2002:a0c:cc0b:0:b0:68f:2b1c:5516 with SMTP id r11-20020a0ccc0b000000b0068f2b1c5516mr3375112qvk.32.1709344003065; Fri, 01 Mar 2024 17:46:43 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709344003; cv=pass; d=google.com; s=arc-20160816; b=WTBMmcSOE9C6We8ATFIawiXtb2b6Ltz3YgIiiJ9EndqavDmtXHRVX6t8x7zmNuvXD9 QME6qJK5DLAh/Kb45C1/UM+qplSvZD+T4Ok854py+keMLpxqJBhCgNqlQIjQbEOxAw4X nxyVuUeQKJrDLrWp///AptaoP+Okoj22CQUXPqfv0kaHg0ziqmUA53Rq8RtN1cp7I/3I 2ReconYh4cS+zggqlq382hqTGtB0CC3KeqCgldecR1QCzcKMtjx3pAc9N8C2RRkSoO7b Col9vKim/5dajEwS2PLVwNdOnuUBVpNCjD2ppsoKmj1/1tBUNdZc6WdftfizyQ9wmXER RUnA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=r3Qfvs3PS/SqaY35b4e9kYVL30tzyoJAgDQ9SsWZHOI=; fh=AMQvelhApQs1aD0yMeedKVW1GeoPNbhg0djwLwrQ3UM=; b=jwz3AxOqFDHKQgZ/1SBdytndO/N0y+g4C3khfMmSrZ55g9SRbRh/Cnpc4Pi9mov6Jg VxL/JnnVpocIuFwObCIx98dcCBgGPUgYEwhthl/Z4imUIKHWA8yHkm0IXNM76irWxo0I 8tWQctau2MO4UP8ZXSRF6y5Ldt4FoLT+gLTkwqpe9iZkCiDLYZLR8bZ/vPOTg8QkYAHG 0/JZQ8OMO/K8jPnHX40bDTIL8bjQEzDhjAN9s34+TLEeySYFXLdJhR10X4ysj9HHNJi9 ZAaIWJMfoo3cEcCRyp8uFSf1SPDuZrHoaSoZfbLgdD2rRWNpLkSuHwkPc9FlNkXwd19W X3Iw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=hejeb6Bu; arc=pass (i=1 spf=pass spfdomain=rivosinc.com dkim=pass dkdomain=rivosinc-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-89298-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-89298-ouuuleilei=gmail.com@vger.kernel.org" Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 01 Mar 2024 17:45:43 -0800 (PST) From: Charlie Jenkins Date: Fri, 01 Mar 2024 17:45:34 -0800 Subject: [PATCH v6 3/4] riscv: Decouple emulated unaligned accesses from access speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240301-disable_misaligned_probe_config-v6-3-612ebd69f430@rivosinc.com> References: <20240301-disable_misaligned_probe_config-v6-0-612ebd69f430@rivosinc.com> In-Reply-To: <20240301-disable_misaligned_probe_config-v6-0-612ebd69f430@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Eric Biggers , Elliot Berman , Charles Lohr , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1709343937; l=4205; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=YiWDyhZlyEbMfbqz0FsXl9yfSIL66FQp7h5UIvYeHJo=; b=M1VlqbLcYcq1VPmyWChr6/UcHm055g1J1jbZi0Ing9Lqe/dnK3npq+QdKEdNeIF7NX4qlMNrp wXdgqrbwSSlALqlnlscL6GXP8VeQb/WoJS8UcYhTBJnToIP2yy3U6iH X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792377097270073319 X-GMAIL-MSGID: 1792377097270073319 Detecting if a system traps into the kernel on an unaligned access can be performed separately from checking the speed of unaligned accesses. This decoupling will make it possible to selectively enable or disable each of these checks as is done in the following patch. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 2 +- arch/riscv/kernel/cpufeature.c | 25 +++++++++++++++++++++---- arch/riscv/kernel/traps_misaligned.c | 20 +++++++------------- 3 files changed, 29 insertions(+), 18 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 466e1f591919..6fec91845aa0 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -37,7 +37,7 @@ void riscv_user_isa_enable(void); #ifdef CONFIG_RISCV_MISALIGNED bool unaligned_ctl_available(void); -bool check_unaligned_access_emulated(int cpu); +bool check_unaligned_access_emulated_all_cpus(void); void unaligned_emulation_finish(void); #else static inline bool unaligned_ctl_available(void) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 7878cddccc0d..abb3a2f53106 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -719,7 +719,8 @@ static int check_unaligned_access(void *param) void *src; long speed = RISCV_HWPROBE_MISALIGNED_SLOW; - if (check_unaligned_access_emulated(cpu)) + if (IS_ENABLED(CONFIG_RISCV_MISALIGNED) && + per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN) return 0; /* Make an unaligned destination buffer. */ @@ -896,8 +897,8 @@ static int riscv_offline_cpu(unsigned int cpu) return 0; } -/* Measure unaligned access on all CPUs present at boot in parallel. */ -static int check_unaligned_access_all_cpus(void) +/* Measure unaligned access speed on all CPUs present at boot in parallel. */ +static int check_unaligned_access_speed_all_cpus(void) { unsigned int cpu; unsigned int cpu_count = num_possible_cpus(); @@ -935,7 +936,6 @@ static int check_unaligned_access_all_cpus(void) riscv_online_cpu, riscv_offline_cpu); out: - unaligned_emulation_finish(); for_each_cpu(cpu, cpu_online_mask) { if (bufs[cpu]) __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); @@ -945,6 +945,23 @@ static int check_unaligned_access_all_cpus(void) return 0; } +#ifdef CONFIG_RISCV_MISALIGNED +static int check_unaligned_access_all_cpus(void) +{ + bool all_cpus_emulated = check_unaligned_access_emulated_all_cpus(); + + if (!all_cpus_emulated) + return check_unaligned_access_speed_all_cpus(); + + return 0; +} +#else +static int check_unaligned_access_all_cpus(void) +{ + return check_unaligned_access_speed_all_cpus(); +} +#endif + arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index c2ed4e689bf9..1e3cec3f5d93 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -596,7 +596,7 @@ int handle_misaligned_store(struct pt_regs *regs) return 0; } -bool check_unaligned_access_emulated(int cpu) +static bool check_unaligned_access_emulated(int cpu) { long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); unsigned long tmp_var, tmp_val; @@ -623,22 +623,16 @@ bool check_unaligned_access_emulated(int cpu) return misaligned_emu_detected; } -void unaligned_emulation_finish(void) +bool check_unaligned_access_emulated_all_cpus(void) { int cpu; - /* - * We can only support PR_UNALIGN controls if all CPUs have misaligned - * accesses emulated since tasks requesting such control can run on any - * CPU. - */ - for_each_online_cpu(cpu) { - if (per_cpu(misaligned_access_speed, cpu) != - RISCV_HWPROBE_MISALIGNED_EMULATED) { - return; - } - } + for_each_online_cpu(cpu) + if (check_unaligned_access_emulated(cpu)) + return false; + unaligned_ctl = true; + return true; } bool unaligned_ctl_available(void)