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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id t14-20020ac86a0e000000b0042e6b901ebesm1885433qtr.40.2024.03.01.09.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 09:33:50 -0800 (PST) From: Trevor Gamblin To: linux-pwm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de, michael.hennerich@analog.com, nuno.sa@analog.com, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, tgamblin@baylibre.com, dlechner@baylibre.com, Drew Fustini , Krzysztof Kozlowski Subject: [PATCH 1/2 v4] dt-bindings: pwm: Add AXI PWM generator Date: Fri, 1 Mar 2024 12:33:41 -0500 Message-ID: <20240301173343.1086332-2-tgamblin@baylibre.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301173343.1086332-1-tgamblin@baylibre.com> References: <20240301173343.1086332-1-tgamblin@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792346245955817766 X-GMAIL-MSGID: 1792346245955817766 From: Drew Fustini Add Analog Devices AXI PWM generator. Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen Signed-off-by: Drew Fustini Reviewed-by: Krzysztof Kozlowski Co-developed-by: Trevor Gamblin Signed-off-by: Trevor Gamblin --- v4 changes: None (rebased, added maintainer's previous Reviewed-by) v3 changes: None (rebased, added maintainer's previous Reviewed-by) v2 changes: * Address feedback for driver and device tree in v1: * Relocate "unevaluatedProperties" in device tree binding * Remove redundant "bindings for" in description --- .../bindings/pwm/adi,axi-pwmgen.yaml | 48 +++++++++++++++++++ MAINTAINERS | 8 ++++ 2 files changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml new file mode 100644 index 000000000000..63461920a362 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AXI PWM generator + +maintainers: + - Michael Hennerich + - Nuno Sá + +description: + The Analog Devices AXI PWM generator can generate PWM signals + with variable pulse width and period. + + https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: adi,axi-pwmgen-1.00.a + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + clocks: + maxItems: 1 + +required: + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + pwm@44b00000 { + compatible = "adi,axi-pwmgen-1.00.a"; + reg = <0x44b00000 0x1000>; + clocks = <&spi_clk>; + #pwm-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 8d1052fa6a69..8a4ed5545680 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3431,6 +3431,14 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/spi/adi,axi-spi-engine.yaml F: drivers/spi/spi-axi-spi-engine.c +AXI PWM GENERATOR +M: Michael Hennerich +M: Nuno Sá +L: linux-pwm@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml + AXXIA I2C CONTROLLER M: Krzysztof Adamski L: linux-i2c@vger.kernel.org From patchwork Fri Mar 1 17:33:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trevor Gamblin X-Patchwork-Id: 208968 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:fa17:b0:10a:f01:a869 with SMTP id ju23csp35281dyc; Fri, 1 Mar 2024 09:36:36 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXEuA8VfPyJAN++b0Piogxb13SxC44bi65LCUyW+HFUsB5HIH+7aGn76KcU32TG17yRxVkQZhh5s4y3LHbRXCq9bGuQvA== X-Google-Smtp-Source: AGHT+IHg6ia9jSQp1q0ucsFaa0IPX7SOK/9su4DFPt3GR/PFfvcq2QJHFZdk3RBi6XKoHFnTbJw/ X-Received: by 2002:a05:6358:3121:b0:17b:b541:2ee with SMTP id c33-20020a056358312100b0017bb54102eemr2683998rwe.15.1709314596385; Fri, 01 Mar 2024 09:36:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709314596; cv=pass; d=google.com; s=arc-20160816; b=HaDF/CKP20CRsw8XVAJuztT1+nlz3W9/8FgTUUARKF3W3qSoncB5Hsc2bPyHNXRZZP OoBTPyV9K1bLQBouLthsrmmXOC233poLs2iUBcFnp32dctrIy8hDC/jSdDLYOZ8wgfQP BlwlMaGp77eLND0UWHvPY30IBppZGDBhHF5cLPPpyGZfEA6Cjy8yPNTwuO4Yie+gegB8 OaqamScG/QWuqElhQcuPLyp6lZP8i5pwcWPBYreGKNEz+IQsm7dowHVbZERo0ogHxWur SiyVjW3myDVZMDAX2oSo32MW2CeOy/AWFDW2anvW9wkh4pvG6Wvai1Z2o1y6FuRLw4uL BNzw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=zOVHcyIQafglLiWlY4Z/94Fwm6mG3X7gH2tvIaZfG2I=; fh=0VlGkOTnd1iE9rJRGNWqcm9+LPHELBmgLyHh87L6WzA=; b=bE/+GPuynEHh8juqvOO7LFz1vGdJXCb0zhCMm4jopSEvCqMrIAvm9/uqz/AnhCS/qO tWKy/3FDKQOoCCtlueq1CSpzElP26LJy/pb2cz/r32FiaP+TWYue8RtOJFqsRMFmAsEI nlMa353g7W0USNYp58g7gzrrpXkAeM2P1YVrAOxdEYOLg+Oq6ZdTMgpE1O7JscdcOhK1 TjuWpVP0nwbEIA6L6JgfUVIzHr/PVBCxbinGLLKKwy6EmLq7v/ndGmfGZ4U+XN3G9Wk7 c14fZtGoh4Yc8K60yUpEJMrAuPtbsYd1ap9dC7HDx8uG1SllqzuadPGJgIuHoVcrS6vt /xxA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=1Wfw3k+p; arc=pass (i=1 spf=pass spfdomain=baylibre.com dkim=pass dkdomain=baylibre-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-88844-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-88844-ouuuleilei=gmail.com@vger.kernel.org" Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id t14-20020ac86a0e000000b0042e6b901ebesm1885433qtr.40.2024.03.01.09.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 09:33:52 -0800 (PST) From: Trevor Gamblin To: linux-pwm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de, michael.hennerich@analog.com, nuno.sa@analog.com, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, tgamblin@baylibre.com, dlechner@baylibre.com, Drew Fustini , Sergiu Cuciurean Subject: [PATCH 2/2 v4] pwm: Add driver for AXI PWM generator Date: Fri, 1 Mar 2024 12:33:42 -0500 Message-ID: <20240301173343.1086332-3-tgamblin@baylibre.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240301173343.1086332-1-tgamblin@baylibre.com> References: <20240301173343.1086332-1-tgamblin@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792346262315584563 X-GMAIL-MSGID: 1792346262315584563 From: Drew Fustini Add support for the Analog Devices AXI PWM Generator. This device is an FPGA-implemented peripheral used as PWM signal generator and can be interfaced with AXI4. The register map of this peripheral makes it possible to configure the period and duty cycle of the output signal. Link: https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen Co-developed-by: Sergiu Cuciurean Signed-off-by: Sergiu Cuciurean Co-developed-by: David Lechner Signed-off-by: David Lechner Signed-off-by: Drew Fustini Acked-by: Nuno Sa Co-developed-by: Trevor Gamblin Signed-off-by: Trevor Gamblin --- v4 changes: * Address feedback for driver in v3: * Update to use devm_pwmchip_alloc() function * Simplify use of dev symbol in axi_pwmgen_probe * Remove unnecessary axi_pwmgen_from_chip function and use pwmchip_get_drvdata directly v3 changes: * Address feedback for driver in v2: * Remove unnecessary blank line in axi_pwmgen_apply * Use macros already defined in for version checking v2 changes: * Address feedback for driver and device tree in v1: * Use more reasonable Kconfig approach * Use common prefixes for all functions * Rename axi_pwmgen struct to axi_pwmgen_ddata * Change use of "pwm" to "ddata" * Set and check state->polarity * Multiply safely with mul_u64_u64_div_u64() * Improve handling of max and zero periods * Error if clk_rate_hz > NSEC_PER_SEC * Add "Limitations" section at top of pwm-axi-pwmgen.c * Don't disable outputs by default * Remove unnecessary macros for period, duty, offset * Fix axi_pwmgen_ddata alignment * Don't artificially limit npwm to four * Use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put() * Cache clk rate in axi_pwmgen_ddata * Don't assign pwm->chip.base, do assign pwm->chip.atomic * Remove redundant calls to clk_get_rate * Test contents of AXI_PWMGEN_REG_CORE_MAGIC instead of arbitrary AXI_PWMGEN_TEST_DATA in AXI_PWMGEN_REG_SCRATCHPAD * Remove redundant clk struct from axi_pwmgen_ddata * Add self as module author * Add major version check for IP core --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 13 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-axi-pwmgen.c | 244 +++++++++++++++++++++++++++++++++++ 4 files changed, 259 insertions(+) create mode 100644 drivers/pwm/pwm-axi-pwmgen.c diff --git a/MAINTAINERS b/MAINTAINERS index 8a4ed5545680..2baa7a0a1c8c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3438,6 +3438,7 @@ L: linux-pwm@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +F: drivers/pwm/pwm-axi-pwmgen.c AXXIA I2C CONTROLLER M: Krzysztof Adamski diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 4b956d661755..d44b0e86adee 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -98,6 +98,19 @@ config PWM_ATMEL_TCB To compile this driver as a module, choose M here: the module will be called pwm-atmel-tcb. +config PWM_AXI_PWMGEN + tristate "Analog Devices AXI PWM generator" + depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || COMPILE_TEST + select REGMAP_MMIO + help + This enables support for the Analog Devices AXI PWM generator. + + This is a configurable PWM generator with variable pulse width and + period. + + To compile this driver as a module, choose M here: the module will be + called pwm-axi-pwmgen. + config PWM_BCM_IPROC tristate "iProc PWM support" depends on ARCH_BCM_IPROC || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c5ec9e168ee7..8322089954e9 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PWM_APPLE) += pwm-apple.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o +obj-$(CONFIG_PWM_AXI_PWMGEN) += pwm-axi-pwmgen.o obj-$(CONFIG_PWM_BCM_IPROC) += pwm-bcm-iproc.o obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-kona.o obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c new file mode 100644 index 000000000000..0c8f7f893a21 --- /dev/null +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AXI PWM generator + * + * Copyright 2024 Analog Devices Inc. + * Copyright 2024 Baylibre SAS + * + * Limitations: + * - The writes to registers for period and duty are shadowed until + * LOAD_CONFIG is written to AXI_PWMGEN_REG_CONFIG at the end of the + * current period. + * - Writing LOAD_CONFIG also has the effect of re-synchronizing all + * enabled channels, which could cause glitching on other channels. It + * is therefore expected that channels are assigned harmonic periods + * and all have a single user coordinating this. + * - Supports normal polarity. Does not support changing polarity. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AXI_PWMGEN_REG_CORE_VERSION 0x00 +#define AXI_PWMGEN_REG_ID 0x04 +#define AXI_PWMGEN_REG_SCRATCHPAD 0x08 +#define AXI_PWMGEN_REG_CORE_MAGIC 0x0C +#define AXI_PWMGEN_REG_CONFIG 0x10 +#define AXI_PWMGEN_REG_NPWM 0x14 +#define AXI_PWMGEN_CHX_PERIOD(ch) (0x40 + (12 * (ch))) +#define AXI_PWMGEN_CHX_DUTY(ch) (0x44 + (12 * (ch))) +#define AXI_PWMGEN_CHX_OFFSET(ch) (0x48 + (12 * (ch))) +#define AXI_PWMGEN_REG_CORE_MAGIC_VAL 0x601A3471 /* Identification number to test during setup */ +#define AXI_PWMGEN_LOAD_CONFIG BIT(1) +#define AXI_PWMGEN_RESET BIT(0) + +struct axi_pwmgen_ddata { + struct regmap *regmap; + unsigned long clk_rate_hz; +}; + +static const struct regmap_config axi_pwmgen_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, +}; + +static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); + unsigned int ch = pwm->hwpwm; + struct regmap *regmap = ddata->regmap; + u64 period_cnt, duty_cnt; + int ret; + + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + + if (state->enabled) { + period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC); + if (period_cnt > UINT_MAX) + period_cnt = UINT_MAX; + + if (period_cnt == 0) + return -EINVAL; + + ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt); + if (ret) + return ret; + + duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC); + if (duty_cnt > UINT_MAX) + duty_cnt = UINT_MAX; + + ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt); + if (ret) + return ret; + } else { + ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0); + if (ret) + return ret; + + ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0); + if (ret) + return ret; + } + + return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG); +} + +static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); + struct regmap *regmap = ddata->regmap; + unsigned int ch = pwm->hwpwm; + u32 cnt; + int ret; + + ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt); + if (ret) + return ret; + + state->enabled = cnt != 0; + + state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); + + ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt); + if (ret) + return ret; + + state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); + + state->polarity = PWM_POLARITY_NORMAL; + + return 0; +} + +static const struct pwm_ops axi_pwmgen_pwm_ops = { + .apply = axi_pwmgen_apply, + .get_state = axi_pwmgen_get_state, +}; + +static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev) +{ + int ret; + u32 val; + + ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_MAGIC, &val); + if (ret) + return ret; + + if (val != AXI_PWMGEN_REG_CORE_MAGIC_VAL) + return dev_err_probe(dev, -ENODEV, + "failed to read expected value from register: got %08x, expected %08x\n", + val, + AXI_PWMGEN_REG_CORE_MAGIC_VAL); + + ret = regmap_read(regmap, AXI_PWMGEN_REG_CORE_VERSION, &val); + if (ret) + return ret; + + if (ADI_AXI_PCORE_VER_MAJOR(val) != 1) { + return dev_err_probe(dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n", + ADI_AXI_PCORE_VER_MAJOR(val), + ADI_AXI_PCORE_VER_MINOR(val), + ADI_AXI_PCORE_VER_PATCH(val)); + } + + /* Enable the core */ + ret = regmap_update_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_RESET, 0); + if (ret) + return ret; + + ret = regmap_read(regmap, AXI_PWMGEN_REG_NPWM, &val); + if (ret) + return ret; + + /* Return the number of PWMs */ + return val; +} + +static void axi_pwmgen_clk_rate_exclusive_put(void *data) +{ + clk_rate_exclusive_put(data); +} + +static int axi_pwmgen_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct pwm_chip *chip; + struct axi_pwmgen_ddata *ddata; + struct clk *clk; + void __iomem *io_base; + int ret; + + io_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(io_base)) + return PTR_ERR(io_base); + + regmap = devm_regmap_init_mmio(dev, io_base, &axi_pwmgen_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to init register map\n"); + + ret = axi_pwmgen_setup(regmap, dev); + if (ret < 0) + return ret; + + chip = devm_pwmchip_alloc(dev, ret, sizeof(*ddata)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + ddata = pwmchip_get_drvdata(chip); + ddata->regmap = regmap; + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n"); + + ret = clk_rate_exclusive_get(clk); + if (ret) + return dev_err_probe(dev, ret, "failed to get exclusive rate\n"); + + ret = devm_add_action_or_reset(dev, axi_pwmgen_clk_rate_exclusive_put, clk); + if (ret) + return ret; + + ddata->clk_rate_hz = clk_get_rate(clk); + if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC) + return dev_err_probe(dev, -EINVAL, + "Invalid clock rate: %lu\n", ddata->clk_rate_hz); + + chip->ops = &axi_pwmgen_pwm_ops; + chip->atomic = true; + + return devm_pwmchip_add(dev, chip); +} + +static const struct of_device_id axi_pwmgen_ids[] = { + { .compatible = "adi,axi-pwmgen-1.00.a" }, + { } +}; +MODULE_DEVICE_TABLE(of, axi_pwmgen_ids); + +static struct platform_driver axi_pwmgen_driver = { + .driver = { + .name = "axi-pwmgen", + .of_match_table = axi_pwmgen_ids, + }, + .probe = axi_pwmgen_probe, +}; +module_platform_driver(axi_pwmgen_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Sergiu Cuciurean "); +MODULE_AUTHOR("Trevor Gamblin "); +MODULE_DESCRIPTION("Driver for the Analog Devices AXI PWM generator");