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AJvYcCVnOEx+JjWi7Y/Etm+UdISj9ZVtcpGbCqJhVniFiTxg6Zr5UDoNc92tzttd7rUDexWQTZ93ecS11LVNFbXKAn9+ahizK+e5Mul/IjKuVbwoRPtSemTm+IJasERyia9zFXcwIB9yhiGXpA== X-Gm-Message-State: AOJu0YwJlxeOmF4UB1wg/SBOnezfHV/1uTC37OJ1PTc9KLx3ic1yozR6 2HisNZWNIplHBEabS+KGy2LRlfV9X1rOpaHhTqOP3tdiybohmb0ks4b8qUNC5yaGpg== X-Received: by 2002:a05:6e02:1d83:b0:365:b9c8:4436 with SMTP id h3-20020a056e021d8300b00365b9c84436mr183974ila.10.1709249764757; Thu, 29 Feb 2024 15:36:04 -0800 (PST) Received: from aford-System-Version.lan ([2601:447:d002:5be:c0ab:242c:2712:ad44]) by smtp.gmail.com with ESMTPSA id j5-20020a056e020ee500b0036576880ffcsm584260ilk.85.2024.02.29.15.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Feb 2024 15:36:04 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: aford@beaconembedded.com, Adam Ford , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64: dts: imx8mp-beacon-kit: Move sai3 to Audio_PLL1 Date: Thu, 29 Feb 2024 17:35:54 -0600 Message-ID: <20240229233556.116944-1-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792278314777178537 X-GMAIL-MSGID: 1792278314777178537 The Beacon board has an LVDS display that cannot get a proper clock rate from Video_PLL if the DSI is operational due to the way the clock divides the pixel clocks from video_pll. To make the LVDS work, the LVDS needs to use an alternative clock. Because the clock rated needed for the LDB driving the LVDS display isn't divisible by the clock rate needed by SAI3, move SAI3 to use Audio_PLL1, and reconfigure the CODEC to use a 12MHz fixed clock. Because these clocks are no longer in sync with each other, the sound generated as the wrong pitch, so reconfigure the SAI3 to be the master since the CODEC can internally compensate when fed a fixed clock reference, even if it is not an even multiple of the desired rate. This now leaves AUDIO_PLL2 completely free for the LDB without compromising the audio sound from the codec. Signed-off-by: Adam Ford diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index a08057410bde..1f827ef38e36 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -211,20 +211,20 @@ sound-wm8962 { simple-audio-card,cpu { sound-dai = <&sai3>; + frame-master; + bitclock-master; }; simple-audio-card,codec { sound-dai = <&wm8962>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - frame-master; - bitclock-master; }; }; }; &audio_blk_ctrl { - assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; - assigned-clock-rates = <393216000>, <135475200>; + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>; + assigned-clock-rates = <393216000>; }; &ecspi2 { @@ -370,8 +370,8 @@ wm8962: audio-codec@1a { pinctrl-0 = <&pinctrl_wm8962>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <22576000>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <12000000>; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; @@ -499,10 +499,9 @@ &pcie_phy { &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MP_CLK_SAI3>, - <&clk IMX8MP_AUDIO_PLL2> ; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <12288000>, <361267200>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; fsl,sai-mclk-direction-output; status = "okay"; };