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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id k40-20020a05600c1ca800b00412b643b5a3sm1922750wms.11.2024.02.29.04.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Feb 2024 04:11:59 -0800 (PST) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrea Parri , Samuel Holland , Anup Patel , Steven Rostedt , Masami Hiramatsu , Mark Rutland , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org Cc: Alexandre Ghiti , Andrea Parri Subject: [PATCH v3 1/2] riscv: Remove superfluous smp_mb() Date: Thu, 29 Feb 2024 13:10:55 +0100 Message-Id: <20240229121056.203419-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240229121056.203419-1-alexghiti@rivosinc.com> References: <20240229121056.203419-1-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792235275969835404 X-GMAIL-MSGID: 1792235275969835404 This memory barrier is not needed and not documented so simply remove it. Suggested-by: Andrea Parri Signed-off-by: Alexandre Ghiti Reviewed-by: Andrea Parri --- arch/riscv/kernel/patch.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c index 37e87fdcf6a0..0b5c16dfe3f4 100644 --- a/arch/riscv/kernel/patch.c +++ b/arch/riscv/kernel/patch.c @@ -239,7 +239,6 @@ static int patch_text_cb(void *data) } else { while (atomic_read(&patch->cpu_count) <= num_online_cpus()) cpu_relax(); - smp_mb(); } return ret; From patchwork Thu Feb 29 12:10:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 208339 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2097:b0:108:e6aa:91d0 with SMTP id gs23csp350640dyb; Thu, 29 Feb 2024 04:18:32 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU9FL0prppoxfRO8HkLgxZeOI10uBbxrhzsK5GgJztM2SlvugAhMug/B1kZ0HjeBbvuWmgvpIgATyEXMzjJXb8jnqccUw== X-Google-Smtp-Source: AGHT+IEVEw3hOhgQ1stVpcvby6NEbpRHku/MT7xUnvFege4NrLSil+VDxMofnmsXLMm2XM6CjHt/ X-Received: by 2002:a17:903:41c8:b0:1dc:a5fd:6dd3 with SMTP id u8-20020a17090341c800b001dca5fd6dd3mr1992363ple.29.1709209112284; Thu, 29 Feb 2024 04:18:32 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709209112; cv=pass; d=google.com; s=arc-20160816; b=krtO3wBFnt3FMHkVgMdaNiGu1NaX7+rqCbA5lJDZ1KZNA+5pA1EI4cQWwTF1ZW0eO7 VJBeU1Xg+4LKW5dl/Szgh88WtOA3jizxo0KjxveQRewpcAveRRCi2uydOqSJrrT74vjA 2/ZairqvKVCF6P9EJF6zEIISCWuuzKWe7Zl7RHSxcTS0OritDMG5ywlDus5altkdMt+T mcyt9oBtArFeJdMwJ/koqdBTNNbzn1SZ+SxSshB0XsY1j5KSNXGkUu4Cy/CBfdePLlew 1ELs4LcRN/MeqJub8YJWL1NDXvUbPqk6rC540zF0eonUqV2wJWmJNCLLj2NTAW2GpAwR W+Hg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=pXXIgfsi20sfR9R1Bl8KEYowaEbmYUeJCudNzsi7ozU=; fh=QXzttAyg/c6o9biF/ggPDIkRSkOMGq+eFIWlaoWYZVo=; b=s+O0cZC51Xo/Hgu7tx3+RX3OupihCim+bjxAGa+hnkQ+RUw6azNfZfYFclzshm313i lXK3td04G0BJCzDuP+tNKzq2+sH8/uQ3uDdosqzTvZhLiu++LVSKpYZ1Mj0QG84w9icC Edu8FcKdi0ZsQsrUOL9ZIKUpTD5SYlJGvIFP0WviyiJIU8IGE4NVuqMaP5e898kwwXGF SSSUVq0sXJXTW437q2cZjXCDFLJjHlrBD5k7SDce9mOjhMXxiofH8e/NL374UQTFN+tW w3Mytsfl8Q5TBOCMezACnn4FO/ytw8Oex+P/nEq+xlAdrmhWJNO/WrlfIExMq6R+eCac o8BQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=TN3uA1De; arc=pass (i=1 spf=pass spfdomain=rivosinc.com dkim=pass dkdomain=rivosinc-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-86680-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-86680-ouuuleilei=gmail.com@vger.kernel.org" Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id r3-20020adfca83000000b0033d2ae84fafsm1605970wrh.52.2024.02.29.04.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Feb 2024 04:13:00 -0800 (PST) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrea Parri , Samuel Holland , Anup Patel , Steven Rostedt , Masami Hiramatsu , Mark Rutland , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org Cc: Alexandre Ghiti , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrea Parri Subject: [PATCH v3 2/2] riscv: Fix text patching when IPI are used Date: Thu, 29 Feb 2024 13:10:56 +0100 Message-Id: <20240229121056.203419-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240229121056.203419-1-alexghiti@rivosinc.com> References: <20240229121056.203419-1-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792235654330146390 X-GMAIL-MSGID: 1792235654330146390 For now, we use stop_machine() to patch the text and when we use IPIs for remote icache flushes (which is emitted in patch_text_nosync()), the system hangs. So instead, make sure every CPU executes the stop_machine() patching function and emit a local icache flush there. Co-developed-by: Björn Töpel Signed-off-by: Björn Töpel Signed-off-by: Alexandre Ghiti Reviewed-by: Andrea Parri --- arch/riscv/include/asm/patch.h | 1 + arch/riscv/kernel/ftrace.c | 44 ++++++++++++++++++++++++++++++---- arch/riscv/kernel/patch.c | 16 +++++++++---- 3 files changed, 53 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/patch.h b/arch/riscv/include/asm/patch.h index e88b52d39eac..9f5d6e14c405 100644 --- a/arch/riscv/include/asm/patch.h +++ b/arch/riscv/include/asm/patch.h @@ -6,6 +6,7 @@ #ifndef _ASM_RISCV_PATCH_H #define _ASM_RISCV_PATCH_H +int patch_insn_write(void *addr, const void *insn, size_t len); int patch_text_nosync(void *addr, const void *insns, size_t len); int patch_text_set_nosync(void *addr, u8 c, size_t len); int patch_text(void *addr, u32 *insns, int ninsns); diff --git a/arch/riscv/kernel/ftrace.c b/arch/riscv/kernel/ftrace.c index f5aa24d9e1c1..4f4987a6d83d 100644 --- a/arch/riscv/kernel/ftrace.c +++ b/arch/riscv/kernel/ftrace.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -75,8 +76,7 @@ static int __ftrace_modify_call(unsigned long hook_pos, unsigned long target, make_call_t0(hook_pos, target, call); /* Replace the auipc-jalr pair at once. Return -EPERM on write error. */ - if (patch_text_nosync - ((void *)hook_pos, enable ? call : nops, MCOUNT_INSN_SIZE)) + if (patch_insn_write((void *)hook_pos, enable ? call : nops, MCOUNT_INSN_SIZE)) return -EPERM; return 0; @@ -88,7 +88,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) make_call_t0(rec->ip, addr, call); - if (patch_text_nosync((void *)rec->ip, call, MCOUNT_INSN_SIZE)) + if (patch_insn_write((void *)rec->ip, call, MCOUNT_INSN_SIZE)) return -EPERM; return 0; @@ -99,7 +99,7 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, { unsigned int nops[2] = {NOP4, NOP4}; - if (patch_text_nosync((void *)rec->ip, nops, MCOUNT_INSN_SIZE)) + if (patch_insn_write((void *)rec->ip, nops, MCOUNT_INSN_SIZE)) return -EPERM; return 0; @@ -134,6 +134,42 @@ int ftrace_update_ftrace_func(ftrace_func_t func) return ret; } + +struct ftrace_modify_param { + int command; + atomic_t cpu_count; +}; + +static int __ftrace_modify_code(void *data) +{ + struct ftrace_modify_param *param = data; + + if (atomic_inc_return(¶m->cpu_count) == num_online_cpus()) { + ftrace_modify_all_code(param->command); + /* + * Make sure the patching store is effective *before* we + * increment the counter which releases all waiting CPUs + * by using the release variant of atomic increment. The + * release pairs with the call to local_flush_icache_all() + * on the waiting CPU. + */ + atomic_inc_return_release(¶m->cpu_count); + } else { + while (atomic_read(¶m->cpu_count) <= num_online_cpus()) + cpu_relax(); + } + + local_flush_icache_all(); + + return 0; +} + +void arch_ftrace_update_code(int command) +{ + struct ftrace_modify_param param = { command, ATOMIC_INIT(0) }; + + stop_machine(__ftrace_modify_code, ¶m, cpu_online_mask); +} #endif #ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c index 0b5c16dfe3f4..9a1bce1adf5a 100644 --- a/arch/riscv/kernel/patch.c +++ b/arch/riscv/kernel/patch.c @@ -188,7 +188,7 @@ int patch_text_set_nosync(void *addr, u8 c, size_t len) } NOKPROBE_SYMBOL(patch_text_set_nosync); -static int patch_insn_write(void *addr, const void *insn, size_t len) +int patch_insn_write(void *addr, const void *insn, size_t len) { size_t patched = 0; size_t size; @@ -232,15 +232,23 @@ static int patch_text_cb(void *data) if (atomic_inc_return(&patch->cpu_count) == num_online_cpus()) { for (i = 0; ret == 0 && i < patch->ninsns; i++) { len = GET_INSN_LENGTH(patch->insns[i]); - ret = patch_text_nosync(patch->addr + i * len, - &patch->insns[i], len); + ret = patch_insn_write(patch->addr + i * len, &patch->insns[i], len); } - atomic_inc(&patch->cpu_count); + /* + * Make sure the patching store is effective *before* we + * increment the counter which releases all waiting CPUs + * by using the release variant of atomic increment. The + * release pairs with the call to local_flush_icache_all() + * on the waiting CPU. + */ + atomic_inc_return_release(&patch->cpu_count); } else { while (atomic_read(&patch->cpu_count) <= num_online_cpus()) cpu_relax(); } + local_flush_icache_all(); + return ret; } NOKPROBE_SYMBOL(patch_text_cb);