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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n1-20020a170902e54100b00185466d72e8si63773plf.320.2022.11.16.21.04.05; Wed, 16 Nov 2022 21:04:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=jTCSb+H8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239239AbiKQFBz (ORCPT + 99 others); Thu, 17 Nov 2022 00:01:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234651AbiKQFBV (ORCPT ); Thu, 17 Nov 2022 00:01:21 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12B86326EC; Wed, 16 Nov 2022 21:01:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668661265; x=1700197265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0ULeWXATHxlooqOwDRTF6YtD/vn0X4PQHlOBJWw8Or4=; b=jTCSb+H8kp6TuZ9qTkQJ/DRniRNOpaaDD49ledBED9f8H55oK1fxqO// ab1dO6nzoszZyDPupeWPs9HqsYISLKNDz9Jb96+dCBD5s6cjod/6Jt3p1 Mrm0R2VWdSNdCKlmTPUBdj7V0x2sduYFk71KmldMig2ruvYU9bQeu01s0 ldzpIyYOvyxvjZ4leXfeLtpBo/MLzo9+XeRQQysxkuKavLo6nR/WWS0fC +j1azMUlFUE0VUkGhG+73QFbJ2IVHwtvy2nvoy/zXMvvtFyxHn7fDHVfM N2GiH1rzdhnoixJoxWb/N0y5Q7OtiVingR8OE/dtshjuBYwUav7F/upyU g==; X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="183919258" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2022 22:01:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 16 Nov 2022 22:01:02 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 16 Nov 2022 22:00:56 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v5 tty-next 1/4] 8250: microchip: pci1xxxx: Add driver for quad-uart support. Date: Thu, 17 Nov 2022 10:31:23 +0530 Message-ID: <20221117050126.2966714-2-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> References: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749718357544310973?= X-GMAIL-MSGID: =?utf-8?q?1749718357544310973?= pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. Quad-uart is one of the functions in the multi-function endpoint. This driver loads for the quad-uart and enumerates single or multiple instances of uart based on the PCIe subsystem device ID. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v5: - Used tabs instead of spaces in MACRO definitions for readability - Removed assignments that are not required - Removed redundant blank lines Changes in v4: - Renamed pci_setup_port to serial8250_pci_setup_port - Added Copyright information to 8250_pcilib.c Changes in v3: - Used NSEC_PER_SEC, HZ_PER_MHZ, FIELD_PREP, FIELD_GET MACROs wherever necessary - Handled failure case of serial8250_register_8250_port properly - Moved pci_setup_port to 8250_pcilib.c Changes in v2: - Use only the 62.5 MHz for baud clock. - Define custom implementation for get_divisor and set_divisor. - Use BOTHER instead of UPF_SPD_CUST for non standard baud rates (untested). - Correct indentation in clock divisor computation. - Remove unnecessary call to pci_save_state in probe function. - Fix null pointer dereference in probe function. - Move pci1xxxx_rs485_config to a separate patch. - Depends on SERIAL_8250_PCI & default to SERIAL_8250. - Change PORT_MCHP16550A to 100 from 124. --- MAINTAINERS | 7 + drivers/tty/serial/8250/8250_pci1xxxx.c | 372 ++++++++++++++++++++++++ drivers/tty/serial/8250/8250_port.c | 8 + drivers/tty/serial/8250/Kconfig | 10 + drivers/tty/serial/8250/Makefile | 1 + include/uapi/linux/serial_core.h | 3 + 6 files changed, 401 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_pci1xxxx.c diff --git a/MAINTAINERS b/MAINTAINERS index d30f26e07cd3..aa98deaba249 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13434,6 +13434,13 @@ F: Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml F: drivers/nvmem/microchip-otpc.c F: include/dt-bindings/nvmem/microchip,sama7g5-otpc.h +MICROCHIP PCIe UART DRIVER +M: Kumaravel Thiagarajan +M: Tharun Kumar P +L: linux-serial@vger.kernel.org +S: Maintained +F: drivers/tty/serial/8250/8250_pci1xxxx.c + MICROCHIP PWM DRIVER M: Claudiu Beznea L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c new file mode 100644 index 000000000000..9dd7aca76e58 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Probe module for 8250/16550-type MCHP PCI serial ports. + * + * Based on drivers/tty/serial/8250/8250_pci.c, + * + * Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "8250.h" + +#define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 +#define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 +#define PCI_DEVICE_ID_EFAR_PCI11101 0xa022 +#define PCI_DEVICE_ID_EFAR_PCI11400 0xa032 +#define PCI_DEVICE_ID_EFAR_PCI11414 0xa042 + +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p 0x0001 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012 0x0002 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013 0x0003 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023 0x0004 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123 0x0005 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01 0x0006 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02 0x0007 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03 0x0008 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12 0x0009 +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13 0x000a +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23 0x000b +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0 0x000c +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1 0x000d +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2 0x000e +#define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 0x000f + +#define PCI_SUBDEVICE_ID_EFAR_PCI12000 0xa002 +#define PCI_SUBDEVICE_ID_EFAR_PCI11010 0xa012 +#define PCI_SUBDEVICE_ID_EFAR_PCI11101 0xa022 +#define PCI_SUBDEVICE_ID_EFAR_PCI11400 0xa032 +#define PCI_SUBDEVICE_ID_EFAR_PCI11414 0xa042 + +#define UART_ACTV_REG 0x11 +#define UART_BLOCK_SET_ACTIVE BIT(0) + +#define UART_PCI_CTRL_REG 0x80 +#define UART_PCI_CTRL_SET_MULTIPLE_MSI BIT(4) +#define UART_PCI_CTRL_D3_CLK_ENABLE BIT(0) + +#define ADCL_CFG_REG 0x40 +#define ADCL_CFG_POL_SEL BIT(2) +#define ADCL_CFG_PIN_SEL BIT(1) +#define ADCL_CFG_EN BIT(0) + +#define UART_BIT_SAMPLE_CNT 16 +#define BAUD_CLOCK_DIV_INT_MSK GENMASK(31, 8) +#define ADCL_CFG_RTS_DELAY_MASK GENMASK(11, 8) +#define UART_CLOCK_DEFAULT (62.5 * HZ_PER_MHZ) + +#define UART_WAKE_REG 0x8C +#define UART_WAKE_MASK_REG 0x90 +#define UART_WAKE_N_PIN BIT(2) +#define UART_WAKE_NCTS BIT(1) +#define UART_WAKE_INT BIT(0) +#define UART_WAKE_SRCS \ + (UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT) + +#define UART_BAUD_CLK_DIVISOR_REG 0x54 + +#define UART_RESET_REG 0x94 +#define UART_RESET_D3_RESET_DISABLE BIT(16) + +struct pci1xxxx_8250 { + struct pci_dev *dev; + unsigned int nr; + void __iomem *membase; + int line[]; +}; + +static int pci1xxxx_get_num_ports(struct pci_dev *dev) +{ + switch (dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + default: + return 1; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + return 2; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + return 3; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: + case PCI_SUBDEVICE_ID_EFAR_PCI11414: + return 4; + } +} + +static unsigned int pci1xxxx_get_divisor(struct uart_port *port, + unsigned int baud, unsigned int *frac) +{ + unsigned int quot; + + /* + * Calculate baud rate sampling period in nanoseconds. + * Fractional part x denotes x/255 parts of a nanosecond. + */ + quot = (NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT)); + *frac = (((NSEC_PER_SEC - (quot * baud * UART_BIT_SAMPLE_CNT)) / + UART_BIT_SAMPLE_CNT) * 255) / baud; + + return quot; +} + +static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, + unsigned int quot, unsigned int frac) +{ + writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac, + port->membase + UART_BAUD_CLK_DIVISOR_REG); +} + +static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, + struct uart_8250_port *port, int idx) +{ + int first_offset; + int offset; + + switch (priv->dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + first_offset = 256; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + first_offset = 512; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + first_offset = 768; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + first_offset = 256; + break; + default: + first_offset = 0; + break; + } + + switch (priv->dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + if (idx > 0) + idx++; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + if (idx > 0) + idx += 2; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + if (idx > 0) + idx++; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + if (idx > 1) + idx++; + break; + } + + offset = first_offset + idx * 256; + port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; + port->port.type = PORT_MCHP16550A; + port->port.set_termios = serial8250_do_set_termios; + port->port.get_divisor = pci1xxxx_get_divisor; + port->port.set_divisor = pci1xxxx_set_divisor; + writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); + writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); + + return 0; +} + +static void pci1xxxx_irq_assign(struct pci1xxxx_8250 *priv, + struct uart_8250_port *uart, int idx) +{ + int irq_idx; + + switch (priv->dev->subsystem_device) { + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0: + case PCI_SUBDEVICE_ID_EFAR_PCI12000: + case PCI_SUBDEVICE_ID_EFAR_PCI11010: + case PCI_SUBDEVICE_ID_EFAR_PCI11101: + case PCI_SUBDEVICE_ID_EFAR_PCI11400: + default: + irq_idx = 0; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: + irq_idx = 1; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2: + irq_idx = 2; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3: + irq_idx = 3; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01: + irq_idx = idx; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02: + if (idx > 0) + idx++; + irq_idx = idx; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03: + if (idx > 0) + idx += 2; + irq_idx = idx; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12: + irq_idx = idx + 1; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13: + if (idx > 0) + idx += 1; + irq_idx = idx + 1; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23: + irq_idx = idx + 2; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012: + irq_idx = idx; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013: + if (idx > 1) + idx++; + irq_idx = idx; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023: + if (idx > 0) + idx++; + irq_idx = idx; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123: + irq_idx = idx + 1; + break; + case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p: + case PCI_SUBDEVICE_ID_EFAR_PCI11414: + irq_idx = idx; + break; + } + uart->port.irq = pci_irq_vector(priv->dev, irq_idx); +} + +static int pci1xxxx_serial_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + unsigned int nr_ports, i; + struct pci1xxxx_8250 *priv; + struct uart_8250_port uart; + struct device *dev; + int num_vectors; + int rc; + + dev = &pdev->dev; + rc = pcim_enable_device(pdev); + if (rc) + return rc; + + nr_ports = pci1xxxx_get_num_ports(pdev); + + priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->membase = pcim_iomap(pdev, 0, 0); + priv->dev = pdev; + priv->nr = nr_ports; + pci_set_master(pdev); + + num_vectors = pci_alloc_irq_vectors(pdev, 1, 4, PCI_IRQ_ALL_TYPES); + if (num_vectors < 0) + return num_vectors; + + memset(&uart, 0, sizeof(uart)); + uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; + uart.port.uartclk = UART_CLOCK_DEFAULT; + uart.port.dev = dev; + + if (num_vectors == 4) + writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, + priv->membase + UART_PCI_CTRL_REG); + else + uart.port.irq = pci_irq_vector(pdev, 0); + + for (i = 0; i < nr_ports; i++) + priv->line[i] = -ENOSPC; + + for (i = 0; i < nr_ports; i++) { + if (num_vectors == 4) + pci1xxxx_irq_assign(priv, &uart, i); + + rc = pci1xxxx_setup(priv, &uart, i); + if (rc) { + dev_warn(dev, "Failed to setup port %u\n", i); + break; + } + priv->line[i] = serial8250_register_8250_port(&uart); + if (priv->line[i] < 0) { + dev_err(dev, + "Couldn't register serial port %lx, irq %d, type %d, error %d\n", + uart.port.iobase, uart.port.irq, + uart.port.iotype, priv->line[i]); + break; + } + } + + pci_set_drvdata(pdev, priv); + + return 0; +} + +static void pci1xxxx_serial_remove(struct pci_dev *dev) +{ + struct pci1xxxx_8250 *priv = pci_get_drvdata(dev); + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) + serial8250_unregister_port(priv->line[i]); + } +} + +static const struct pci_device_id pci1xxxx_pci_tbl[] = { + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11400) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11414) }, + { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI12000) }, + {} +}; +MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl); + +static struct pci_driver pci1xxxx_pci_driver = { + .name = "pci1xxxx serial", + .probe = pci1xxxx_serial_probe, + .remove = pci1xxxx_serial_remove, + .id_table = pci1xxxx_pci_tbl, +}; +module_pci_driver(pci1xxxx_pci_driver); + +MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module"); +MODULE_AUTHOR("Kumaravel Thiagarajan "); +MODULE_AUTHOR("Tharun Kumar P "); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 1d2a43214b48..ec2fe5fd7b02 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -313,6 +313,14 @@ static const struct serial8250_config uart_config[] = { .rxtrig_bytes = {1, 4, 8, 14}, .flags = UART_CAP_FIFO, }, + [PORT_MCHP16550A] = { + .name = "MCHP16550A", + .fifo_size = 256, + .tx_loadsz = 256, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01, + .rxtrig_bytes = {2, 66, 130, 194}, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index d0b49e15fbf5..1c41722d8ac5 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -291,6 +291,16 @@ config SERIAL_8250_HUB6 To compile this driver as a module, choose M here: the module will be called 8250_hub6. +config SERIAL_8250_PCI1XXXX + tristate "Microchip 8250 based serial port" + depends on SERIAL_8250_PCI + default SERIAL_8250 + help + Select this option if you have a setup with Microchip PCIe + Switch with serial port enabled and wish to enable 8250 + serial driver for the serial interface. This driver support + will ensure to support baud rates upto 1.5Mpbs. + # # Misc. options/drivers. # diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index bee908f99ea0..fbc7d47c25bd 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o +obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 3ba34d8378bd..281fa286555c 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -207,6 +207,9 @@ /* Atheros AR933X SoC */ #define PORT_AR933X 99 +/* MCHP 16550A UART with 256 byte FIFOs */ +#define PORT_MCHP16550A 100 + /* ARC (Synopsys) on-chip UART */ #define PORT_ARC 101 From patchwork Thu Nov 17 05:01:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 21433 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp216933wrr; Wed, 16 Nov 2022 21:03:09 -0800 (PST) X-Google-Smtp-Source: AA0mqf6UPjpy46lN+w3RKv7n6OIlWmcOZ4MJ60sVt22LickxcWmVOhdVaOxgK1FzL87vKveDBMiN X-Received: by 2002:a62:1d05:0:b0:56b:a0f4:decc with SMTP id d5-20020a621d05000000b0056ba0f4deccmr1341200pfd.33.1668661386248; Wed, 16 Nov 2022 21:03:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668661386; cv=none; d=google.com; s=arc-20160816; b=CyRBLxFkirhaRLU0WZewDBDxIgEzJ0PkMBimDeJzSf02Fdt2x7+RZPE5nkKf5FZQIL UPru31VEQM6w5zXIvuQLgljQHtE/4cPSE6qOe/Mpf9JsSMY5hVVHJfkU6q3mBihz5AU+ iFLLJNH5IuNf/vFLRAW6bVfcItb2KsDHrellA51/pi01KVPLTSsY/pozGa8LjHImZAl5 AXYeMg+Q+hH3z0WtJudyqSdLZY9cTT0Rq6t+id3xn+M4UA+wszEuo4WlhT4y6CcnA198 JLpiNrBUflSiwMWxJh0BOMPIYH9kD2tbIq/oLcr4sMDrl4hTgTJZbTIHVY8PBbcFjHKo 6CPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rRJXGb5p29RyESxeVi62pZP/y70N89137uDYqddEBcs=; b=oynk33EWayMVSiZeUe6wQ3raqUlGsjl+y7LAV7cU+M+NnoJCO5GH47qYtcoBe0lSrh wntfW1my9CUXPcAHGgxOxGK0ybqm+VNLx0rb7P6kIQpdYtsLAcbksEQ2Ei5daco8Eh7p kKaJoaUvIyQhvaFzwVIy0q2aKb443u7F+PWZQ4pyJx6xG58/gqAVxjX5oowB6yz2iJMh 1CnB/KeowLauMSIwyDqc1ypak+l88ITKwA+lFnbwE1A335Es1RHaNtRkJhKz2mRGPl6i /fgwCD/bGlH3dVM48HaEHEyO6vuu0undr8jEbrBCC0iY6jES9xsJOi0bVtqktUz2npSl lrUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=VaN6XOoH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. 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Wed, 16 Nov 2022 22:01:10 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 16 Nov 2022 22:01:04 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v5 tty-next 2/4] 8250: microchip: pci1xxxx: Add serial8250_pci_setup_port definition in 8250_pcilib.c Date: Thu, 17 Nov 2022 10:31:24 +0530 Message-ID: <20221117050126.2966714-3-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> References: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749718281485958237?= X-GMAIL-MSGID: =?utf-8?q?1749718281485958237?= Move implementation of setup_port API to serial8250_pci_setup_port Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v5: - This is the new patch added in v5 version of this patchset - Moved implementation of setup_port from 8250_pci.c to 8250_pcilib.c --- drivers/tty/serial/8250/8250_pci.c | 24 ++-------------- drivers/tty/serial/8250/8250_pci1xxxx.c | 6 ++++ drivers/tty/serial/8250/8250_pcilib.c | 38 +++++++++++++++++++++++++ drivers/tty/serial/8250/8250_pcilib.h | 9 ++++++ drivers/tty/serial/8250/Kconfig | 5 ++++ drivers/tty/serial/8250/Makefile | 1 + 6 files changed, 61 insertions(+), 22 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_pcilib.c create mode 100644 drivers/tty/serial/8250/8250_pcilib.h diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 6f66dc2ebacc..69ff367b08de 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -24,6 +24,7 @@ #include #include "8250.h" +#include "8250_pcilib.h" /* * init function returns: @@ -89,28 +90,7 @@ static int setup_port(struct serial_private *priv, struct uart_8250_port *port, u8 bar, unsigned int offset, int regshift) { - struct pci_dev *dev = priv->dev; - - if (bar >= PCI_STD_NUM_BARS) - return -EINVAL; - - if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { - if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) - return -ENOMEM; - - port->port.iotype = UPIO_MEM; - port->port.iobase = 0; - port->port.mapbase = pci_resource_start(dev, bar) + offset; - port->port.membase = pcim_iomap_table(dev)[bar] + offset; - port->port.regshift = regshift; - } else { - port->port.iotype = UPIO_PORT; - port->port.iobase = pci_resource_start(dev, bar) + offset; - port->port.mapbase = 0; - port->port.membase = NULL; - port->port.regshift = 0; - } - return 0; + return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); } /* diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index 9dd7aca76e58..02b9c6959dcc 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -22,6 +22,7 @@ #include #include "8250.h" +#include "8250_pcilib.h" #define PCI_DEVICE_ID_EFAR_PCI12000 0xa002 #define PCI_DEVICE_ID_EFAR_PCI11010 0xa012 @@ -143,6 +144,7 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, { int first_offset; int offset; + int ret; switch (priv->dev->subsystem_device) { case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1: @@ -191,6 +193,10 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; + ret = serial8250_pci_setup_port(priv->dev, port, 0, offset, 0); + if (ret < 0) + return ret; + writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); diff --git a/drivers/tty/serial/8250/8250_pcilib.c b/drivers/tty/serial/8250/8250_pcilib.c new file mode 100644 index 000000000000..e5a4a9b22c81 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * 8250 PCI library. + * + * Copyright (C) 2001 Russell King, All Rights Reserved. + */ +#include +#include +#include +#include + +#include "8250.h" + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, + u8 bar, unsigned int offset, int regshift) +{ + if (bar >= PCI_STD_NUM_BARS) + return -EINVAL; + + if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { + if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) + return -ENOMEM; + + port->port.iotype = UPIO_MEM; + port->port.iobase = 0; + port->port.mapbase = pci_resource_start(dev, bar) + offset; + port->port.membase = pcim_iomap_table(dev)[bar] + offset; + port->port.regshift = regshift; + } else { + port->port.iotype = UPIO_PORT; + port->port.iobase = pci_resource_start(dev, bar) + offset; + port->port.mapbase = 0; + port->port.membase = NULL; + port->port.regshift = 0; + } + return 0; +} +EXPORT_SYMBOL_GPL(serial8250_pci_setup_port); diff --git a/drivers/tty/serial/8250/8250_pcilib.h b/drivers/tty/serial/8250/8250_pcilib.h new file mode 100644 index 000000000000..41ef01d5c3c5 --- /dev/null +++ b/drivers/tty/serial/8250/8250_pcilib.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * 8250 PCI library header file. + * + * Copyright (C) 2001 Russell King, All Rights Reserved. + */ + +int serial8250_pci_setup_port(struct pci_dev *dev, struct uart_8250_port *port, u8 bar, + unsigned int offset, int regshift); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index 1c41722d8ac5..f67542470eae 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -132,6 +132,7 @@ config SERIAL_8250_DMA config SERIAL_8250_PCI tristate "8250/16550 PCI device support" depends on SERIAL_8250 && PCI + select SERIAL_8250_PCILIB default SERIAL_8250 help This builds standard PCI serial support. You may be able to @@ -294,6 +295,7 @@ config SERIAL_8250_HUB6 config SERIAL_8250_PCI1XXXX tristate "Microchip 8250 based serial port" depends on SERIAL_8250_PCI + select SERIAL_8250_PCILIB default SERIAL_8250 help Select this option if you have a setup with Microchip PCIe @@ -510,6 +512,9 @@ config SERIAL_8250_MID Intel Medfield SOC and various other Intel platforms that is not covered by the more generic SERIAL_8250_PCI option. +config SERIAL_8250_PCILIB + bool + config SERIAL_8250_PERICOM tristate "Support for Pericom and Acces I/O serial ports" default SERIAL_8250 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index fbc7d47c25bd..98202fdf39f8 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o 8250_base-$(CONFIG_SERIAL_8250_DMA) += 8250_dma.o 8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o +8250_base-$(CONFIG_SERIAL_8250_PCILIB) += 8250_pcilib.o obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o From patchwork Thu Nov 17 05:01:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 21434 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp217114wrr; Wed, 16 Nov 2022 21:03:39 -0800 (PST) X-Google-Smtp-Source: AA0mqf6guKtGUx3uKSCfMK+0rnGk3gkrCCuI89WiHHhdAkYP7De7aK/OiwrGnxr2IdqGDHuMM04f X-Received: by 2002:a62:1582:0:b0:563:f32:2c9d with SMTP id 124-20020a621582000000b005630f322c9dmr1327852pfv.32.1668661419035; Wed, 16 Nov 2022 21:03:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668661419; cv=none; d=google.com; s=arc-20160816; b=tVTNTlRHUY5Zmsz4ZIeIaBE3qyAN6bq8inAvwmTWJDs/JvQgcN5ZIjOUH/AVg4yYYd 6R8KNnTyzV6n6ezt+P7kmSDXnW/NCzbfXI06LBRGhol/DuFcIcb5Gvr1lASBCU4zqZR+ mT82H/ajtpwgmi0uuHbdHkAxr3SbRiNTLGiyFm7Cy+llsQCA9V4HBrYqQRsiUSDitmhO 4MOMW4bghxUUY6ESWksUJM6+vR56bC47WyQVS1c5Y/evsBWe+jsdPQDqIGgPnhqZ6Yxo CVzNhUSvI1kX72kahxdh7+ve9dfHTMcdseH6uzHMkp6PEHiXGCj9I0VQXf3VfN5+AixD hh2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UH0uo3qvfT0N8FgInW/HXfCMnUVmG+wYXW7ts8IIhMc=; b=sg0MU3MWh0Qfxtbje5KGJGyiv1hsnMQVpU/zdLvV3PJjZKUdyx1ow8Joga8V0LKVDZ LkegrCi4gnU/+vQ0pTocjllAdIbhYFEaptCRE4SSK9zw/zZKC+BiE4WNkiYCBLf3I+1a igQHeoPdg2+evMrYvGNT3CSO4yA1j9vRR9TTUl+qY5+ULd/u34Nk+kLn++TFEnOScqA9 kPSrRverX8MlWnzEuYs20JmzdvoIVozYjHNb+beaIXLzAUEZrdMmLs6CMXb0TwtohTDa OjuyLTJIZSGJlh3YsjzoK5KwFqVotn1WXPxZOJAh+FQXBBSjeKjrXkAd1GluNM8xl80Z w0EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=hnWPIQBa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h8-20020a656388000000b0046fd9ddc689si39484pgv.571.2022.11.16.21.03.26; Wed, 16 Nov 2022 21:03:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=hnWPIQBa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238829AbiKQFBo (ORCPT + 99 others); Thu, 17 Nov 2022 00:01:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234681AbiKQFBb (ORCPT ); Thu, 17 Nov 2022 00:01:31 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9CAE654E4; Wed, 16 Nov 2022 21:01:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668661279; x=1700197279; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KtXZOYbD4plLDa2Ad1WCAaIg5uR0r+ACgPobtXvRYeU=; b=hnWPIQBaJEGKYFGXoeJGNXpiLaWr64RQ4bDJEjv4Y9j9kZCPKU6ZV5In QrzzObErA0/+EKbsmrkbhbCifiwAuws1DYtRxJcIOk2Mz4+5glTPcVrHK HUcqVY+XLu4SiNdYhUN4YJPxDPp1OAFCn4DUwb440zwJhm1V1Qy4hOU1R xF8X0UdjtSkusVBcNF8FNMhZUgdWJjsJ2y9zu5kWSxCtRPpo68JAr66qI zK+ortNYNbIvmHkI03CNTRNeT9vijQezFCgkxRUbnSMdmLbNC5kcQDxpN 2HQ1Vd9VLKPT1Z1YHgXT/7Y3SC99JShz69zOPKEgLMm26F8PBSC9UJXHC A==; X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="187387079" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2022 22:01:18 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 16 Nov 2022 22:01:18 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 16 Nov 2022 22:01:12 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v5 tty-next 3/4] 8250: microchip: pci1xxxx: Add RS485 support to quad-uart driver Date: Thu, 17 Nov 2022 10:31:25 +0530 Message-ID: <20221117050126.2966714-4-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> References: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749718316376570185?= X-GMAIL-MSGID: =?utf-8?q?1749718316376570185?= pci1xxxx uart supports RS485 mode of operation in the hardware with auto-direction control with configurable delay for releasing RTS after the transmission. This patch adds support for the RS485 mode. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v5: - Removed unnecessary assignments - Corrected styling issues in comments Changes in v4: - No Change Changes in v3: - Remove flags sanitization in driver which is taken care in core Changes in v2: - move pci1xxxx_rs485_config to a separate patch with pci1xxxx_rs485_supported. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 50 +++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index 02b9c6959dcc..bead9fd4019e 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -139,6 +139,54 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, port->membase + UART_BAUD_CLK_DIVISOR_REG); } +static int pci1xxxx_rs485_config(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u32 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); + u8 delay_in_baud_periods; + u32 baud_period_in_ns; + u32 data = 0; + + /* + * pci1xxxx's uart hardware supports only RTS delay after + * Tx and in units of bit times to a maximum of 15 + */ + if (rs485->flags & SER_RS485_ENABLED) { + data = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; + + if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) + data |= ADCL_CFG_POL_SEL; + + if (rs485->delay_rts_after_send) { + baud_period_in_ns = + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * + UART_BIT_SAMPLE_CNT; + delay_in_baud_periods = + (rs485->delay_rts_after_send * NSEC_PER_MSEC) / + baud_period_in_ns; + delay_in_baud_periods = + min_t(u8, delay_in_baud_periods, + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); + data |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, + delay_in_baud_periods); + rs485->delay_rts_after_send = + (baud_period_in_ns * delay_in_baud_periods) / + NSEC_PER_MSEC; + rs485->delay_rts_before_send = 0; + } + } + writel(data, port->membase + ADCL_CFG_REG); + return 0; +} + +static const struct serial_rs485 pci1xxxx_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND, + .delay_rts_after_send = 1, + /* Delay RTS before send is not supported */ +}; + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int idx) { @@ -193,6 +241,8 @@ static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; + port->port.rs485_config = pci1xxxx_rs485_config; + port->port.rs485_supported = pci1xxxx_rs485_supported; ret = serial8250_pci_setup_port(priv->dev, port, 0, offset, 0); if (ret < 0) return ret; From patchwork Thu Nov 17 05:01:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumaravel Thiagarajan X-Patchwork-Id: 21436 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp217451wrr; Wed, 16 Nov 2022 21:04:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf4GyI47Lkiq47mPSoZlG3B4fTW+oyNCPvfbXAO8Jl8kSF0aTQ8sItj/mKDAo5RZAHoauNEM X-Received: by 2002:a63:f047:0:b0:45c:eb5a:3361 with SMTP id s7-20020a63f047000000b0045ceb5a3361mr584004pgj.346.1668661484047; Wed, 16 Nov 2022 21:04:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668661484; cv=none; d=google.com; s=arc-20160816; b=UsmzBYwJZk4T63XAerK95yQ/REvCA5X6gd7TGEhP1YxprA9XW0WUaNtQyL5VAXnRsR AxSrqKQXB7QsHhh43kV9wXoo4BBSgiFuMsUtpZ0zb1rhtOqFvpVrYl9Fmm6HxJH/eAnr ZhVTYNpkKaHR0A0j+n8BA8tLSMJmcL9LmJXX4cCn9QlsWzA0vjoAkjfo9HbE5WHIuNX6 CxSz9A2sppGkuXPolqFeKvmtswdt3FSpJdc/7OeSYq3OlXBHwG9Kb76e6/QdhBoBFUDl Fh1aGXLKPyWp5Ja/sW8MWPuwaS5HbTtccKLHQXWhHudpOlq+1QAHl7ls7uVWRk/SJqjK gjsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hxQyM+j2g8NcfQYXd0Qtjozsq16ASfTymAWD99GJBnc=; b=WTQrNMnD+gsILD2rsJMERrUzfCnp4S0JdXq7/BTPm2yiPaq79zDQtb/WcPtQFfDTq3 uCsOI6zeE4H4xiulbATPl9l+oDtM9EfF0e/OxkHxYFQu5eQBRAihuqZn5/Muhwd2ctZe vkqoQpIn+a60S4dS3xgw2f8VEBjmSnUFOj5gMTHt8O1WFy2XfWcGhXPvwGpLFsUfIycn 32o/vAxwMUHde3vcqc088cYLUdbTMJBhi5SnUQnGaUnwdrwjUS6yp31KbDiPM0ehod/H RIo2J3FnTb0Mdkj3aIYeftq6fnjJKpmBEcAeZyzE54GxCjGx4GN9W78xgpV1qzO5u3lP 8MDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=JVN9CfDD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w15-20020a17090a5e0f00b00205ee3e845bsi3606642pjf.116.2022.11.16.21.04.31; Wed, 16 Nov 2022 21:04:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=JVN9CfDD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234672AbiKQFCe (ORCPT + 99 others); Thu, 17 Nov 2022 00:02:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234783AbiKQFBd (ORCPT ); Thu, 17 Nov 2022 00:01:33 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20C77391F5; Wed, 16 Nov 2022 21:01:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668661289; x=1700197289; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WIa7e02s2OlQrBiSr3I/1P4AtM84MFYonMHbPfbsrPY=; b=JVN9CfDDNsq8QjMlcBjvDz+ZjGnz7/3MNxNjjEKWslohONUkmta9XBGY J3ZRt+uqz2oBFq2zqrUoce+J+MJ2N2Un7KwnqzuYa7TlybaJDbIVN+Jbe /s7Z00RAAbu9NE759KAN8UXjP3NT96idDILEaJ2pjTgBbBahf+waD6COQ nWYI9NzXdMpbN2rJBfimi7rl2FJxWA7IiF6O+ysq7zcPbDcQgfbs54AxC +nh9JcwXTlWpu3PcWc22OOiWpbDBp/10PuCz4G0hBEBU+cX1nxWDKd6AO uI8lBAKY0AVRfD5Ha6OvKQHg4eKmLjZCCyEt92o7vlwmN4JHWYWHDSTT3 g==; X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="200162683" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Nov 2022 22:01:29 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 16 Nov 2022 22:01:26 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 16 Nov 2022 22:01:20 -0700 From: Kumaravel Thiagarajan To: , CC: , , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v5 tty-next 4/4] 8250: microchip: pci1xxxx: Add power management functions to quad-uart driver Date: Thu, 17 Nov 2022 10:31:26 +0530 Message-ID: <20221117050126.2966714-5-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> References: <20221117050126.2966714-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749718384626406050?= X-GMAIL-MSGID: =?utf-8?q?1749718384626406050?= pci1xxxx's quad-uart function has the capability to wake up UART from suspend state. Enable wakeup before entering into suspend and disable wakeup on resume. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan --- Changes in v5: - Corrected commit message Changes in v4: - No Change Changes in v3: - Handled race condition in suspend and resume callbacks Changes in v2: - Use DEFINE_SIMPLE_DEV_PM_OPS instead of SIMPLE_DEV_PM_OPS. - Use pm_sleep_ptr instead of CONFIG_PM_SLEEP. - Change the return data type of pci1xxxx_port_suspend to bool from int. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 116 ++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index bead9fd4019e..fa3477a7ea59 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -187,6 +187,116 @@ static const struct serial_rs485 pci1xxxx_rs485_supported = { /* Delay RTS before send is not supported */ }; +static bool pci1xxxx_port_suspend(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + bool ret = false; + u8 wakeup_mask; + + mutex_lock(&tport->mutex); + if (port->suspended == 0 && port->dev) { + wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); + + spin_lock_irqsave(&port->lock, flags); + port->mctrl &= ~TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + + ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; + } + + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + mutex_unlock(&tport->mutex); + + return ret; +} + +static void pci1xxxx_port_resume(int line) +{ + struct uart_8250_port *up = serial8250_get_port(line); + struct uart_port *port = &up->port; + struct tty_port *tport = &port->state->port; + unsigned long flags; + + mutex_lock(&tport->mutex); + writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); + writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); + + if (port->suspended == 0) { + spin_lock_irqsave(&port->lock, flags); + port->mctrl |= TIOCM_OUT2; + port->ops->set_mctrl(port, port->mctrl); + spin_unlock_irqrestore(&port->lock, flags); + } + mutex_unlock(&tport->mutex); +} + +static int pci1xxxx_suspend(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + bool wakeup = false; + unsigned int data; + void __iomem *p; + int i; + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + serial8250_suspend_port(priv->line[i]); + wakeup |= pci1xxxx_port_suspend(priv->line[i]); + } + } + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + + if (wakeup) + writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG); + + iounmap(p); + device_set_wakeup_enable(dev, true); + pci_wake_from_d3(pcidev, true); + + return 0; +} + +static int pci1xxxx_resume(struct device *dev) +{ + struct pci1xxxx_8250 *priv = dev_get_drvdata(dev); + struct pci_dev *pcidev = to_pci_dev(dev); + unsigned int data; + void __iomem *p; + int i; + + p = pci_ioremap_bar(pcidev, 0); + if (!p) { + dev_err(dev, "remapping of bar 0 memory failed"); + return -ENOMEM; + } + + data = readl(p + UART_RESET_REG); + writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG); + iounmap(p); + + for (i = 0; i < priv->nr; i++) { + if (priv->line[i] >= 0) { + pci1xxxx_port_resume(priv->line[i]); + serial8250_resume_port(priv->line[i]); + } + } + + return 0; +} + static int pci1xxxx_setup(struct pci1xxxx_8250 *priv, struct uart_8250_port *port, int idx) { @@ -404,6 +514,9 @@ static void pci1xxxx_serial_remove(struct pci_dev *dev) } } +static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, + pci1xxxx_resume); + static const struct pci_device_id pci1xxxx_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11010) }, { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_PCI11101) }, @@ -418,6 +531,9 @@ static struct pci_driver pci1xxxx_pci_driver = { .name = "pci1xxxx serial", .probe = pci1xxxx_serial_probe, .remove = pci1xxxx_serial_remove, + .driver = { + .pm = pm_sleep_ptr(&pci1xxxx_pm_ops), + }, .id_table = pci1xxxx_pci_tbl, }; module_pci_driver(pci1xxxx_pci_driver);