From patchwork Wed Feb 28 10:35:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 207750 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp3259424dyb; Wed, 28 Feb 2024 02:36:22 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUgjdgzpNaLkpEYKKEJ0PnJIBuRTowfaqU7YZlNgpr1nUM+5gwwRj3ggDgn9QiTlMP5I4Tla2yL8uyatmEB787CeLcDAw== X-Google-Smtp-Source: AGHT+IHVmXKsqULvSeY9JZvTLTejQHteesghqoy/BqxSOQcTkrTFUucrykDm/cMniPfPDl8CI6UH X-Received: by 2002:ac8:7d04:0:b0:42e:6468:6f99 with SMTP id g4-20020ac87d04000000b0042e64686f99mr15322826qtb.6.1709116582126; Wed, 28 Feb 2024 02:36:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709116582; cv=pass; d=google.com; s=arc-20160816; b=HmQLVLHiZczS1u1lTe/rIQaJqf2P/nqP7LQlew2UmoKTzrDl2Eee1YBt6KoKd0QGzq vFObuJ6YXIqxcGVKMKI0Dg4yDkyUMwlMQiIRE4jfCaOZDqiPuA4wMrWoAJfV8/3UPRIA LgLLlEvotOOiVPJ/jEwj4aGViK7OHW9Ab9YeZ8i9yya/fIc6ZFAXacHmbjQ4vxZb6FUU 4bLRbSZF8jAdKnoSCOWTTZVY0/2ZdllGuq1Nu/OHIFqMrBkW9UNmrx5SHjMKLSIUFsD/ qyPan0vpnnxwwKXCqJjcU89gtXsEMTbO847Z8VnvbFcMtOkyFz2kSuUomn3xVrrkUUuy EmDQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=aEzrPsmvCZOVlzuULUW+r0zPhML1xPDPhwG1r6r95v0=; fh=HOahLdxVPwEOTyfS+vjJu5aPtFjN/ZnZsgwt1+wU8BI=; b=JXjPKv2S1LtUED39CBFYqxHTgfi3TYtxkRm0nqy8lxcdsALzsc2rkfhwtaBdkUrbeJ +SQXwJsDIVwUGM6aSfELLRN02FDc+Rmky3yYlZUhg4jJ4aV0Uoq20Mbund+EY/dGfCdO g6BNH1270eCjVcGrAO9Rn6nNvx7rE/xD3u/lJh3kkPVRgPXPWI/H+bIsLCEFp0dTvVht elTyo2XsNa0B74RFKfd8S1eBn+ShI0f6uQ20CDpl3N/9nH7KIi5wFHSAhPZcvt91GvvL KrBR5TC1oLYOL9gxTWNjGpGCz6x/SsH2VhpVIZjg6le0nDoo09Ye1JFfd2fQaCie5Y07 4DAA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dZOl6gZK; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id y23-20020ac85257000000b0042e4cfe8d9csi8993106qtn.199.2024.02.28.02.36.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 02:36:22 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dZOl6gZK; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE16E3858412 for ; Wed, 28 Feb 2024 10:36:21 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by sourceware.org (Postfix) with ESMTPS id 754E43858C52 for ; Wed, 28 Feb 2024 10:35:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 754E43858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 754E43858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709116542; cv=none; b=af8niNiLDPVwmssIw2FVk8Ue44/Q1TrXuTpblD6iuK83L5AUeDcxMXUhuj8TMAv5O7tAbUktyLHfZNwo6N+kfrqFpBuEu5XBFp9ayLCPJoTfBJvZBc2U2a+BnDiAGR1dGbq6p22ol+f5Ji+/TWV6ucuAEVbxHKs120uxI7KFxBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1709116542; c=relaxed/simple; bh=Igh+qWtevGHPzKopYwR1eyTqBz0OkhK/n1ivBXMxgeQ=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=m2TysNzCJEe8cfRsqjVWlH+Lh2PwRkY+JntP6rrSgU+/Cz0HXoo1eVy2xWGUe3LcoYWWIab5vtMvXrsQFF1T1TnCZVlfQ/NapZOTKMuJcfhjpe6wvQbwR8XgIBmRXQnHicLHNua3EXsXjFuIsEhrrr0TR28vFrucfKnxfC2MmgM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709116539; x=1740652539; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Igh+qWtevGHPzKopYwR1eyTqBz0OkhK/n1ivBXMxgeQ=; b=dZOl6gZKwdelEP4hZ847SFjtf64r0zUR0QNMhzsddO0JXPIjnfPr4w/c 6dGRWIWa7brhhHMpO0BQ1an4K6KIM4pxcidBzewbYk3RpRqDRdPOotELw Z3cSH/f/yJuY5THrbvSGA7aZaYb/sR44LBeVwS6R918rYf0F1woMuTAQv 0/WYerqDbdkm7CX8AA2Ty4KsokNQbYvehQJ+tfEk6fE9cgPl5NW+eW3wc qmZpBQ9igovEckYjTTjcZHLTde811TvEDHJB7LIx2KD8jxZk+hjEaFYYK bIVmRFueppsfCcUZ9wOsQEMNCD8y6InUAKXy5/4EQ0EQStN8qZ/QIIkLC Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="7289611" X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="7289611" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2024 02:35:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="11972966" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa003.fm.intel.com with ESMTP; 28 Feb 2024 02:35:35 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 41B661006FFF; Wed, 28 Feb 2024 18:35:34 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, yanzhang.wang@intel.com, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com, Pan Li Subject: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV Date: Wed, 28 Feb 2024 18:35:32 +0800 Message-Id: <20240228103532.2079576-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240223080558.2644800-1-pan2.li@intel.com> References: <20240223080558.2644800-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791676254160017510 X-GMAIL-MSGID: 1792138629426227094 From: Pan Li This patch would like to introduce one new gcc option for RVV. To appoint the bits size of one RVV vector register. Valid arguments to '-mrvv-vector-bits=' are: * scalable * zvl The scalable will pick up the zvl*b in the march as the minimal vlen. For example, the minimal vlen will be 512 when march=rv64gcv_zvl512b and mrvv-vector-bits=scalable. The zvl will pick up the zvl*b in the march as exactly vlen. For example, the vlen will be 1024 exactly when march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl. Given below sample: void test_rvv_vector_bits () { vint32m1_t x; asm volatile ("def %0": "=vr"(x)); asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); asm volatile ("use %0": : "vr"(x)); } With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >= 128) csrr t0,vlenb sub sp,sp,t0 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 csrr t0,vlenb add sp,sp,t0 jr ra With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128) addi sp,sp,-16 def v1 vs1r.v v1,0(sp) vl1re32.v v1,0(sp) use v1 addi sp,sp,16 jr ra The below test are passed for this patch. * The riscv fully regression test. gcc/ChangeLog: * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for different RVV vector bits. * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to get the RVV vector bits, with given min_vlen. (riscv_convert_vector_chunks): Combine the mrvv-vector-bits option with min_vlen to RVV vector chunks. (riscv_override_options_internal): Update comments and rename the vector chunks. * config/riscv/riscv.opt: Add option mrvv-vector-bits. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test. * gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-opts.h | 8 +++++ gcc/config/riscv/riscv.cc | 35 +++++++++++++++---- gcc/config/riscv/riscv.opt | 14 ++++++++ .../riscv/rvv/base/rvv-vector-bits-1.c | 7 ++++ .../riscv/rvv/base/rvv-vector-bits-2.c | 7 ++++ .../riscv/rvv/base/rvv-vector-bits-3.c | 9 +++++ .../riscv/rvv/base/rvv-vector-bits-4.c | 9 +++++ .../riscv/rvv/base/rvv-vector-bits-5.c | 17 +++++++++ .../riscv/rvv/base/rvv-vector-bits-6.c | 17 +++++++++ 9 files changed, 116 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 4edddbadc37..2a311c9d2a3 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -129,6 +129,14 @@ enum vsetvl_strategy_enum { VSETVL_OPT_NO_FUSION, }; +/* RVV vector bits for option -mrvv-vector-bits, default is scalable. */ +enum rvv_vector_bits_enum { + /* scalable indicates taking the value of zvl*b as the minimal vlen. */ + RVV_VECTOR_BITS_SCALABLE, + /* zvl indicates taking the value of zvl*b as the exactly vlen. */ + RVV_VECTOR_BITS_ZVL, +}; + #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT)) /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5e984ee2a55..b6b133210ff 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -8801,13 +8801,33 @@ riscv_init_machine_status (void) return ggc_cleared_alloc (); } -/* Return the VLEN value associated with -march. +static int +riscv_convert_vector_bits (int min_vlen) +{ + int rvv_bits = 0; + + switch (rvv_vector_bits) + { + case RVV_VECTOR_BITS_ZVL: + case RVV_VECTOR_BITS_SCALABLE: + rvv_bits = min_vlen; + break; + default: + gcc_unreachable (); + } + + return rvv_bits; +} + +/* Return the VLEN value associated with -march and -mwrvv-vector-bits. TODO: So far we only support length-agnostic value. */ static poly_uint16 -riscv_convert_vector_bits (struct gcc_options *opts) +riscv_convert_vector_chunks (struct gcc_options *opts) { int chunk_num; int min_vlen = TARGET_MIN_VLEN_OPTS (opts); + int rvv_bits = riscv_convert_vector_bits (min_vlen); + if (min_vlen > 32) { /* When targetting minimum VLEN > 32, we should use 64-bit chunk size. @@ -8826,7 +8846,7 @@ riscv_convert_vector_bits (struct gcc_options *opts) - TARGET_MIN_VLEN = 2048bit: [256,256] - TARGET_MIN_VLEN = 4096bit: [512,512] FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */ - chunk_num = min_vlen / 64; + chunk_num = rvv_bits / 64; } else { @@ -8847,8 +8867,9 @@ riscv_convert_vector_bits (struct gcc_options *opts) compile-time constant if TARGET_VECTOR is disabled. */ if (TARGET_VECTOR_OPTS_P (opts)) { - if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX) - return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8); + if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX + || opts->x_rvv_vector_bits == RVV_VECTOR_BITS_ZVL) + return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8); else return poly_uint16 (chunk_num, chunk_num); } @@ -8920,8 +8941,8 @@ riscv_override_options_internal (struct gcc_options *opts) if (TARGET_VECTOR && TARGET_BIG_ENDIAN) sorry ("Current RISC-V GCC does not support RVV in big-endian mode"); - /* Convert -march to a chunks count. */ - riscv_vector_chunks = riscv_convert_vector_bits (opts); + /* Convert -march and -mrvv-vector-bits to a chunks count. */ + riscv_vector_chunks = riscv_convert_vector_chunks (opts); } /* Implement TARGET_OPTION_OVERRIDE. */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 20685c42aed..bf60dcc8b53 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -607,3 +607,17 @@ Enum(stringop_strategy) String(vector) Value(STRATEGY_VECTOR) mstringop-strategy= Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy) Init(STRATEGY_AUTO) Specify stringop expansion strategy. + +Enum +Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum) +The possible RVV vector register lengths: + +EnumValue +Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE) + +EnumValue +Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL) + +mrvv-vector-bits= +Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits) Init(RVV_VECTOR_BITS_SCALABLE) +-mrvv-vector-bits=zvl Set the number of bits in zvl for an RVV vector register. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c new file mode 100644 index 00000000000..20708460201 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3" } */ + +#include "riscv_vector.h" + +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c new file mode 100644 index 00000000000..54c86ffcc56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=invalid-bits -O3" } */ + +#include "riscv_vector.h" + +/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */ +/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable zvl" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c new file mode 100644 index 00000000000..9c9acebd5e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c @@ -0,0 +1,9 @@ +/* Test that we do not have error when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */ + +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) +{ + for (int i = 0; i < 8; i++) + out[i] = a[i] + b[i]; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c new file mode 100644 index 00000000000..9589bf81296 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c @@ -0,0 +1,9 @@ +/* Test that we do not have error when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */ + +void test_rvv_vector_bits_zvl (int *a, int *b, int *out) +{ + for (int i = 0; i < 8; i++) + out[i] = a[i] + b[i]; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c new file mode 100644 index 00000000000..1f03bbce04f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3" } */ + +#include "riscv_vector.h" + +void test_rvv_vector_bits_zvl () +{ + vint32m1_t x; + asm volatile ("def %0": "=vr"(x)); + asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); + asm volatile ("use %0": : "vr"(x)); +} + +/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c new file mode 100644 index 00000000000..ea762090457 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable -O3" } */ + +#include "riscv_vector.h" + +void test_rvv_vector_bits_scalable () +{ + vint32m1_t x; + asm volatile ("def %0": "=vr"(x)); + asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"); + asm volatile ("use %0": : "vr"(x)); +} + +/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */